TW201445691A - Semiconductor device and manufacturing method of same - Google Patents

Abstract

To provide a semiconductor device of a multi-pin structure using a lead frame. The semiconductor device comprises a tab 1c having a chip supporting surface 1d, the chip supporting surface whose dimension is smaller than a back surface of a semiconductor chip, a plurality of leads arranged around the tab 1c, the semiconductor chip mounted over the chip supporting surface 1d of the tab 1c, a plurality of suspending leads 1e for supporting the tab 1c, four bar leads 1f arranged outside the tab 1c so as to surround the tab 1c and coupled to the suspending leads 1e, a plurality of wires for coupling between the semiconductor chip and the leads, and a sealing body for sealing the semiconductor chip and the wires with resin, with first slits 1g being formed respectively in first coupling portions 1j of the bar leads 1f for coupling with the suspending leads 1e.

Description

Semiconductor device and method of manufacturing same

The present invention relates to semiconductor devices and their manufacturing techniques, and more particularly to an effective technique applied to semiconductor devices assembled using lead frames.

A technique is known in which a ground connection portion is disposed between a semiconductor wafer and an internal lead and electrically connected to a ground pad for a semiconductor wafer by wire bonding; the ground connection portion is formed by The grounding potential is stabilized by electrically connecting to and supporting the suspension wire of the carrier portion (for example, refer to Patent Document 1).

There is also known a technique of using a lead frame having a die pad having a size smaller than that of a semiconductor wafer, and an insulating tape for interconnecting the suspension wire of the lead frame and the internal lead portion (for example, reference patent) Literature 2).

[Patent Document 1] Japanese Patent Laid-Open No. Hei 11-168169

[Patent Document 2] Japanese Patent Laid-Open No. Hei 11-224929

In recent years, with the increase in the performance of semiconductor devices, the number of external terminals (number of pins) for transmitting and receiving data signals between semiconductor devices and external electronic devices has also increased. As a configuration for realizing such a multi-pin semiconductor device, for example, a BGA (Ball Grid Array) is generally known. Since the BGA has a structure as described below, it is suitable for multi-pinning, and this structure is a structure in which a semiconductor wafer is mounted on a main surface of a wiring board and an external terminal (spherical electrode) is provided on the back surface. However, due to the wiring substrate fixture There is a structure in which a plurality of wiring layers and insulating layers are formed. Therefore, the material cost is higher than that of the lead frame, and the manufacturing cost of the BGA is relatively high. Therefore, in recent years, a mechanism for reducing the manufacturing cost of the BGA is considered to be effective by a so-called MAP (Multi Array Package) method, and a plurality of semiconductor devices are formed on one wiring substrate. In the region, after a semiconductor wafer is mounted in each of a plurality of regions, a plurality of regions are collectively sealed with a resin.

However, if the size of each of the BGA products is increased by multi-pinning, the number of products obtained from each of the wiring substrates can be only 4 to 5, and the total number of moldings used is large. When the substrate (the substrate for MAP) is obtained, the manufacturing cost is increased. Therefore, in order to achieve cost reduction, it is effective to use a lead frame type such as a QFP (Quad Flat Package).

If the lead frame is used, since the wiring layer and the insulating layer are not laminated as in the case of the wiring substrate used for the BGA, the manufacturing cost can be reduced.

However, the QFP system can be configured such that a carrier portion of a semiconductor wafer and a plurality of wires are disposed around the carrier portion. In other words, since the lead wires serving as the external terminals are disposed on the peripheral portion of the semiconductor device, the outer dimensions of the semiconductor device are also increased as the multi-pinning progresses.

Therefore, one of the mechanisms for realizing the miniaturization of the semiconductor device and achieving the multi-pinning of the lead frame type semiconductor device is effective as described in the above-mentioned Patent Document 1 (JP-A-H11-168169). As shown in the figure, the number of terminals (external terminals) that are externally pulled out by the power supply and GND (ground) is reduced. In other words, a common conductor called a bus bar or a bar wire is connected, and the wires of the power source or the GND are connected to the bus wires to achieve the commonality of the wires, thereby reducing the number of terminals pulled out to the outside. Pinned.

However, since the lead frame is made of metal, the die bonding step of mounting the semiconductor wafer or the electrical connection of the semiconductor wafer and the wire by wiring is performed. The wire bonding step and the like affect the heat, and the lead frame is prone to expansion and contraction (thermal skew). This expansion and contraction are particularly likely to occur when the lead frame is made of a metal such as a copper alloy. In the wire bonding step, wire bonding is performed in a state where one of the wires (a region outside the portion where the wires are connected) is fixed by the pressing jig (clamp), but the region where the wiring is formed is planarly overlapped. The bus wires are not pressed by the pressing jig, and the wiring is connected to the semiconductor wafer and the wire. For this reason, when the expansion action acts on the lead frame, since both ends of the bus line are fixed to the suspension wire supporting the carrier portion, the horizontal direction cannot be fully expanded, and the bus bar is deflected. In such a state, if the bus bar is connected to the wiring, the 2nd side is not pressed by the pressing jig, and the wiring is not crimped. Moreover, this wiring is not crimped for the cause, and the wiring is peeled off (broken wire).

Further, in the method of fixing the bus bar, it is also conceivable to fix by vacuum suction, but even if vacuum adsorption is performed, it is difficult to sufficiently suppress the deflection of the lead frame; further, it is used in the wiring bonding step. The temperature of the heating platform is uneven due to the vacuum, and the wiring connection is also likely to occur.

Further, since the wiring connected to the wires is required to be joined across the bus bars, if the bus wires are deflected by thermal skew, a problem of short-circuiting of the wires occurs.

Further, as described in the above-described Patent Document 1, if only the bus wires are simply arranged in a ring shape, the thermal fluctuation of the bus wires is synchronized, and the fluctuation of the carrier portion occurs, which also becomes a problem.

Further, since the number of internal wires is increased by multi-pinning, the shape of the front end of the internal wire is tapered, and the rigidity of the internal wire becomes low.

Further, when the number of internal wires is increased by the multi-pinning, the gap between the wires is also reduced, so that the fluidity of the molding resin at the time of resin molding is lowered.

Further, in Patent Document 1 described above, there is described a configuration of a small load-bearing portion having a ground connection portion between the carrier portion and the internal lead. Further, in the above-mentioned Patent Document 2 (JP-A-Heisei No. Hei 11-224929), there is a description of a structure in which a small load-bearing portion structure is used and a bending process is performed on a suspension wire.

However, in the above-mentioned Patent Documents 1 and 2, the countermeasure against the bus wire which is deflected by the expansion and contraction is not described at all, and the expansion and contraction are affected by the heat of the lead frame.

It is an object of the present invention to provide a technique that can be implemented by a multi-pin semiconductor device of a leadframe.

Another object of the present invention is to provide a technique for achieving cost reduction of a semiconductor device.

Another object of the present invention is to provide a technique for achieving an improvement in the reliability of a semiconductor device.

Another object of the present invention is to provide a technique for achieving an improvement in the quality of a semiconductor device.

The above and other objects and novel features of the present invention will be fully understood from the description and appended claims.

Hereinafter, the outline of a representative of the invention disclosed in the application of the present invention will be briefly described.

That is, the present invention has a wafer mounting portion which is smaller in size than the back surface of the semiconductor wafer, and a plurality of wires disposed around the wafer mounting portion, and a semiconductor wafer mounted on the semiconductor wafer a wafer support surface of the wafer mounting portion; a plurality of suspension wires that support the wafer mounting portion; and a rod-shaped common wire that is disposed outside the wafer mounting portion so as to surround the wafer mounting portion, and is connected The wire is suspended; and the first slit is formed in the common wire.

Furthermore, the present invention includes the steps of: preparing a lead frame, comprising: a wafer mounting portion; and a plurality of suspension wires integrally formed with the wafer mounting portion, each having a slit; each of the plurality of wires And a plurality of common wires are respectively located between the wafer mounting portion and the plurality of wires, and are formed integrally with the plurality of suspension wires; a semiconductor wafer on which a main surface of a plurality of electrodes has been formed is mounted on the wafer mounting portion; and the plurality of electrodes of the semiconductor wafer and the plurality of common wires are electrically connected via a plurality of common conductor wires And the plurality of electrodes of the semiconductor wafer and the plurality of wires are electrically connected to each other via a plurality of wires, and the semiconductor wafer, the chip mounting portion, and the plurality of common-conductor wires and the A plurality of wires are wired and sealed with a resin.

1‧‧‧ lead frame

1a‧‧‧Internal conductors (wires)

1b‧‧‧External wire (wire)

1c‧‧‧bearing section (wafer mounting section)

1d‧‧‧ wafer support surface

1e‧‧‧suspension wire

1f‧‧‧ rod wire (common wire)

1f'‧‧‧ plating film (plating layer)

1g‧‧‧1st slit

1h‧‧‧1st internal lead

1i‧‧‧2nd internal conductor

1j‧‧‧1st link

1m‧‧‧1st offset

1n‧‧‧2nd slit

1p‧‧‧2nd offset

1q‧‧‧ tape

1r‧‧‧2nd link

1s‧‧‧3rd slit

1t‧‧‧Snake Department

1u‧‧‧large load bearing unit (wafer mounting part)

1v‧‧‧through hole

1w‧‧‧Extrusion (common wire)

2‧‧‧Semiconductor wafer

2a‧‧‧Main face

2b‧‧‧back

2c‧‧‧ pads (electrodes)

3‧‧‧ Sealing body

4‧‧‧Wiring

4a‧‧‧1st wiring

4b‧‧‧2nd wiring

5‧‧‧Silver glue

6‧‧‧QFP (semiconductor device)

7‧‧‧ potting nozzle

8‧‧‧Adsorption collet

9‧‧‧ Capillary

10‧‧‧Joining platform

10a‧‧‧Adsorption holes

11‧‧‧Clamp

11a‧‧‧Clamping Department

12‧‧‧External plating

13‧‧‧QFP (semiconductor device)

14‧‧‧Shaping mould

14a‧‧‧上模

14b‧‧‧ cavity surface

14c‧‧‧下模

14d‧‧‧ cavity surface

15‧‧‧QFN (semiconductor device)

16‧‧‧SOP (semiconductor device)

17‧‧‧SON (semiconductor device)

18‧‧‧QFN (semiconductor device)

19‧‧‧SON (semiconductor device)

Fig. 1 is a plan view showing an example of a structure of a semiconductor device according to an embodiment of the present invention.

Fig. 2 is a cross-sectional view showing an example of a structure cut along the line A-A of Fig. 1;

Fig. 3 is a cross-sectional view showing an example of a structure cut along the line B-B of Fig. 1;

4 is a cross-sectional view showing an example of a manufacturing process to the completion of wiring bonding in the assembly of the semiconductor device shown in FIG. 1.

Fig. 5 is a cross-sectional view showing an example of a manufacturing process after wiring bonding in the assembly of the semiconductor device shown in Fig. 1.

Fig. 6A is a partial plan view showing an example of a structure of a lead frame used for assembly of the semiconductor device shown in Fig. 1.

Figure 6B is a partially enlarged plan view showing a portion of a lead frame used for assembly of the semiconductor device shown in Figure 6A.

Fig. 7 is a partial plan view showing an example of a structure of a second offset portion of a lead frame used for assembly of the semiconductor device shown in Fig. 1.

Fig. 8 is a cross-sectional view showing an example of a structure cut along the line A-A of Fig. 7.

Fig. 9 is a plan view showing an example of a clamping region at the time of wire bonding in the assembly of the semiconductor device shown in Fig. 1.

Fig. 10 is a cross-sectional view showing an example of a clamping structure at the time of wiring joining in the assembly of the semiconductor device shown in Fig. 1.

Fig. 11 is a partial plan view showing an example of a structure in which the resin is molded in the assembly of the semiconductor device shown in Fig. 1 through the sealing body.

Fig. 12 is a cross-sectional view showing the structure of an assembled lead frame used in a semiconductor device according to a modification of the embodiment of the present invention.

Fig. 13 is a partial plan view showing the structure in which the resin is molded in the assembly of the semiconductor device according to the modification of the embodiment of the present invention.

Fig. 14 is a cross-sectional view showing the structure of a semiconductor device according to a modification of the embodiment of the present invention.

Fig. 15 is a partial cross-sectional view showing an example of a structure in which a mold of a mold is clamped in the case where a lead frame without offset is used in the embodiment of the present invention.

Fig. 16 is a partial plan view showing an example of a structure of an assembled lead frame used in a semiconductor device using a large carrying portion in an embodiment of the present invention.

Fig. 17 is a partial plan view showing an example of a structure in which the resin is molded in the assembly of the semiconductor device using the lead frame shown in Fig. 16 through the sealed body.

Fig. 18 is a cross-sectional view showing an example of the structure of the semiconductor device shown in Fig. 17.

Fig. 19 is a partial plan view showing an example of a structure in which a lead frame having a slit is provided in a common wire in the embodiment of the present invention.

Fig. 20 is a cross-sectional view showing an example of a structure cut along the line A-A of Fig. 19.

Fig. 21 is an enlarged plan view showing an example of a structure of a slit forming portion in the lead frame shown in Fig. 19.

Figure 22 is a view showing a group of semiconductor devices using the lead frame shown in Figure 19 through a sealed body. A partial plan view of an example of a structure in which the resin in the package is molded.

Fig. 23 is a cross-sectional view showing an example of a structure cut along the line A-A of Fig. 22;

Fig. 24 is an enlarged partial plan view showing an example of a configuration of a slit forming portion in the configuration shown in Fig. 22.

Fig. 25 is an enlarged partial plan view showing the configuration of a modification of the mechanism for alleviating the stress on the common wire in the embodiment of the present invention.

Fig. 26 is a partial plan view showing the configuration of a modification of the mechanism for relaxing the stress on the common wire in the lead frame of the embodiment of the present invention.

Fig. 27 is a partial plan view showing the configuration of a modification of the mechanism for relieving the stress on the common wire in the lead frame of the embodiment of the present invention.

Fig. 28 is a view showing the structure of a semiconductor device (QFN) according to a modification of the embodiment of the present invention, wherein (a) is a plan view, (b) is a cross-sectional view, and (c) is a rear view.

Fig. 29 is a view showing the structure of a semiconductor device (SOP) according to a modification of the embodiment of the present invention, wherein (a) is a plan view, (b) is a cross-sectional view, and (c) is a rear view.

Fig. 30 is a view showing the structure of a semiconductor device (SON) according to a modification of the embodiment of the present invention, wherein (a) is a plan view, (b) is a cross-sectional view, and (c) is a rear view.

Fig. 31 is a view showing the structure of a semiconductor device (QFN) according to a modification of the embodiment of the present invention, wherein (a) is a plan view, (b) is a cross-sectional view, and (c) is a rear view.

32 is a view showing the structure of a semiconductor device (SON) according to a modification of the embodiment of the present invention, wherein (a) is a plan view, (b) is a cross-sectional view, and (c) is a rear view.

[Effects of the Invention]

Hereinafter, among the inventions disclosed in the application of the present application, the effects obtained by the representative will be briefly described.

A rod-shaped common wire that is connected to the suspension wire is disposed outside the wafer mounting portion so as to surround the wafer mounting portion, and a slit is formed in the common wire, even when The expansion due to the influence of heat ‧ the contraction acts on the common wire, and the expansion and sag effect can be alleviated by the slit, and the deflection (deformation) due to the expansion and contraction of the common wire can be reduced.

In this way, it is possible to prevent the occurrence of wiring peeling, and it is also possible to wire the common wires. As a result, the fabrication of a multi-lead semiconductor device on the lead frame can be realized.

Furthermore, by using a lead frame for manufacturing, it is possible to achieve a cost reduction of a semiconductor device.

Further, since the deflection due to the expansion and contraction of the common wire can be reduced, the occurrence of the wiring short circuit can be reduced. As a result, the reliability and quality of the semiconductor device can be improved.

In the following embodiments, when it is necessary, it is divided into plural sections or implementation types for explanation, but unless otherwise specified, the parties are not related to each other, and one party is The relationship between some or all of the other variants, details, supplementary explanations, and the like. In addition, in the following embodiments, the case of the number of elements, including the number, the numerical value, the quantity, the range, and the like, except for the case where it is specifically indicated and the case where the specific number is clearly defined in principle, etc. It is not limited to the specific number, and may be set to a specific number or more or less.

In addition, in the following embodiments, the constituent elements (including the element steps, etc.) are not necessarily necessary except for the case where it is specifically indicated and the case where it is obviously necessary in principle, and this is not necessarily a problem.

Similarly, in the following embodiments, when the shape, the positional relationship, and the like of the constituent elements and the like are referred to, the shape is substantially included and the shape is included unless otherwise specified and the case is not apparent in principle. Etc. Approximate or similar. This matter is the same as the above numerical values and ranges.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings. again In the entire drawings for explaining the embodiments, the same reference numerals will be given to those having the same functions, and the description thereof will be omitted.

(Embodiment) FIG. 1 is a plan view showing an example of a structure of a semiconductor device according to an embodiment of the present invention; and FIG. 2 is a cross-sectional view showing an example of a structure cut along a line AA of FIG. 1; FIG. 4 is a cross-sectional view showing an example of a structure which is cut along the line BB of FIG. 1; FIG. 4 is a cross-sectional view showing an example of a manufacturing process for completing wiring bonding in the assembly of the semiconductor device shown in FIG. 1; Fig. 1 is a cross-sectional view showing an example of a manufacturing process after wiring bonding in the assembly of the semiconductor device shown in Fig. 1. 6A is a partial plan view showing an example of a structure of a lead frame used for assembly of the semiconductor device shown in FIG. 1. FIG. 6B is a partially enlarged plan view showing a portion of a lead frame used for assembly of the semiconductor device shown in FIG. 6A. Fig. 7 is a partial plan view showing an example of a structure of a second offset portion of a lead frame used for assembly of the semiconductor device shown in Fig. 1. Fig. 8 is a view showing an example of a structure cut along the line AA of Fig. 7. Sectional view. 9 is a plan view showing an example of a clamping region at the time of wiring bonding in the assembly of the semiconductor device shown in FIG. 1. FIG. 10 is a view showing a clamping structure at the time of wiring bonding in the assembly of the semiconductor device shown in FIG. FIG. 11 is a partial plan view showing an example of a structure in which a resin is molded in the assembly of the semiconductor device shown in FIG. 1 through a sealing body.

12 is a cross-sectional view showing a structure of a lead frame used for assembling a semiconductor device according to a modification of the embodiment of the present invention; and FIG. 13 is a semiconductor showing a modified example of the embodiment of the present invention. A plan view of a structure in which a resin is molded in the assembly of the device; and FIG. 14 is a cross-sectional view showing a structure of a semiconductor device according to a modification of the embodiment of the present invention.

The semiconductor device of the present embodiment is a surface-mount type which is assembled using a lead frame and has a multi-pin, and has a common wire to which a power source and a GND are connected. As an example, a QFP 6 will be described.

The configuration of the semiconductor device (QFP6) will be described with reference to Figs. 1 to 3 . By inheritance a carrier (wafer mounting portion) 1c, a plurality of wires, a semiconductor wafer 2, and a plurality of suspension wires 1e, and the carrier portion (wafer mounting portion) 1c has a wafer supporting surface 1d capable of supporting the semiconductor wafer 2, and the wafer The outer dimension of the support surface 1d is smaller than the back surface 2b of the semiconductor wafer 2; and the plurality of wires are disposed around the carrier portion 1c; and the semiconductor wafer 2 is mounted on the wafer support surface 1d of the carrier portion 1c. And the plurality of suspension wires 1e support the carrier portion 1c. Further, the QFP 6 has a rod-shaped common wire which is disposed on the outer side of the carrier portion 1c so as to surround the carrier portion 1c and is connected to the suspension wire 1e; the first wiring 4a is a semiconductor wafer 2 pads (electrodes) 2c are electrically connected to the wires; second wires 4b are electrically connected to the pads 2c of the semiconductor wafer 2 and the common wires; and a sealing body 3 is a semiconductor wafer 2. The first wiring 4a and the second wiring 4b are sealed by a resin.

Further, the configuration of the semiconductor device (QFP6) will be described with reference to FIGS. 6A and 6B, and include a wafer mounting portion (support portion, die pad) 1c having a wafer capable of supporting the semiconductor wafer 2. The support surface 1d is provided, and the outer dimension of the wafer support surface 1d is smaller than the back surface 2b of the semiconductor wafer 2. Further, a plurality of suspension wires 1e are formed integrally with the wafer mounting portion 1c, and slits (first slits 1g) are provided in each. Further, the semiconductor wafer 2 is provided with a main surface 2a on which a plurality of pads (electrodes) 2c have been formed, and is mounted on the wafer mounting portion 1c. Further, a plurality of wires (internal wires 1a) are provided, which are provided around the semiconductor wafer 2. Further, a plurality of common conductors (bus bars, rod wires) 1f including a plurality of rods are respectively located between the wafer mounting portion 1c and the plurality of wires (internal wires 1a), and the plurality of suspension wires 1e are respectively In addition, a plurality of wires (the first wire 4a and the wire wire) 4 are electrically connected to the plurality of wires 2c of the semiconductor wafer 2 and the plurality of wires (the inner wires 1a). By. In addition, the wiring (the second wiring 4b and the common conductor wiring) 4 is electrically connected to the plurality of electrodes 2c of the semiconductor wafer 2 and the plurality of rod-shaped common conductors 1f. Further, the sealing body 3 is included, and the semiconductor wafer 2, the wafer mounting portion 1c, and the plural are included The wiring (the first wiring 4a and the second wiring 4b) 4 is sealed. Further, a plurality of external wires 1b including a plurality of wires (internal wires 1a) are integrally formed, and the sealing bodies 3 are respectively exposed.

Further, each of the plurality of wires has a plurality of internal wires 1a embedded in the inside of the sealing body 3, and a plurality of external wires 1b exposed to external terminals outside the sealing body 3, and It is bent into a wing shape. The inner wire 1a is integrally connected to the outer wire 1b.

Further, in the QFP 6, as shown in Figs. 6A and 6B, a rod-shaped elongated common wire (rod wire 1f) is provided in a region between the carrier portion 1c and the front end of the plurality of internal wires 1a.

Further, the slit (through hole, hole) in the present embodiment means a configuration in which one portion of the lead frame (suspended wire 1e) 1 is excluded; by this means, the stress applied to the lead frame 1 is alleviated. effect.

Further, in the present embodiment, the width of the rod-shaped common wire (rod wire) 1f is formed to be thinner than the width of the suspension wire 1e (including the total width of the first slit 1g and the second slit 1n). . For this reason, the length of the first wire 4a can be shortened compared to the case where the width of the common wire 1f is thicker than the width of the suspension wire 1e, and the pad (electrode) 2c of the semiconductor wafer 2 is The internal wire 1a corresponding thereto is electrically connected. As a result, the signal transmission speed can be increased. Moreover, in the resin sealing step, it is possible to suppress short-circuit defects of the wiring due to the resin flow in the wiring 4.

The rod wire 1f is a wire which can be connected to the wiring 4 of the pad 2c which is common to the power source and the GND. Further, both end portions of the rod wire (common wire, bus wire) 1f are integrally formed with the adjacent suspension wire 1e. Therefore, in the semiconductor wafer 2, signals from the pads of the increased power source and GND are shared in the package, whereby the wires (internal wires, external wires) can be made in comparison with the number of pads. Since the number is reduced, it is very effective as a mechanism for suppressing an increase in the package size. And the semiconductor wafer 2 is electrically For the purpose of improving the characteristics, it is necessary to use multiple power supplies and GND pads.

In the QFP 6, the rod wire 1f corresponds to each of the four sides of the semiconductor wafer 2, and four strips are provided, each of which extends along the direction in which the front ends of the plurality of inner leads 1a are arranged, and the respective rods are arranged. Both ends of the wire 1f are connected to the suspension wire 1e, and are provided along the diagonal direction of the main surface 2a of the semiconductor wafer 2. Therefore, the rod wire 1f is formed in a square frame shape around the carrier portion 1c.

By forming the square frame shape by the rod wire 1f, the wiring of the power source or the GND 4 can be connected in four directions. Further, the flow balance of the molding resin in the four directions can be made approximately uniform.

Further, in the QFP 6, as shown in FIGS. 6A and 6B, the first slit 1g is formed in each of the rod wires 1f. That is, the first slit 1g is formed in the first joint portion 1j of the rod wire 1f and the suspension wire 1e.

In the suspension wire 1e, as a mechanism for relieving stress, a plurality of slits (first slit 1g and second slit 1n) are formed; and the first slit 1g will be described in detail as follows. That is, as shown in FIG. 6B, the first slit 1g is provided so as to extend to a portion connected to the end portion of the common wire (rod wire, bus wire) 1f in the suspension wire 1e. In other words, the slit (the first slit 1g) which is a mechanism for relieving the stress is formed in the suspension wire 1e, and is formed in the extension of the common wire 1f indicated by the dash L (imaginary line) at 2 o'clock in Fig. 6B. on-line.

Further, in the slit (through hole, hole) of this embodiment, the suspension wire 1e is partially cut out. As will be described in detail, as shown in FIG. 3, the main surface of the suspension wire 1e (the surface on the same side as the main surface 2a of the semiconductor wafer 2) faces the back surface (the same side as the back surface 2b of the semiconductor wafer 2). Through hole (hole) through which the surface is penetrated.

In this manner, the rod wire 1f connected to the suspension wire 1e is disposed on the outer side of the carrier portion 1c so as to surround the carrier portion 1c, and is formed in the first connection portion 1j of the bar wire 1f and the suspension wire 1e. 1 sew 1g, in this way, even if the expansion ‧ shrinkage (thermal skew) effect due to heat acts on the rod wire 1f, by providing the first slit 1g, Expansion and contraction are alleviated.

As will be briefly explained, it is as follows. That is, the common wire 1f is expanded in the wiring bonding step even by the influence of the heat of the bonded bonding platform 10, since the common wire (rod wire, bus wire) is connected in the suspension wire 1e. The portion of the end portion of 1f is formed into a slit (first slit 1g), so that the suspension wire 1e is deformed, but the expansion of the suspension wire 1e is not hindered.

In this way, the rod wire 1f can be reduced in deformation, and the variation of the carrier portion 1c connected via the suspension wire 1e can be reduced.

Further, the outer side of the wiring joining region at the front end of the inner lead 1a is adhered to the tape material 1q of the annular film, and is used for preventing adhesion and deformation of the inner lead 1a.

In the QFP6 type small load-bearing portion structure of the present embodiment (the load-bearing portion 1c having a smaller outer shape than the semiconductor wafer 2), the size of the mounted semiconductor wafer 2 can be made versatile and the solder reflow resistance can be improved.

Further, in the assembly of the QFP 6, for example, a lead frame made of a copper alloy (see FIGS. 6A and 6B) 1 is used. Therefore, the carrier portion 1c, the plurality of internal wires 1a and the external wires 1b, the four suspension wires 1e, and the rod wires 1f are made of a copper alloy. Further, in each of the plurality of internal wires 1a and the four bar wires 1f, silver plating is applied to a region where the wiring 4 is connected, and a plating film (plating layer) 1f' is formed.

By forming the plating film (electroplating layer) 1f', the connectivity of the wiring 4 made of gold and the internal wiring 1a made of copper can be improved. Further, although not shown, a portion of the inner lead 1a to which the distal end portion (wiring 4) is connected is also plated with silver to form a plating film (plating layer) 1f'.

Further, the semiconductor wafer 2 is composed of, for example, tantalum, and a plurality of pads 2c serving as electrodes are formed on the principal surface 2a. The back surface 2b is bonded to the carrier portion 1c via a die bonding material, and the semiconductor wafer 2 is supported by the carrier portion 1c.

Moreover, the wiring 4 including the first wiring 4a and the second wiring 4b is, for example, a gold wire. Further, the sealing resin forming the sealing body 3 is, for example, a thermosetting epoxy resin. Next, other features of the QFP 6 will be described.

As shown in FIG. 3, FIG. 6A, and FIG. 6B, in the QFP 6, the four suspension wires 1e are formed on the inner side of the first connection portion 1j of the bar wire 1f by the bending process. Offset portion 1m.

By forming the first offset portion 1m, it is possible to prevent fluctuations in the position (position) of the carrier portion 1c, which is caused by thermal skew or thermal deformation of the rod wire 1f. In other words, even if thermal skew or thermal deformation occurs in the rod wire 1f, the influence is absorbed by the first offset portion 1m and absorbed, so that it is not transmitted to the carrier portion 1c, and as a result, the carrier portion 1c can be prevented. Change of place (location).

Further, by forming the first offset portion 1m, it is versatile for wafer thickness difference products having different thicknesses of the semiconductor wafer 2. In other words, by adjusting the amount of shift of the first offset portion 1m, the amount of resin on the upper side and the lower side of the semiconductor wafer 2 can be adjusted, making it possible to adjust the resin balance.

Here, the details of the positional relationship between the first offset portion 1m and the common conductor (bar conductor, bus conductor) 1f will be described below. Fig. 15 is a partial cross-sectional view showing an example of a structure when clamped by a mold of a mold is used in the case of using a lead frame without offset in the embodiment of the present invention.

First, when the lead frame 1 of the first offset portion 1m is not formed in the suspension wire 1e, as shown in Fig. 15, the cavity surface from the upper mold 14a in the molding die 14 (resin molding die) is used. The interval X between the 14b and the main surface 2a of the semiconductor wafer 2 is narrower than the interval Y from the cavity surface 14d of the lower mold 14c to the back surface of the carrier portion 1c in the molding die 14 (resin molding die).

For this reason, in the resin sealing step, the amount of resin transferred to the back side of the carrier portion 1c is larger than the amount of resin transferred onto the main surface 2a of the semiconductor wafer 2, so that the resin is unevenly distributed. The semiconductor wafer 2 is mounted by the unevenness of the resin balance The carrier portion 1c is pushed upward, and a problem arises in which one portion of the wiring 4 is exposed from the upper surface of the sealing body 3 or a problem that the wiring 4 is broken.

Therefore, in the present embodiment, as shown in FIG. 3, FIG. 6A, and FIG. 6B, the first offset portion 1m is formed in the suspension wire 1e. In short, the bending process is performed from the main surface of the suspension wire 1e toward the back surface. In this way, the resin can be made to be approximately uniform.

Here, in the present embodiment, the first offset portion 1m is formed on the side of the carrier portion 1c in the suspension wire than the portion where the end portion of the common wire 1f is connected. By forming the first offset portion 1m between the carrier portion 1c and the common conductor 1f, even if thermal skew or thermal deformation occurs in the common conductor 1f, the influence is alleviated by the first offset portion 1m. Therefore, it is difficult to transmit to the carrying portion 1c, and as a result, fluctuations in the position (position) of the carrying portion 1c can be suppressed.

Further, the offset amount of the first offset portion 1m is, for example, 0.24 mm.

Further, in the QFP 6, as shown in FIGS. 6A and 6B, a plurality of internal wires 1a connected to the rod wires 1f are provided among the plurality of internal wires 1a. The plurality of internal wires 1a connected to the rod wire 1f have: a first inner wire 1h; a second inner wire 1i adjacent to the first inner wire 1h; and a second connecting portion 1r which is attached to the rod The end of the wire 1f side connects the first inner wire 1h to the second inner wire 1i.

In other words, the inner lead 1a connected to the rod lead 1f is composed of the first inner lead 1h, the second inner lead 1i, and the second connecting portion 1r. The second connecting portion 1r is disposed between the tip end of each of the first inner lead 1h and the second inner lead 1i on the side of the rod lead 1f and the rod lead 1f.

In this manner, the second connecting portion 1r is disposed between the tip end of the inner lead 1a on the side of the rod wire 1f and the rod lead 1f. Here, the front end of the inner lead 1a is a tapered region. Therefore, by providing the second connecting portion 1r, the rigidity of the front end side of the first inner lead wire 1h and the second inner lead wire 1i can be secured, and the second connecting portion 1r connects the first inner lead wire 1h and the second inner portion. Wire 1i.

Further, as shown in FIGS. 6A and 6B, each of the first inner lead 1h and the second inner lead 1i The ends from the outer side (external wire side) are different from each other and are not joined as the side of the rod wire 1f.

By this means, in the resin sealing step, the fluidity (flow velocity) of the molding resin passing through the region can be made approximately equal: the region where the first inner conductor 1h and the second inner conductor 1i have been formed, and other forms have been formed The area of the inner wire 1a. In other words, between the first inner conductor 1h and the second inner conductor 1i which are branched, the resin which flows between the molding resin and the other inner conductor 1a flows approximately uniformly, thereby ensuring the flow of the molding resin. Sex becomes roughly equal. In this way, it is possible to prevent the wiring from floating, the deformation of the carrier portion 1c, the occurrence of voids, and the like.

Further, as shown in FIG. 3, FIG. 6A, and FIG. 6B, the second slit 1n is formed on each of the four suspension wires 1e at a position outside the first connection portion 1j of the bar wire 1f. In this way, the flow rate of the molding resin flowing in during the resin injection can be made uniform, and the wiring floating, the deformation of the bearing portion 1c, the occurrence of voids, and the like can be prevented.

To explain in more detail, the four suspension wires 1e are provided to support the carrier portion 1c. However, as in the present embodiment, when the size (size) of the load-bearing portion 1c is smaller than the outer size (size) of the semiconductor wafer 2 (small load-bearing portion configuration), the size ratio is smaller than that of the load-bearing portion 1c. In the case where the outer shape of the semiconductor wafer 2 is large (the large load-bearing portion structure), the length of each of the suspension wires 1e also becomes long. When the shape of the suspension wire 1e is simply elongated, in the resin sealing step, the suspension wire 1e is deflected by the injection pressure of the resin, and the position (position) of the carrier portion is changed.

Therefore, as shown in Figs. 6A and 6B, the rigidity of the suspension wire 1e is increased by forming the width of the suspension wire 1e to be thick. Further, as shown in FIG. 3, FIG. 6A, and FIG. 6B, the second slit (through hole, hole) 1n is formed in the suspension wire 1e. The reason is as follows.

The lead frame 1 of the present embodiment is, for example, a thin plate member made of a copper alloy, and the adhesion between the lead frame 1 and the molding resin (sealing body 3, resin) is compared with, for example, a crucible. The adhesion of the semiconductor wafer 2 to the shaped resin is low. For this reason, if the width of the suspension wire 1e is simply formed thick, the interface between the sealing body 3 formed by the resin sealing step and the lead frame (especially, the suspension wire 1e) is peeled off, so that the semiconductor device is made. The reliability is reduced. Therefore, by forming the slit (the second slit 1n) in the suspending wire 1e, the resin formed in the slit becomes an anchoring effect, and the sealing body 3 and the lead frame (suspended wire 1e) can be lifted. The adhesion. Further, by providing slits in the suspension wires 1e, the density of the wires in the vicinity of the sides of the semiconductor wafer 2 and the density of the wires in the vicinity of the corners of the semiconductor wafer 2 can be made approximately uniform, and the semiconductor wafer 2 is planar. The shape is composed of a quadrangle. In this way, since the flow velocity of the resin flowing in the vicinity of the suspension wire 1e and the flow velocity of the resin flowing in the vicinity of the plurality of wires (the inner wire 1a) are approximately uniform, the respective flow rates are not generated. Large differences can suppress the decline in resin equilibrium.

Here, if only the decrease in the equilibrium of the above-mentioned suppression resin is focused, only one slit which is larger than the slit (the first slit 1g and the second slit 1n) shown in FIG. 6A is formed in the suspension. The hanging wire 1e can also be used. However, as in the present embodiment, when the size (size) of the load-bearing portion 1c is smaller than the outer size (size) of the semiconductor wafer 2, the length of each of the suspension wires 1e is compared with the configuration of the large load-bearing portion. It has also grown. For this reason, in the case of the lead frame 1 having such a small load-bearing portion structure, if a larger slit is formed in the suspension wire 1e, the rigidity of the suspension wire 1e may be lowered. Therefore, as shown in FIG. 6A, by dividing the slit into a plurality of pieces and forming the suspension wire 1e, the rigidity of the suspension wire 1e can be suppressed from decreasing.

Further, the slit (the first slit 1g and the second slit 1n) has a width which is thicker than the width of each of the suspension wires 1e divided by the slit. In this way, the respective shapes of the divided suspension wires 1e can be matched to the shape of the adjacent inner wires 1a. For this reason, it is possible to suppress a large fluctuation in the flow velocity of the resin flowing from the inner wire 1a toward the suspension wire 1e (or from the suspension wire 1e toward the inner wire 1a).

Further, on the surface of the rod wire 1f, silver plating is applied as the crimping of the wiring 4, On the other hand, a plating film (electroplated layer) 1f' is formed, but it is not completely applied to the rod wire 1f, and is formed only in one of the respective portions (for example, the outer side portion of the bar wire 1f of Figs. 6A and 6B). Although the silver plating has a low adhesion to the molding resin, as shown in FIGS. 6A and 6B, the rod wire 1f is not comprehensive, and the plating film 1f' is formed only in the region where the wiring 4 is connected. In this way, the adhesion between the molding resin and the rod wire 1f can be improved, and the reliability and quality of the semiconductor device can be improved.

That is, the adhesion between the silver plating and the molding resin is lower than the adhesion between the lead frame 1 made of a copper alloy and the molding resin, but it can be suppressed by forming only the region where the wiring 4 is connected. The adhesion of the molding resin to the lead frame 1 (common wire 1f) is lowered.

As shown in Fig. 7, among the four bar wires 1f arranged in a rectangular frame shape, the second offset portion 1p as shown in Fig. 8 is formed in the following bar wire 1f, and the bar wire 1f is The portion other than the both ends is not connected to the front end of the inner wire 1a.

The second offset portion 1p is a skew buffer for clamping the internal lead 1a by the jig 11 (see FIGS. 4 and 10) during wire bonding. That is, as shown in Fig. 9, at the time of wire bonding, the rod wire 1f is not clamped by the jig 11, and only the inner wire 1a is clamped. In this case, when the inner wire 1a is clamped, the bar wire 1f connected to the inner wire 1a is fixed among the four bar wires 1f, so that it is difficult to be affected by the skew; as a result, the skew is concentrated. The rod wire 1f is deformed by the rod wire 1f which is not connected to the inner wire 1a, and the rod wire 1f is floated from the joining platform 10 shown in Fig. 10.

Therefore, as a countermeasure against the floating of the rod wire 1f, the bar wire 1f which is not connected to the inner wire 1a at a portion other than the both ends is subjected to the offset processing as shown in Fig. 8, by which, When the wiring is joined, the rod wire 1f can be brought into close contact with the bonding platform 10. That is, the adhesion of the rod wire 1f to the joining platform 10 can be ensured.

Further, as an example of the portion where the offset processing is performed, it is preferable to form the second offset portion 1p in a region where the rod wire 1f is not connected to the internal wire 1a, and in the example shown in Fig. 7, it is formed. Near or near the ends of the rod wire 1f.

Further, in the QFP 6 of the present embodiment, the rod wire 1f which is not connected to the front end of the internal lead wire 1a at a portion other than the both ends is one of the four bar wires 1f.

Further, the offset amount (T) of the second offset portion 1p of the rod wire 1f shown in Fig. 8 is, for example, about 0.05 mm which can be formed by imprint processing. Therefore, the offset amount (0.05 mm) of the second offset portion 1p of the rod wire 1f is much smaller than the offset amount (0.24 mm) of the first offset portion 1m of the suspension wire 1e.

Further, in the QFP 6, the internal lead wire 1a of the region of the rod wire 1f which is not connected to the internal lead wire 1a is a wire group for signal, and a wire group connected to the outside is disposed in this region. Therefore, the connection of the rod wire 1f to the inner wire 1a in this region becomes difficult.

Further, as shown in FIG. 2, in the QFP 6, the circuit heights are different in connection with the adjacent internal wires 1a or the adjacent wires 4 of the bar wires 1f and the internal wires 1a. In other words, in the QFP 6, the wiring 4 (the first wiring 4a) is connected to the internal lead 1a beyond the rod lead 1f, and the wiring length is lengthened, so that wiring contact failure is likely to occur.

Therefore, by changing the loop height between adjacent wirings, it is possible to prevent the occurrence of wiring contact.

Next, the assembly of the QFP 6 of this embodiment will be described in accordance with the process flow chart shown in FIGS. 4 and 5.

First, the preparation of the lead frame shown in step S1 of Fig. 4 is performed. As shown in FIG. 6A and FIG. 6B, the lead frame 1 is provided with four bar wires (common wires) 1f around the small load-bearing portion (bearing portion 1c), and the two ends are connected to the suspension wires 1e, respectively. Further, the first slit 1g is formed in the first joint portion 1j of the suspension wire 1e.

As described in detail, the lead frame 1 is prepared, as shown in FIGS. 6A and 6B, and includes a wafer mounting portion (bearing portion, die pad) 1c, and a plurality of suspension wires 1e, which are mounted on the wafer. The portions 1c are integrally formed, and each of the slits (first slit 1g) is provided; a plurality of wires (internal wires 1a) are provided around the wafer mounting portion 1c; and a common wire (rod wire) , the bus wire) 1f, which is located in the wafer mounting portion 1c and the plural Between the wires (internal wires 1a), the plurality of suspension wires 1e are formed integrally with each other.

Further, in the lead frame 1, the slit (the first slit 1g) as a mechanism for relieving the stress is provided in a portion where the end portion of the common wire 1f is connected to the suspension wire 1e. In other words, the slit (the first slit 1g) which is a mechanism for relieving the stress is formed on the extension line of the common wire 1f indicated by the broken line (imaginary line) of FIG. 6B in the suspension wire 1e.

Further, in each of the internal wires 1a, an annular tape member 1q is adhered to the outer side of each of the wire bonding portions.

Further, among the four bar wires 1f, the three bar wires 1f are connected to the plurality of internal wires 1a via the second connecting portion 1r at the respective end portions in the vicinity of the center; The one bar wire 1f is not connected to the inner wire 1a near the center thereof. In the rod wire 1f which is not connected to the inner lead 1a in the vicinity of the center, the second offset portion 1p as shown in Fig. 8 is formed.

Further, the plurality of inner leads 1a are respectively branched at the front end opposite to the bar lead 1f, and the plurality of inner leads 1a are connected to the front end of the rod lead 1f side by the second connecting portion 1r, and are connected via the second connecting portion 1r. The connecting portion 1r is connected to the rod wire 1f.

Further, in each of the suspension wires 1e, the first offset portion 1m is formed inside the first connection portion 1j of the bar wire 1f.

Further, the lead frame 1 is, for example, a thin plate member composed of a copper alloy.

Thereafter, the die bonding shown in step S2 of Fig. 4 is performed. First, the silver paste 5 is applied from the potting nozzle 7 on the carrier portion 1c. After the application, the main surface 2a of the semiconductor wafer 2 is adsorbed and held by the adsorption type collet 8, and is placed on the carrier portion 1c, and the semiconductor wafer 2 is fixed to the carrier portion 1c by the silver paste 5. As shown in FIG. 6A and FIG. 6B, the first offset portion 1m is formed on the inner side (the side of the carrier portion 1c) of the first connecting portion 1j of the rod lead 1f. When the semiconductor wafer 2 of a relatively large size is mounted on the carrying portion 1c, if a collet is used, one of the collet members is offset from the first one. The transfer portion 1m is in contact with the crucible, and the collet is formed by a pyramid shape that maintains the outer edge of the semiconductor wafer 2. However, as in the case of the present embodiment, when the suction type cartridge 8 is used, since the main surface 2a of the semiconductor wafer 2 is held and held, the semiconductor wafer 2 is mounted on the carrier portion 1c. The collet 8 is lowered, and one portion of the collet 8 is not in contact with the first offset portion 1m.

Thereafter, the wiring bonding shown in step S3 is performed. First, as shown in FIG. 10, the lead frame 1 is placed on the bonding platform 10, and then the back surface 2b of the semiconductor wafer 2 is evacuated via the adsorption hole 10a, and the semiconductor wafer 2 is adsorbed and fixed to the bonding platform. At the same time, the lead frame 1 is fixed by pressing the tape 1q of the inner lead 1a from the upper portion of the lead frame 1 by the clamp portion 11a of the jig 11. The clamp portion 11a of the jig 11 presses the loop-shaped tape material 1q from above over the entire circumference.

In short, this wiring bonding step is performed in a state in which the lead frame 1 on which the semiconductor wafer 2 has been mounted is disposed on the heated bonding stage 10, and each of the plurality of wires (internal wires 1a) is held by the jig 11 .

Here, the reason why the common wire 1f is not held by the jig 11 is that the shape of the jig 11 is formed in a ring shape in the portion where the wire is pressed as shown in FIGS. 9 and 10 . Further, when the common wire 1f is held by the jig 11 having such a shape, the front end portion (wiring connection region) of the inner wire 1a is covered with the jig 11, and therefore, it is difficult to apply a plurality of pads (electrodes) of the semiconductor wafer 2. 2c is connected to a plurality of internal wires 1a by wiring (first wiring 4a, wire harness wiring) 4.

In this way, all of the internal wires 1a are clamped by the clamp portion 11a when the wires are joined. In this case, as shown in Figs. 9 and 10, the rod wires 1f and 4 are not clamped.

In this state, as shown in FIG. 4, the capillary 9 is used for wire bonding. Here, for example, as shown in FIG. 10, the signal pad 2c of the semiconductor wafer 2 and the signal internal lead 1a are electrically connected by the first wiring 4a, and the second wiring is provided by the second wiring. The wire 4b electrically connects the pad 2c for the power supply (or GND) of the semiconductor wafer 2 to the bar wire 1f.

In this case, in connection with the adjacent inner lead 1a or the adjacent wiring 4 of the rod lead 1f and the inner lead 1a, the loop height is changed to perform wire bonding. The occurrence of wiring contact can be prevented by changing the loop height between such adjacent wirings.

In the present embodiment, in consideration of the occurrence of the above-described wiring contact, the pad 2c for the power supply (or GND) of the semiconductor wafer 2 is connected to the wiring (the second wiring 4b and the common wiring for wiring) having a low loop height. After the rod lead wire 1f is electrically connected, the signal pad 2c of the semiconductor wafer 2 and the signal inner lead wire 1a are electrically connected by a wiring having a high loop height (the first wiring 4a and the wire harness).

Further, in the QFP 6, three of the four bar wires 1f are connected to the inner wire 1a in the vicinity of the center. Therefore, in the wire bonding step, the three bar wires 1f are less likely to be deformed by heat, but in the case of the bar wire 1f which is not connected to the inner wire 1a in the vicinity of the center, the thermal skew is easily concentrated and easily deformed. However, in the case of the rod wire 1f which is not connected to the inner lead wire 1a in the vicinity of the center, the second offset portion 1p is formed as shown in Fig. 8. Therefore, the bar wire 1f can be adhered to the joint platform at the time of wire bonding. 10.

In the assembly of the semiconductor device (QFP6) of the present embodiment, the first slit 1g is formed in the first connecting portion 1j of the rod lead 1f and the suspension lead 1e, and in this way, even during the wiring bonding The expansion of the influence of heat ‧ shrinkage (heat skew) acts on the rod wire 1f, but by the first slit 1g, the expansion and contraction can be alleviated.

As a result, the deflection (deformation) due to the expansion and the contraction of the rod wire 1f can be reduced, and the occurrence of peeling of the wiring can be prevented.

Thereafter, the resin is molded and baked as shown in step S4 of Fig. 5 . Here, the semiconductor wafer 2, the rod wire 1f, the plurality of internal wires 1a, and the plurality of wires 4 are resin-sealed by plasticization or the like to form a sealing body 3 as shown in FIG. .

Thereafter, external plating is performed as shown in step S5. Here, the exterior plating 12 is formed on the external lead 1b exposed from the sealing body 3.

Thereafter, the cutting and forming shown in step S6 is performed. Here, the cutting and bending of the outer lead 1b are performed, and the assembly of the QFP 6 is completed.

Here, the importance of the first slit 1g in the QFP 6 of the present embodiment will be described, and it is formed in the first connecting portion 1j of the rod wire 1f and the suspension wire 1e.

The inventors of the present invention found that, in the case where the rod wire 1f is applied to the QFP 6, if a slit is not formed at the joint portion of the rod wire 1f and the suspension wire 1e, the semiconductor device (QFP6) is at the following point. The manufacturing system has become difficult. That is, the length of the suspension wire 1e is lengthened by adopting the small load-bearing portion structure, and as a result, the suspension wire 1e is easily deflected, but as one of the countermeasures, it is conceivable to make the suspension wire 1e The width becomes thicker and the rigidity is increased.

On the other hand, in the case of a semiconductor wafer requiring a plurality of pads for power sources and GND for the purpose of improving electrical characteristics, the number of external terminals is increased, and the package size is also increased. Therefore, in order to suppress the package size from becoming large, the rod wire 1f becomes required. At this time, since the rod wire 1f is not held by the jig (clamp 11) at the time of wire bonding, the suspension wire 1e is fixed at both ends thereof, thereby ensuring the stability of the bar wire 1f. .

However, the lead frame 1 made of a metal such as a copper alloy is easily expanded by the influence of heat. For this reason, the both ends of the rod wire itself are stretched by expansion, but at this time, the suspension wire is suspended. 1e is formed thicker in order to increase the rigidity, thereby hindering the phenomenon that the rod wire 1f is stretched by expansion.

As a result, the rod wire 1f is deflected.

Therefore, by forming the first slit 1g in the first joint portion 1j of the rod wire 1f and the suspension wire 1e, the expanded bar wire 1f can be opened, and the bar wire 1f can be prevented from being bent (deformed). . In other words, in the manufacture of the multi-lead semiconductor device (QFP6) using the lead frame 1, the first slit 1g is formed in the first connecting portion 1j of the rod lead 1f and the suspended lead 1e. important.

In the QFP 6 of the present embodiment, the rod wire 1f connected to the suspension wire 1e is disposed on the outer side of the carrier portion 1c so as to surround the carrier portion 1c, and is suspended from the bar wire 1f. The first connecting portion 1j of the lead wire 1e forms the first slit 1g, and by this means, even if the expansion/contraction (thermal skew) action due to the influence of heat acts on the rod wire 1f, the first slit can be used. 1g while relaxing expansion ‧ contraction

In this way, the deflection (deformation) due to the expansion and the contraction of the rod wire 1f can be reduced, and the occurrence of wiring peeling can be prevented.

Further, if the suspension wire 1e is formed thicker, the bar wire 1f is prevented from being stretched by expansion, and the fluidity (flow velocity) of the resin flowing in the vicinity of the suspension wire 1e is arranged and plural. The area of the inner lead 1a is different, and therefore, a void is easily formed inside the formed sealed body 3.

However, as in the present embodiment, by forming the first slit 1g first, the thickness of the suspension wire 1e can be formed to be approximately the same as the thickness of the inner wire 1a, so that the inner wire 1a can be formed. The fluidity (flow velocity) of the resin flowing through the portion and the suspension wire 1e portion is approximately equal, and the occurrence of voids can be suppressed.

Therefore, wiring bonding to the rod wire 1f is also possible.

As a result, the manufacture of the QFP 6 using the multi-pin of the lead frame 1 can be realized.

Furthermore, since the lead frame 1 is used for manufacturing, the cost of the QFP 6 can be reduced.

Further, since the deflection due to the expansion and the contraction of the rod wire 1f can be reduced, the occurrence of the wiring short circuit can be reduced. As a result, the reliability and quality of QFP6 can be improved.

Next, a modification of the present embodiment shown in FIGS. 12 to 14 will be described.

Fig. 14 is a view showing a semiconductor device according to a modification of the present embodiment, and as shown in Fig. 12, a QFP 13 having a large load-bearing portion 1u structure in which the size of the wafer mounting portion is larger than that of the semiconductor wafer 2 is displayed.

In this QFP13, it is extruded from the semiconductor wafer 2 of the large carrier 1u. The portion 1w is a common wire, and the wiring 4 such as a power source and a GND is connected to the extrusion portion 1w of the large carrier portion 1u to achieve commonality of the wires.

In other words, in the QFP 6 shown in FIGS. 1 to 3, the modified QFP 13 is formed by removing the rod wire 1f in order to completely suppress the thermal distortion of the rod wire 1f, and adopts a large load portion (than the semiconductor wafer 2). In place of the rod wire 1f, the extrusion portion 1w is used as a common wire, and the wiring 4 such as a power source and a GND is connected to the extrusion portion 1w.

In this case, the adhesion between the lead frame 1 made of a copper alloy and the sealing resin is lower than that of the semiconductor wafer 2 composed of tantalum and the sealing resin, and is in the large load-bearing portion 1u and Peeling is likely to occur at the interface of the resin for sealing. For this reason, if the large load-bearing portion 1u is used, the contact area between the large load-bearing portion 1u and the sealing resin is increased, and the contact area between the semiconductor wafer 2 and the sealing resin is lower than that of the small-bearing portion structure. The problem of the above-mentioned peeling failure has become more remarkable. Therefore, as shown in FIG. 12 and FIG. 13, a plurality of through holes 1v are formed in the large carrier portion 1u, and the sealing resin passes through the through holes 1v to raise the area where the semiconductor wafer 2 and the sealing resin are in contact with each other. Even if the large load-bearing portion 1u is used, the problem of peeling occurring at the interface between the sealing resin and the large load-bearing portion 1u can be suppressed.

Further, although not shown, in the large carrier portion 1u, silver plating is applied to the region where the wiring 4 is connected to form a plating film (plating layer). Since the adhesion between the silver plating and the molding resin is relatively low, the adhesion between the molding resin and the large load-bearing portion 1u can be improved by not being fully applied to the bearing portion, so that the semiconductor device can be realized. Reliability and quality improvement.

In the modified example QFP13, since the rod wire 1f is not provided, it is possible to prevent the connection portion (extrusion portion 1w) of the power source or the GND second wire 4b from being bent.

Further, as shown in Fig. 13, by connecting the front end of a part of the internal lead 1a to the large carrying portion 1u, the large carrying portion 1u is fixed, so that the large carrying portion 1u can be prevented from rotating in the horizontal direction.

In the above, according to the embodiment of the invention, the invention developed by the inventors will be made. The present invention is not limited to the embodiments of the invention described above, and various changes can be made without departing from the spirit and scope of the invention.

For example, in the above-described embodiment, the following is an example in which the number of the rod wires 1f which are connected to the internal wires 1a in the vicinity of the center of each of the four bar wires 1f is three. However, the number of the rod wires 1f that are connected to the inner lead wires 1a in the vicinity of the respective centers is not limited to three, and may be three.

Further, in the above-described embodiment, the semiconductor wafer 2 is adsorbed and held by the adsorption type collet 8. However, the present invention is not limited thereto, and the outer diameter of the semiconductor wafer 2 is as viewed from the rod wire 1f. In the case of a relatively small case, it is also possible to use a collet composed of a pyramid shape for the portion of the semiconductor wafer 2.

Further, in the above-described embodiment, the semiconductor device having the small carrier portion structure will be described, but the invention is not limited thereto. For example, when the deflection of the common wire (rod wire or bus wire) 1f is suppressed, the lead frame 1 including the wafer mounting portion (bearing portion, die pad) 1c as shown in FIG. 16 is used. As shown in FIGS. 17 and 18, the wafer mounting portion (bearing portion, die pad) 1c may have an outer size (size) of the wafer supporting surface 1d of the semiconductor wafer 2 than the back surface 2b of the semiconductor wafer 2. The bigger one.

In the above-described embodiment, the suspension wire 1e is provided with a slit (first slit 1g) at a portion where the end portion of the common wire 1f is connected, thereby suppressing the common wire. 1f is deflected by the influence of the heat of the joining platform 10, but is not limited thereto. For example, as shown in Fig. 19, Fig. 20 and Fig. 21, the lead frame 1 provided with slits (through holes, holes) for 1 s may be used, and the slits (through holes, holes) 1s are used for common wires (rods). A part of the wire (conductor wire) 1f (central part) that relieves stress. In this case, the area where the wiring (second wiring 4b) 4 can be connected to the common conductor 1f is smaller than that of the above-described embodiment. However, if the number of pads (electrodes) 2c of the semiconductor wafer 2 is smaller than that of the above-described embodiment, as shown in FIGS. 22, 23, and 24, it is possible to use the slit (the third slit). The connection wiring 4 is connected to the side of 1s). Furthermore, in Fig. 24, it is easy to confirm in the slit (the third slit The wiring 4 is connected to the side of 1s), and the number of the wirings 4 connecting the pad 2c of the semiconductor wafer 2 and the internal lead 1a is omitted.

Further, in the above-described embodiment, the following description will be made: the slit (the first slit 1g) is in the suspension wire 1e as shown by the two-dotted line L (imaginary line) of FIG. 6B. It is formed on the extension line of the common wire 1f, but is not limited thereto. If the heat of the joining platform 10 on the wire joining step is lower than the temperature used in the above embodiment, the expansion of the common wire 1f becomes difficult to cause compared to the foregoing embodiment. For this reason, for example, as shown in FIG. 25, the slit (the first slit 1g) may be formed at the position where the suspension wire 1e is farther away from the extension line L of the common wire 1f. Part 1c.

Further, in the above-described embodiments and modifications, the following description will be made on the case where the suspension wire 1e or the common wire 1f is used as a mechanism for relieving stress, but the slit is not limited thereto. For example, as shown in Fig. 26, a part of the common wire 1f, or as shown in Fig. 27, may have a serpentine shape at both ends of the common wire. Even in such a configuration, the common wire 1f is expanded by the influence of heat, but since the meandering portion 1t is contracted, the deflection of the common wire 1f can be suppressed.

Further, in the above-described embodiment, the case where the configuration of the invention of the present invention is applied to a QFP type semiconductor device and a method of manufacturing the same is described, and the QFP type semiconductor device is a plurality of external wires 1b from the sealing body 3 The side surface is protruded, but is not limited thereto. For example, it can be applied to a semiconductor device of a QFN (Quad Flat Non-leaded Package) type 15, as shown in FIG. 28(a) and FIG. 28(b). As shown in Fig. 28(c), the carrier portion 1c and the common conductor 1f are located inside the sealing body 3, and only a plurality of wires (the external wires 1b) are exposed from the lower surface (mounting surface, back surface) of the sealing body 3.

Further, a case where the configuration of the invention of the present invention is applied to a QFP type semiconductor device and a method of manufacturing the same will be described, and a QFP type semiconductor device is provided with a plurality of wires along four sides of the sealing body 3, and the sealing body The 3 series planar shape is composed of a quadrangle, but is not limited thereto, and is applied as shown in FIGS. 29(a), 29(b), and 29(c). SOP (Small Outline Package) type 16 or SON (Small Outline Non-leaded Package) as shown in Fig. 30 (a), Fig. 30 (b), and Fig. 30 (c) The semiconductor device of the SOP 16 type, the carrier portion 1c and the common wire 1f are located inside the sealing body 3, and a plurality of wires are arranged along the two sides of the sealing body 3.

Further, the present invention is not limited thereto, and may be applied to a semiconductor device of a QFN (Quad Flat Non-leaded Package) type 18, as shown in FIG. 31(a), FIG. 31(b) and FIG. As shown in FIG. 31(c), the carrier portion 1c, the common wire 1f, and a plurality of wires (the external wires 1b) are exposed from the lower surface (mounting surface, back surface) of the sealing body 3. Further, as applied to a semiconductor device of the SON (Small Outline Non-leaded Package) type 19, as shown in FIGS. 32(a), 32(b) and 32(c), The carrier portion 1c, the common conductor 1f, and a plurality of wires (the external wires 1b) are exposed from the lower surface (mounting surface, back surface) of the sealing body 3.

[Industrial availability]

The present invention is well suited for use in electronic devices assembled using lead frames and their assembly.

1‧‧‧ lead frame

1a‧‧‧Internal conductors (wires)

1c‧‧‧bearing section (wafer mounting section)

1d‧‧‧ wafer support surface

1e‧‧‧suspension wire

1f‧‧‧ rod wire (common wire)

1f'‧‧‧ plating film (plating layer)

1g‧‧‧1st slit

1h‧‧‧1st internal lead

1i‧‧‧2nd internal conductor

1j‧‧‧1st link

1m‧‧‧1st offset

1n‧‧‧2nd slit

1q‧‧‧ tape

1r‧‧‧2nd link

Claims (19)

A semiconductor device comprising: a wafer mounting portion; and a semiconductor wafer mounted on the wafer mounting portion, comprising: a main surface; a first electrode formed on the main surface; and a second electrode formed on the main surface And a back surface opposite to the main surface; a plurality of suspension wires supporting the wafer mounting portion; and a plurality of common wires disposed in a periphery of the wafer mounting portion in a plan view; and a plurality of wires In a plan view, the first wiring is electrically connected to the plurality of common wires, and the plurality of second wires are the same as the second wiring. The plurality of second electrodes are electrically connected to the plurality of wires, and the sealing body seals the semiconductor wafer, the plurality of first wires, and the plurality of second wires; and the wafer mounting portion and the plurality of suspensions The hanging wire, the plurality of common wires, and the plurality of wires comprise a metal mainly composed of copper; and each of the plurality of common wires is in a plan view. Disposed between the suspension wires of the plurality of suspension wires adjacent to each other; each of the plurality of common wires is disposed between the wafer mounting portion and the plurality of wires in a plan view; each of the plurality The common wire is connected to the first portion of each of the plurality of suspension wires; and the first portion of each of the plurality of suspension wires is formed with a slit; Each of the plurality of common conductors is formed in a linear shape; the first portion of each of the plurality of suspension wires is formed, and the slits not formed in the plurality of common conductors are located in the plurality of common conductors Extension line. The semiconductor device according to claim 1, wherein the wafer mounting portion has a size smaller than that of the semiconductor wafer in a plan view. The semiconductor device according to claim 2, wherein each of the plurality of suspension wires includes a first offset portion formed closer to a second portion of the wafer mounting portion than the first portion. The semiconductor device of claim 2, wherein the first common conductor of the plurality of common conductors is connected to the first one of the plurality of conductors. The semiconductor device of claim 4, wherein the second common conductor of the plurality of common conductors is not connected to the plurality of conductors, and the second common conductor includes a second offset portion. A semiconductor device comprising: a wafer mounting portion; and a semiconductor wafer mounted on the wafer mounting portion, comprising: a main surface; a plurality of first electrodes formed on the main surface; and a plurality of the main surfaces formed on the main surface a second electrode and a back surface opposite to the main surface; a plurality of suspension wires supporting the wafer mounting portion; and a plurality of common wires disposed in a periphery of the wafer mounting portion in a plan view; The lead wire is disposed in the periphery of the wafer mounting portion in plan view a plurality of first wirings electrically connecting the plurality of first electrodes and the plurality of wires, and the plurality of second wires electrically connecting the plurality of second electrodes and the plurality of common wires The sealing body is configured to seal the semiconductor wafer, the wafer mounting portion, the plurality of first wirings, and the plurality of second wirings; and the plurality of common conductors are disposed on the wafer in plan view Between the mounting portion and the plurality of wires; and each of the plurality of common wires is disposed between the suspension wires adjacent to each other among the plurality of suspension wires and connected to the adjacent ones in plan view a first portion of each of the plurality of suspension wires; wherein, in a plan view, each of the suspension wires has a slit in the interior of the suspension wire in a width direction of the suspension wire, and the slit is formed in the suspension wire The first region of the first portion is included; the slit includes a portion formed in a joint region of the corresponding suspension wire and the adjacent common wire. The semiconductor device according to claim 6, wherein the wafer mounting portion, the plurality of suspension wires, the plurality of common wires, and the plurality of wires comprise copper. The semiconductor device according to claim 6, wherein the wafer mounting portion has a size smaller than that of the corresponding semiconductor wafer in a plan view. The semiconductor device of claim 6, wherein each of the plurality of common wires is formed in a straight line shape. The semiconductor device of claim 6, wherein Each of the plurality of suspension wires includes a first offset portion formed closer to a second portion of the wafer mounting portion than the first portion. The semiconductor device of claim 6, wherein the first common conductor of the plurality of common conductors is connected to the first one of the plurality of conductors. The semiconductor device according to claim 11, wherein the second common conductor of the plurality of common conductors is not connected to the plurality of conductors, and the second common conductor includes a second offset portion. A semiconductor device comprising: a wafer mounting portion; and a semiconductor wafer mounted on the wafer mounting portion, comprising: a main surface; a plurality of first electrodes formed on the main surface; and a plurality of the main surfaces formed on the main surface a second electrode and a back surface opposite to the main surface; a plurality of suspension wires supporting the wafer mounting portion; and a plurality of common wires disposed in a periphery of the wafer mounting portion in a plan view; The plurality of wires are disposed around the wafer mounting portion in a plan view, and the plurality of first wires are electrically connected to the plurality of first electrodes and the plurality of wires, and the plurality of wires are electrically connected to the plurality of wires. The second electrode of the plurality of electrodes and the plurality of common wires are electrically connected to each other; and the sealing body seals the semiconductor wafer, the wafer mounting portion, the plurality of first wires, and the plurality of second wires; Each of the plurality of common wires is disposed on the wafer in a plan view Between the plurality of wires and the plurality of wires, wherein each of the plurality of common wires is disposed between the suspension wires adjacent to each other among the plurality of suspension wires and connected to each other in a plan view a first portion of the plurality of suspension wires; wherein, in a plan view, each of the suspension wires has a slit in the interior of the suspension wire in a width direction of the suspension wire, and the slit is in a thickness of the suspension wire Extending through the suspension wire in a direction, and the slit is formed in a first region of the suspension wire including the first portion; the slit includes a portion formed in the corresponding suspension wire and adjacent The junction area of the aforementioned common wire is connected. The semiconductor device of claim 13, wherein the wafer mounting portion, the plurality of suspension wires, the plurality of common wires, and the plurality of wires comprise copper. The semiconductor device according to claim 13, wherein the wafer mounting portion has a size smaller than that of the corresponding semiconductor wafer in a plan view. The semiconductor device of claim 13, wherein each of the plurality of common wires is formed in a straight line shape. The semiconductor device according to claim 13, wherein each of the plurality of suspension wires includes a first offset portion formed closer to a second portion of the wafer mounting portion than the first portion. The semiconductor device of claim 13, wherein the first common conductor of the plurality of common conductors is connected to the first one of the plurality of conductors. The semiconductor device of claim 18, wherein the second common conductor of the plurality of common conductors is not connected to the plurality of conductors The second common wire is connected and includes a second offset portion.