CN102194797A - Square flat leadless packaging structure capable of avoiding electromagnetic interference and manufacturing method thereof - Google Patents
Square flat leadless packaging structure capable of avoiding electromagnetic interference and manufacturing method thereof Download PDFInfo
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- CN102194797A CN102194797A CN2010101365921A CN201010136592A CN102194797A CN 102194797 A CN102194797 A CN 102194797A CN 2010101365921 A CN2010101365921 A CN 2010101365921A CN 201010136592 A CN201010136592 A CN 201010136592A CN 102194797 A CN102194797 A CN 102194797A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
The invention discloses a square flat leadless packaging structure capable of avoiding electromagnetic interference and a manufacturing method thereof. The square flat leadless packaging structure capable of avoiding electromagnetic interference comprises a lead frame, a chip, a bonding wire, packaging colloid and a shielding film, wherein the lead frame is provided with a chip seat, a plurality of support parts connected with the chip seat and a plurality of guide pins which surround the chip seat and are not connected with the chip seat; the packaging colloid wraps the chip, the bonding wire and the lead frame and exposes the sides and bottom surfaces of the guide pins and the bottom surface of the chip seat; and the shielding film is arranged at the top surface and side surface of the packaging colloid and electrically connected with the support parts so as to shield electromagnetic interference through the shielding film. Moreover, the invention also provides a manufacturing method of the square flat leadless packaging structure capable of avoiding electromagnetic interference.
Description
Technical field
The present invention relates to a kind of encapsulating structure and method for making thereof, particularly relate to a kind of square flat non-leaded package that can avoid electromagnetic interference (Quad Flat Non Leaded Package, QFN) and method for making.
Background technology
Semiconductor package part is as chip bearing member with lead frame (Lead Frame), and this lead frame comprises a chip carrier and be formed at this chip carrier a plurality of lead foots on every side, adhering chip on this chip carrier, and after electrically connecting this chip and lead foot with bonding wire, coat the inner segment of this chip, chip carrier, bonding wire and lead foot with packing colloid again and form the semiconductor package part of this tool lead frame.
Except that the semiconductor package part of conventional wires frame type, also develop the square flat non-leaded package that to dwindle the overall semiconductor package size, it is characterized in that not having the outer lead foot that protrudes out packing colloid, and can dwindle overall dimensions.On the other hand, semiconductor package part is when operation, and what can be disturbed by extraneous electromagnetism noises such as (EMI), cause the electrical operation function of this semiconductor package part undesired, therefore the whole electrical functionality of influence.
Because existing semiconductor package part is subject to the problem of electromagnetic interference, and just like United States Patent (USP) the 5th, 166, be disclosed in the structure that is embedded into metal cap in the packing colloid No. 772.
See also Fig. 1, it is a United States Patent (USP) the 5th, 166, the three-dimensional cross-sectional schematic of No. 772 encapsulating structure; As shown in the figure, be on substrate (substrate) 10, to connect to put chip 11, and this chip 11 is electrically connected to this substrate 10 with many bonding wires 12, and outside this chip 11, be covered with a netted metal cap (metal shield) 13, and has at least one earth terminal 14 on this substrate 10, make this metal cap 13 be electrically connected to this earth terminal 14, in addition, at this metal cap 13, chip 11, bonding wire 12, and formation packing colloid 15 on the part substrate 10, so that this metal cap 13 is embedded in this packing colloid 15, and the operation of covering this chip 11 of outside electromagnetic interference by this netted metal cap 13, thereby can avoid electrical operation function undesired, and the whole electrical functionality of influence.Other similar encapsulating structures of electromagnetic interference design of avoiding comprise United States Patent (USP) the 4th, 218,578,4,838,475,4,953,002 and 5,030, and No. 935 disclosed contents.
But above-mentioned existing structure must be made earlier netted metal cap 13 separately, thereby increases the complexity of technology; Afterwards, again this metal cap 13 is covered on this chip 11, and this metal cap 13 is fixed on this substrate 10, like this then increase the degree of difficulty of assembling.In addition, after this netted metal cap 13 covers on this substrate 10, when on this metal cap 13, chip 11, bonding wire 12 and part substrate 10, forming packing colloid 15, this packing colloid 15 must can be covered on this chip 11 by netted metal cap 13, because this metal cap 13 is netted, when the fine and closely woven mesh of this packing colloid 15 by this metal cap 13, be easy to generate turbulent flow, cause bubble to produce, therefore easily in this packing colloid 15, produce bubble, and in subsequent thermal technology, produce popcorn effect.
Other sees also Fig. 2; it is a United States Patent (USP) the 5th; 557; the three-dimensional cross-sectional schematic of No. 142 encapsulating structure; be on substrate 20, to connect to put chip 21; and this chip 21 is electrically connected to this substrate 20 with many bonding wires 22; on this chip 21, bonding wire 22 and part substrate 20, form packing colloid 23 again; to protect this chip 21, bonding wire 22 and substrates 20 by this packing colloid 23; and the exposed surface at this packing colloid 23 forms metal level 24 with sputter, thereby to cover outside electromagnetic interference by this metal level 24.Other similar encapsulating structures of electromagnetic interference design of avoiding comprise United States Patent (USP) the 5th, 220,489,5,311,059 and 7,342, and No. 303 disclosed contents.
But, above-mentioned existing structure, though can exempt complicated manufacturing process, but must on this substrate 20, finish to connect and put chip 21 and packing colloid 23, and after cutting list (singular) and becoming single encapsulating structure, can form metal level 24 at the exposed surface coating or the sputter of this packing colloid 23, and this single encapsulating structure is difficult for the discharging pickup in manufacturing process, thereby is unfavorable for a large amount of productions.Moreover the mode of sputter also can't be applied to the encapsulating structure that packing colloid flushes with substrate side.
In addition, as United States Patent (USP) the 7th, 030, No. 469 disclosed a kind of encapsulating structure, it is to form the groove that exposes outside bonding wire on packing colloid, and be formed with the conductor layer that is connected with this bonding wire on this groove and the packing colloid, to reach the effect of ELECTROMAGNETIC OBSCURANT, still, this conductor layer is required to be non-ferrous metal material, and only can be covered on groove and the packing colloid with deposition or sputtering way, can't be applied to the encapsulating structure that packing colloid flushes with substrate side.Moreover this conductor layer is that point contacts with this bonding wire, and the problem of loose contact is easily arranged.
Therefore, in view of the above-mentioned problems, how to obtain to avoid the square flat non-pin packaging part of electromagnetic interference, the real problem that has become present anxious desire solution.
Summary of the invention
Many disadvantages in view of above-mentioned prior art, main purpose of the present invention provides a kind of square flat non-leaded package that can avoid electromagnetic interference, produce turbulent flow to improve, and cause the problem of popcorn effect because of the fine and closely woven mesh of metal cap easily makes packing colloid.
Another object of the present invention provides a kind of square flat non-leaded package that can avoid electromagnetic interference, can significantly improve the loose contact problem that prior art utilization bonding wire is done a contact.
For reaching above-mentioned target, the invention provides a kind of square flat non-leaded package that can avoid electromagnetic interference, comprise: lead frame has support portion and a plurality of lead foot that is located on around this chip carrier and does not connect this chip carrier of chip carrier, a plurality of these chip carriers of connection; Chip connects and places on this chip carrier; Bonding wire electrically connects this chip and reaches respectively this lead foot; Packing colloid coats this chip, bonding wire and lead frame, and exposes outside this lead foot side and bottom surface and chip carrier bottom surface; And shielding film, be located at the end face and the side of this packing colloid and electrically connect this support portion.
The present invention also provides a kind of method for making that can avoid the square flat non-leaded package of electromagnetic interference, comprise: prepare a metal support body, comprise a plurality of lead frames and a plurality of intercell connector that distributes in length and breadth, respectively this lead frame has support portion and a plurality of lead foot that is located on around this chip carrier and does not connect this chip carrier of chip carrier, a plurality of these chip carriers of connection, wherein, respectively this lead frame connects this intercell connector by described support portion and lead foot; On the chip carrier of this lead frame respectively, connect and put chip, and with corresponding respectively this lead foot that electrically connects of bonding wire; Form packing colloid coating this intercell connector, chip, bonding wire, chip carrier, lead foot and support portion, and expose outside the bottom surface of this intercell connector, chip carrier and lead foot; Carry out cutting the first time along this intercell connector respectively, cutting this packing colloid, in this packing colloid, to form a plurality of respectively grooves of this intercell connector and part support portion that expose; In this packing colloid surface and groove, form shielding film, electrically connect described support portion to make this shielding film; And along this groove respectively and respectively this intercell connector carry out cutting the second time, cutting this shielding film and metal support body, thereby make this shielding film coat this packing colloid side, and flush with the side of this lead foot and support portion.
Described shielding film can be formed in the exposed surface and described groove of this packing colloid by screen painting, and solidify this shielding film, perhaps, this covers film formed method, comprise: in described groove, splash into carbonaceous material or containing metal powder body material, to form first shielding film; On the exposed surface of this packing colloid and first shielding film in the described groove, form second shielding film; And solidify this first shielding film and second shielding film.
As from the foregoing, the present invention can avoid the square flat non-leaded package and the method for making thereof of electromagnetic interference, be on the chip carrier of each lead frame of this metal support body, to connect to put chip, and electrically connect this chip and described lead foot with bonding wire, then at this metal support body, form packing colloid on chip and the bonding wire, described intercell connector along this metal support body carries out cutting the first time then, to cut this packing colloid, in this packing colloid, to form a plurality of grooves of cutting apart in length and breadth, in packing colloid surface of having cut apart and groove, form shielding film again, carry out cutting the second time along this groove respectively more afterwards, to cut shielding film and the intercell connector in this groove, to make this shielding film be formed at the side of this packing colloid, method of the present invention can cut single before the formation by groove dexterously, thereby contact with intercell connector and insert the ELECTROMAGNETIC OBSCURANT material therein, and reach the effect of electromagnetic shielding, and be beneficial to a large amount of productions.
In addition, form the shielding film of tool capability of electromagnetic shielding by groove, can avoid the fine and closely woven mesh of metal cap to make packing colloid produce turbulent flow easily, produce the popcorn effect cause and have because of bubble, moreover, for face contacts, significantly improve the loose contact problem that prior art utilization bonding wire is done a contact between shielding film and the support portion.
Description of drawings
Fig. 1 is a United States Patent (USP) the 5th, 166, No. 772 encapsulating structure three-dimensional cutaway view;
Fig. 2 is a United States Patent (USP) the 5th, 557, No. 142 encapsulating structure three-dimensional cutaway view;
Fig. 3 A to Fig. 3 E can avoid the cross-sectional schematic of method for making of the square flat non-leaded package of electromagnetic interference for the present invention, wherein, and the A-A dotted line cutaway view that this Fig. 3 A ' is Fig. 3 A; This Fig. 3 D-1 and Fig. 3 D-2 are another embodiment of Fig. 3 D.
The main element symbol description:
10,20 substrates
11,21 chips
12,22 bonding wires
13 metal caps
14 earth terminals
15,23 packing colloids
24 metal levels
3 encapsulating structures
30 metal support bodys
The 301a lateral connection bar
The 301b longitudinal bond strip
301 intercell connectors
31 lead frames
311 chip carriers
312 support portions
313 lead foots
301c, 311a, 312a, 313a, 3131 end faces
301d, 311b, 312b, 313b bottom surface
3130 extensions
32 chips
33 bonding wires
34 packing colloids
340 grooves
341 sides
35 shielding films
351 first shielding films
352 second shielding films
The d degree of depth
T thickness
W1 cuts width for the first time
W2 cuts width for the second time
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the content that this specification disclosed.
See also Fig. 3 A to Fig. 3 E, be a kind of method for making that can avoid the square flat non-leaded package of electromagnetic interference provided by the present invention.
Shown in Fig. 3 A and Fig. 3 A ', this Fig. 3 A is the vertical view of Fig. 3 A '.As shown in the figure, at first, preparing one is the metal support body 30 of copper, this metal support body 30 comprises a plurality of lead frames 31 and the intercell connector of being made up of a plurality of lateral connection bar 301a and a plurality of longitudinal bond strip 301b 301, and respectively this lead frame 31 has support portion 312 and a plurality of lead foot 313 that is located on around this chip carrier 311 and does not connect this chip carrier 311 of chip carrier 311, this chip carrier 311 of a plurality of connection, and described again support portion 312 and lead foot 313 connect this intercell connector 301.
Above-mentioned lead foot 313 has corresponding end face 313a and bottom surface 313b, and this lead foot 313 also has an extension 3130, and the thickness of this extension 3130 is less than this lead foot 313 respectively, thereby make the end face 3131 of this extension 3130 and this lead foot 313 end face 313a form section difference structure, usually, the end face 3131 of this extension 3130 or a section difference structure can remove part metals through etching, with the thickness that makes this extension 3130 less than this lead foot 313 respectively.
In addition, describe in detail with regard to previous embodiment again, as shown in Figure 3A, respectively the support portion 312 of this lead frame 31 can be connected to the intersection point of lateral connection bar 301a and longitudinal bond strip 301b from chip carrier 311, and this lead foot 313 is to connect intercell connectors 301 and connection-core bar 311 not by extension 3130.Again, the thickness of above-mentioned support portion 312 is less than this chip carrier 311.Particularly, the bottom surface 312b of this support portion 312 and this chip carrier 311 bottom surface 311b and intercell connector 301 bottom surface 301d form section difference structure.Certainly, also can make the end face 312a of support portion 312 not flush or the section of formation difference structure,, and be not limited to previous embodiment so that the thickness of support portion 312 is less than this chip carrier 311 with this chip carrier 311 end face 311a and intercell connector 301 end face 301c.And this section difference structure can form through etching.
Shown in Fig. 3 B, on the end face 311a of the chip carrier 311 of this lead frame 31 respectively, connect and put chip 32, and be electrically connected to respectively the end face 313a of this lead foot 313 and the end face 311a of chip carrier 311 with bonding wire 33 correspondences, wherein, chip carrier 311 be ground connection electrically.Then, also form packing colloid 34 coating this intercell connector 301, chip 32, bonding wire 33, chip carrier 311, lead foot 313 and support portion 312, and expose outside the bottom surface (301d, 311b, 313b) of this intercell connector 301, chip carrier 311 and lead foot 313.
Shown in Fig. 3 C, carry out cutting the first time along the center line of this intercell connector 301 respectively, to cut this packing colloid 34, a plurality ofly expose the respectively groove 340 of this intercell connector 301 and part support portion 312 in this packing colloid 34, to form, and this depth d that cuts for the first time is more than or equal to the thickness t of this packing colloid 34.Particularly, the groove 340 that is formed at this intercell connector 301 and 312 junctions, support portion exposes respectively this intercell connector 301 and part support portion 312, just the depth of cut d of this section electrically connects described support portion 312 greater than the shielding film that the thickness t of this packing colloid 34 is beneficial to follow-up formation, the groove 340 depth of cut d of its elsewhere only expose respectively this intercell connector 301 then less than the thickness t of this packing colloid 34.In addition, the width of the groove that forms 340 is greater than this intercell connector 301.
Shown in Fig. 3 D, in the surface of this packing colloid 34 and groove 340, form shielding film 35 in mode as screen painting, the material of this shielding film 35 is carbonaceous material or containing metal powder body material, and make this shielding film 35 electrically connect described support portion 312, and behind screen painting, be cured, so can prevent that this chip 32 is subjected to outside electromagnetic interference by covering of this shielding film 35, thereby so that normal operation to be provided.
Other sees also Fig. 3 D-1 and Fig. 3 D-2, it is for forming another embodiment of this shielding film 35, in described groove 340, splash into liquid carbonaceous material or containing metal powder body material earlier with different being in of previous embodiment, to form first shielding film 351, shown in Fig. 3 D-1; Then, on the exposed surface of this packing colloid 34 and first shielding film 351 in the described groove 340, form second shielding film 352, shown in Fig. 3 D-2; This first shielding film 351 of final curing and second shielding film 352, and form this shielding film 35.
Shown in Fig. 3 E, the center line of the intercell connector 301 in this groove 340 respectively carries out cutting the second time, to cut this shielding film 35 and metal support body 30, and the width w2 that this cuts for the second time is less than this width w1 that cuts for the first time, make this shielding film 35 coat the side 341 of this packing colloid 34, and flush with the side of this lead foot 313 and support portion 312.
According to above-mentioned method for making, the present invention also provides a kind of square flat non-leaded package 3 that can avoid electromagnetic interference, comprising: lead frame 31, chip 32, bonding wire 33, packing colloid 34, and shielding film 35.
Described lead frame 31 has support portion 312 and a plurality of lead foot 313 that is located on around this chip carrier 311 and does not connect this chip carrier 311 of chip carrier 311, this chip carrier 311 of a plurality of connection.
This chip 32 connects and places on this chip carrier 311, and electrically connects this chip 32 and respectively the end face 313a of this lead foot 313 and the end face 311a of chip carrier 311 with bonding wire 33.
Described packing colloid 34 coats this chip 32, bonding wire 33 and lead frame 31, and exposes outside these lead foot 313 sides and bottom surface 313b and chip carrier 311 bottom surface 311b.
Described shielding film 35 is located at the end face and the side of this packing colloid 34 and is electrically connected this support portion 312.This shielding film can be carbonaceous material or containing metal powder body material.
In square flat non-leaded package of the present invention, this lead foot 313 and shielding film 35 separate for packing colloid 34, and this encapsulating structure 3 has the side surface that flushes.Know clearly it, respectively this lead foot 313 can have an extension 3130 that extends to these encapsulating structure 3 sides, and the thickness of this extension 3130 is less than this lead foot 313 respectively, thereby the end face 3131 that makes this extension 3130 forms section difference structure with this lead foot 313 end face 313a and is embedded in this packing colloid 34, therefore, this lead foot 313 and shielding film 35 separate for packing colloid 34.
On the other hand, the thickness of this support portion 312 is less than this chip carrier 311, and for example, this support portion 312 bottom surface 312b and this chip carrier 311 bottom surface 311b form section difference structure, thereby make this support portion be embedded in this packing colloid 34.Moreover, because of this encapsulating structure 3 has the side surface that flushes, and these shielding film 35 these support portions 312 of electric connection, therefore, this shielding film 35 can cover this support portion 312 ends; Perhaps, shown in Fig. 3 E, these support portion 312 ends can partly expose outside the side surface of this encapsulating structure 3.
The present invention can avoid the square flat non-leaded package and the method for making thereof of electromagnetic interference, be on the chip carrier of each lead frame of this metal support body, to connect to put chip, and electrically connect this chip and described lead foot and chip carrier with bonding wire, then at this metal support body, form packing colloid on chip and the described bonding wire, described intercell connector along this metal support body carries out cutting the first time then, to cut this packing colloid, but do not cut this metal support body, in this packing colloid, to form a plurality of grooves of cutting apart in length and breadth, and expose the respectively part surface of the support portion of this lead frame, in the exposed surface of this packing colloid and described groove, form shielding film again, make this shielding film electrically connect this support portion, carry out cutting the second time along this groove respectively more afterwards, to cut this shielding film and metal support body, and make this shielding film coat the side of this packing colloid, and be divided into a plurality of encapsulation units.Owing to cut apart this packing colloid earlier, but do not cut apart this metal support body, in packing colloid surface of having cut apart and groove, form shielding film again, cut apart this shielding film and metal support body afterwards more fully, therefore can form shielding film at the exposed surface of packing colloid, avoiding electromagnetic interference, and this method for making helps a large amount of productions.
In addition, form the shielding film of tool capability of electromagnetic shielding by groove, can avoid the fine and closely woven mesh of metal cap to make packing colloid produce turbulent flow easily, produce the popcorn effect cause and have because of bubble, moreover, for face contacts, significantly improve the loose contact problem that prior art utilization bonding wire is done a contact between shielding film and the support portion.
The foregoing description is in order to illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art all can make amendment to the foregoing description under spirit of the present invention and category.Therefore the scope of the present invention should be foundation with the scope of claims.
Claims (20)
1. the square flat non-leaded package that can avoid electromagnetic interference is characterized in that, comprising:
Lead frame has support portion and a plurality of lead foot that is located on around this chip carrier and does not connect this chip carrier of chip carrier, a plurality of these chip carriers of connection;
Chip connects and places on this chip carrier;
Bonding wire electrically connects this chip and reaches respectively this lead foot;
Packing colloid coats this chip, bonding wire and lead frame, and exposes outside this lead foot side and bottom surface and chip carrier bottom surface; And
Shielding film is located at the end face and the side of this packing colloid and is electrically connected this support portion.
2. the square flat non-leaded package that can avoid electromagnetic interference according to claim 1 is characterized in that, this lead foot and shielding film are that packing colloid separates.
3. the square flat non-leaded package that can avoid electromagnetic interference according to claim 1 is characterized in that this encapsulating structure has the side surface that flushes.
4. the square flat non-leaded package that can avoid electromagnetic interference according to claim 1, it is characterized in that, respectively this lead foot has an extension that extends to this encapsulating structure side, the thickness of this extension is less than this lead foot respectively, and the end face of this extension and this lead foot end face form section difference structure and be embedded in this packing colloid.
5. the square flat non-leaded package that can avoid electromagnetic interference according to claim 1 is characterized in that the thickness of this support portion is less than this chip carrier.
6. the square flat non-leaded package that can avoid electromagnetic interference according to claim 1 is characterized in that, this bottom surface, support portion and this chip carrier bottom surface form section difference structure, and this support portion is embedded in this packing colloid.
7. the square flat non-leaded package that can avoid electromagnetic interference according to claim 1 is characterized in that this support portion end exposes outside the side surface of this encapsulating structure.
8. the square flat non-leaded package that can avoid electromagnetic interference according to claim 1 is characterized in that, this shielding film is carbonaceous material or containing metal powder body material.
9. the method for making that can avoid the square flat non-leaded package of electromagnetic interference is characterized in that, comprising:
Prepare a metal support body, comprise a plurality of lead frames and a plurality of intercell connector that distributes in length and breadth, respectively this lead frame has support portion and a plurality of lead foot that is located on around this chip carrier and does not connect this chip carrier of chip carrier, a plurality of these chip carriers of connection, wherein, respectively this lead frame connects this intercell connector by described support portion and lead foot;
On the chip carrier of this lead frame respectively, connect and put chip, and with corresponding respectively this lead foot that electrically connects of bonding wire;
Form packing colloid coating this intercell connector, chip, bonding wire, chip carrier, lead foot and support portion, and expose outside the bottom surface of this intercell connector, chip carrier and lead foot;
Carry out cutting the first time cutting this packing colloid along this intercell connector respectively, in this packing colloid, to form a plurality of respectively grooves of this intercell connector and part support portion that expose;
In this packing colloid surface and groove, form shielding film, electrically connect described support portion to make this shielding film; And
Along this groove respectively and respectively this intercell connector carry out cutting the second time, cutting this shielding film and metal support body, thereby make this shielding film coat this packing colloid side, and flush with the side of this lead foot and support portion.
10. the method for making that can avoid the square flat non-leaded package of electromagnetic interference according to claim 9 is characterized in that the material of this metal support body is a copper.
11. the method for making that can avoid the square flat non-leaded package of electromagnetic interference according to claim 9 is characterized in that the thickness of this support portion is less than this chip carrier.
12. the method for making that can avoid the square flat non-leaded package of electromagnetic interference according to claim 9 is characterized in that, this bottom surface, support portion and this chip carrier bottom surface and intercell connector bottom surface form section difference structure.
13. the method for making that can avoid the square flat non-leaded package of electromagnetic interference according to claim 12 is characterized in that, this section difference structure is to form through etching.
14. the method for making that can avoid the square flat non-leaded package of electromagnetic interference according to claim 9, it is characterized in that, respectively this lead foot has an extension, and the thickness of this extension is less than this lead foot respectively, thereby makes the end face of this extension and this lead foot end face form a section difference structure.
15. the method for making that can avoid the square flat non-leaded package of electromagnetic interference according to claim 14 is characterized in that, this section difference structure is to form through etching.
16. the method for making that can avoid the square flat non-leaded package of electromagnetic interference according to claim 9 is characterized in that the width of this groove is greater than this intercell connector.
17. the method for making that can avoid the square flat non-leaded package of electromagnetic interference according to claim 9 is characterized in that this width that cuts for the second time is less than this width that cuts for the first time.
18. the method for making that can avoid the square flat non-leaded package of electromagnetic interference according to claim 9 is characterized in that, the material that forms this shielding film is carbonaceous material or containing metal powder body material.
19. the method for making that can avoid the square flat non-leaded package of electromagnetic interference according to claim 9 is characterized in that, this shielding film is to be formed in the exposed surface and described groove of this packing colloid with screen painting, and solidifies this shielding film.
20. the method for making that can avoid the square flat non-leaded package of electromagnetic interference according to claim 18 is characterized in that the method that forms this shielding film comprises:
In described groove, splash into liquid carbonaceous material or containing metal powder body material, to form first shielding film;
On the exposed surface of this packing colloid and first shielding film in the described groove, form second shielding film; And
Solidify this first shielding film and second shielding film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101365921A CN102194797A (en) | 2010-03-11 | 2010-03-11 | Square flat leadless packaging structure capable of avoiding electromagnetic interference and manufacturing method thereof |
Applications Claiming Priority (1)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111653552A (en) * | 2020-06-16 | 2020-09-11 | 西安科技大学 | Square flat chip packaging structure with high electromagnetic pulse interference resistance |
| WO2020253147A1 (en) * | 2019-06-17 | 2020-12-24 | 潍坊歌尔微电子有限公司 | Shielding process for sip packaging |
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| CN1374697A (en) * | 2001-03-01 | 2002-10-16 | 松下电器产业株式会社 | Resin sealing semi-conductor device and its producing method |
| CN101083231A (en) * | 2006-06-01 | 2007-12-05 | 美国博通公司 | Leadframe ic packages having top and bottom integrated heat spreaders |
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| US5679975A (en) * | 1995-12-18 | 1997-10-21 | Integrated Device Technology, Inc. | Conductive encapsulating shield for an integrated circuit |
| US20010007780A1 (en) * | 1999-02-24 | 2001-07-12 | Masanori Minamio | Resin-molded semicondutor device, method for manufacturing the same, and leadframe |
| CN1374697A (en) * | 2001-03-01 | 2002-10-16 | 松下电器产业株式会社 | Resin sealing semi-conductor device and its producing method |
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| WO2020253147A1 (en) * | 2019-06-17 | 2020-12-24 | 潍坊歌尔微电子有限公司 | Shielding process for sip packaging |
| CN111653552A (en) * | 2020-06-16 | 2020-09-11 | 西安科技大学 | Square flat chip packaging structure with high electromagnetic pulse interference resistance |
| CN111653552B (en) * | 2020-06-16 | 2022-06-10 | 西安科技大学 | Square flat chip packaging structure with high electromagnetic pulse interference resistance |
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Application publication date: 20110921 |