CN103066047B - Semiconductor-sealing-purpose conductive wire frame strip and method for packing - Google Patents
Semiconductor-sealing-purpose conductive wire frame strip and method for packing Download PDFInfo
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- CN103066047B CN103066047B CN201210585689.XA CN201210585689A CN103066047B CN 103066047 B CN103066047 B CN 103066047B CN 201210585689 A CN201210585689 A CN 201210585689A CN 103066047 B CN103066047 B CN 103066047B
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- pin
- lead frame
- frame unit
- conductive wire
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000012856 packing Methods 0.000 title claims abstract description 8
- 239000000084 colloidal system Substances 0.000 claims description 6
- 238000005253 cladding Methods 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 abstract description 21
- 238000004806 packaging method and process Methods 0.000 description 21
- 239000004065 semiconductor Substances 0.000 description 13
- 238000005538 encapsulation Methods 0.000 description 8
- 238000010276 construction Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The open a kind of semiconductor-sealing-purpose conductive wire frame strip of the present invention and method for packing, described conductive wire frame strip comprises a housing, several connection supports, several lead frame unit and at least one through-hole section, each lead frame unit comprises a chip carrier, at least one support bar and several spaced pin, described support bar connects described chip carrier to described connection support, described pin is connected to described connection support, and described through-hole section is formed on the connection support between the lead frame unit that described connection at least two is adjacent.By the design of described through-hole section, cutter cutting can be reduced and connect burr phenomena produced by support, and then effectively promote chip package quality and the process rate of final finished.
Description
Technical field
The invention relates to the manufacture method of a kind of conductive wire frame strip and encapsulation, in particular to one half
Conductor encapsulation conductive wire frame strip and method for packing.
Background technology
Now, semiconductor packaging essentially consists in and prevents chip from being affected by ambient temperature, dampness,
And the pollution of miscellaneous dirt, and provide the electric connection between chip and external circuit, therefore, in order to meet
Various package requirements, gradually develop the packaging structure of various different types, such as by semiconductor silicon wafer
(wafer) silicon (chip) of cutting, utilizes routing (wire bonding) or projection (bumping) etc.
Appropriate ways, and select to be fixed on lead frame (leadframe) or substrate (substrate), then recycle
Colloid encapsulation cladding protection silicon, so can complete the basic framework of semiconductor packaging structure.Mesh
Before, in order to emphasize compact trend in response to consumption electronic products, use a kind of square surface without outward
The encapsulation kenel of leaded semiconductor packaging structure (QFN, Quad Flat No lead), described square surface without
Exterior pin semiconductor packaging construction (QFN, Quad Flat No lead) does not have outer pin, it is common that one
On conductive wire frame strip (leadframe strip), several lead frame unit is set, the most several chips is fixed
On the chip carrier of lead frame unit, the routing combination processor such as (wire bonding) and sealing, finally
Unnecessary framework is removed in cutting again, in order to manufactured several packaging structure with lead frame, wherein simultaneously
By the way of routing combines (wire bonding), chip is electrically connected on the pin of conductive wire frame strip, energy
Enough there is shorter signal bang path, thus there is signal transmission speed faster.
But, described square surface non-exterior pin semiconductor packaging construction (QFN, Quad Flat No lead)
During encapsulation, separate each lead frame unit and must carry out transverse direction and longitudinal direction on conductive wire frame strip
Cutting action, is all to use high-density pin spacing due to present quasiconductor, and described conductive wire frame strip is copper
Alloy, in described cutting action, utilizes cutter cutting can produce burr (bur) on conductive wire frame strip, makes
Two adjacent leads on conductive wire frame strip cause the situation of product short-circuit failure because of burr contact, thus sternly
Ghost image rings package quality and the process rate of final finished of chip.
Therefore, it is necessary to provide a kind of semiconductor-sealing-purpose conductive wire frame strip, to solve existing for prior art
Problem.
Summary of the invention
In view of this, the present invention provides a kind of semiconductor-sealing-purpose conductive wire frame strip, to solve after packaging
In cutting process, the problem that cutting action produces burr on conductive wire frame strip and causes product short-circuit failure.
Present invention is primarily targeted at a kind of semiconductor-sealing-purpose conductive wire frame strip of offer, it can pass through
Connect support and form through-hole section, to reduce burr phenomena produced by cutter cutting connection support, relatively keep away
Exempt from two adjacent pins and cause the risk of product short-circuit failure because of burr contact.
The secondary objective of the present invention is to provide a kind of semiconductor-sealing-purpose conductive wire frame strip, and it can pass through
Connect support and form through-hole section, to reduce burr phenomena produced by cutter cutting connection support, can be effective
Promote chip package quality and the process rate of final finished.
For reaching the object defined above of the present invention, one embodiment of the invention provides a kind of semiconductor-sealing-purpose wire
Frame bar, wherein said semiconductor-sealing-purpose conductive wire frame strip comprises a housing, several connect supports, several lead
Coil holder unit and at least one through-hole section, described connection support is staggered in the range of described housing, institute
Stating in the space that lead frame unit is arranged in the definition of described connection support, each lead frame unit comprises a core
Bar, at least one support bar and several spaced pin, described support bar connects described chip carrier extremely
Described connection support, described pin is connected to described connection support, and described through-hole section is formed at described connection
On connection support between the lead frame unit that at least two is adjacent.
Furthermore, a kind of semiconductor-sealing-purpose conductive wire frame strip of another embodiment of the present invention offer, wherein said half
Conductor encapsulation conductive wire frame strip comprise a housing, several connect support, several lead frame unit and at least
Through-hole section, described connection support is staggered in the range of described housing, and described lead frame unit arranges
In the space of described connection support definition, each lead frame unit comprises several spaced pin,
Described pin is connected to described connection support, and described through-hole section is formed at the wire that described at least two is adjacent
On connection support between frame unit.
It addition, further embodiment of this invention provides a kind of method for packing, wherein said manufacture method comprises step
Rapid: to purchase a conductive wire frame strip, described conductive wire frame strip comprise a housing, several connect support, be staggered
In the range of described housing；And several lead frame unit, it is arranged in the space of described connection support definition
In, each lead frame unit comprises: several pins are connected to described connection support；At least one through-hole section,
It is formed on the connection support between the described lead frame unit that at least two is adjacent；By several chips respectively
It is fixed in described lead frame unit；It is electrically connected with described pin and chip with several conducting elements；By institute
State conductive wire frame strip to be positioned in a mould, and fill the colloid described chip of cladding；By each connection support
Break and cut, make two adjacent lead frame unit separately.
According to above-mentioned semiconductor-sealing-purpose conductive wire frame strip and method for packing, in cutting process after packaging,
The present invention, by forming through-hole section at described connection support, can reduce cutter cutting and connect produced by support
Burr phenomena, avoids two adjacent pins to cause the risk of product short-circuit failure because of burr contact relatively,
Can effectively promote the process rate of chip package quality and final finished.
Accompanying drawing explanation
Fig. 1 is the top view of one embodiment of the invention semiconductor-sealing-purpose conductive wire frame strip.
Fig. 2 is the sectional view of Fig. 1 embodiment semiconductor-sealing-purpose conductive wire frame strip II-II of the present invention.
Figure 1A to 1D is other shape of through-hole section of Fig. 1 embodiment semiconductor-sealing-purpose conductive wire frame strip of the present invention
The top view of state.
Fig. 3 is the top view of another embodiment of the present invention semiconductor-sealing-purpose conductive wire frame strip.
Fig. 3 A is the top view of Fig. 3 embodiment semiconductor-sealing-purpose conductive wire frame strip another kind form of the present invention.
Fig. 4 is the sectional view of Fig. 3 A embodiment semiconductor-sealing-purpose conductive wire frame strip IV-IV.
Fig. 5 is the top view of further embodiment of this invention semiconductor-sealing-purpose conductive wire frame strip.
Fig. 6 is the sectional view of Fig. 5 embodiment semiconductor-sealing-purpose conductive wire frame strip VI-VI.
Detailed description of the invention
The explanation of following embodiment is graphic with reference to add, may be used to enforcement in order to illustrate the present invention
Specific embodiment.Furthermore, the direction term that the present invention is previously mentioned, the most upper and lower, top, the end, front,
Afterwards, left and right, inside and outside, side, surrounding, central authorities, level, laterally, vertically, longitudinally, axially,
Radially, the superiors or orlop etc., be only the direction with reference to annexed drawings.Therefore, the direction of use is used
Language is to illustrate and understand the present invention, and is not used to limit the present invention.
Refer to Fig. 1, shown in 2, one embodiment of the invention provides a kind of semiconductor-sealing-purpose conductive wire frame strip
100 can apply at square surface non-exterior pin semiconductor packaging construction (QFN, Quad Flat No lead),
And utilizing a metallic plate to be made, described metallic plate is selected from the metal of various tool satisfactory electrical conductivity, example
Such as copper, ferrum, aluminum, nickel, zinc or its alloy etc..Described semiconductor-sealing-purpose conductive wire frame strip 100 comprises one
Housing 1, several connect supports 2, several lead frame unit 3 and several through-hole section 21, the present invention will be in
Describe the detail structure of each element of described embodiment, assembled relation and operation principles thereof the most one by one in detail.
Described connection support 2 is staggered in the range of described housing 1, described lead frame unit 3 row
Be listed in described connection support 2 definition space 20 in, each lead frame unit 3 comprise a chip carrier 31,
Several support bars 32 and several spaced pin 33, as it is shown in figure 1, each lead frame unit 3
Support bar 32 be four, connect two connection supports 2 of described chip carrier 31 both sides respectively, make institute
State support bar 32 from described chip carrier 31 to described connection support 2, but described support bar 32 also can only set
Put one, in order to support on described chip carrier 31, prop up it addition, described pin 33 is connected to described connection
Frame 2, the pin 33 of the most each connection support 2 both sides each extension one lead frame unit 3 respectively is described logical
Hole portion 21 is formed on the connection support 2 between the lead frame unit 3 that described connection two is adjacent, at this
In enforcement, described through-hole section 21 is single long slot bore, and described long slot bore refers to a perforation, described perforation edge
The size on the length direction connecting support 2 at its place, more than the company at described its place of perforated vertical
Connect the size on the length direction of support 2.Described long slot bore can have any shape, such as rectangle, two
Strip that end is curved edge, oval or irregularly shaped etc., described long slot bore is positioned at two lead frames
Between the pin 33 of unit 3.
Additionally, in other embodiments of the invention, as shown in Figure 1A, described through-hole section 21 can also
It is two (or two or more) spaced long slot bores；Or, as shown in Figure 1B, described through-hole section
21 ' connect on the position of described pin 33 at least formed at described connection support 2, and are several interval rows
The short slotted eye of row, described short slotted eye refers to a perforation, and described perforation connects support 2 along its place
Size on length direction, less than or equal to the length side connecting support 2 at described its place of perforated vertical
Size upwards.Described short slotted eye can have any shape, such as circular, square, rectangle or its
His shape；And, as shown in Figure 1 C, described through-hole section 21 is a long slot bore, described through-hole section 21
It it is a concavo-convex spaced long slot bore in border；Furthermore, as shown in figure ip, described through-hole section 21,21 '
It is respectively staggered spaced two long slot bores and a short slotted eye.Described long slot bore refers to a perforation, described
Perforation is along the size on the length direction connecting support 2 at its place, more than its institute of described perforated vertical
Connect support 2 length direction on size.The shape of described long slot bore can have any shape,
Such as rectangle, two ends are the strip of curved edge, oval or irregularly shaped etc..Described short slotted eye
Referring to a perforation, described perforation, along the size on the length direction connecting support 2 at its place, is less than
Or equal to the size on the length direction connecting support 2 at described its place of perforated vertical.Described short slotted eye
Can have any shape, such as circular, square, rectangle or other shapes.
As it has been described above, in cutting process after packaging, separating each lead frame unit 3 must be first at gold
Belong to or carry out cutting action on the connection support 2 of alloy, and the present invention is by described through-hole section 21,21 '
For long slot bore or the design of short slotted eye, the area that cutter cuts on described connection support 2 can be reduced, because of
And reduce cutter cutting and connect burr phenomena produced by support 2, relatively avoid two adjacent pins 33
Cause the risk of product short-circuit failure because of burr contact, can effectively promote chip package quality and finally become
The process rate of product, it addition, described long slot bore (cuts out bigger of continuous print connecting on stent length direction
Long-pending) it is used in the situation of the wider width of described connection support 2, the formation of described long slot bore does not interferes with described
The bulk strength of semiconductor-sealing-purpose conductive wire frame strip 100, described short slotted eye (is connecting on stent length direction
Cut out the area at interval) it is used in the situation of the narrower width of described connection support 2, the formation of described short slotted eye
The effect as far as possible avoiding affecting the bulk strength of described semiconductor-sealing-purpose conductive wire frame strip 100 can be played.
And, according to the specific design of described semiconductor-sealing-purpose conductive wire frame strip 100, can be by described long slot bore
Reasonably distribute with described short slotted eye, during to reach to reduce cutting to greatest extent burr phenomena and
Do not affect the bulk strength of described semiconductor-sealing-purpose conductive wire frame strip 100.Furthermore, same described quasiconductor
The through-hole section connected on support between upper each lead frame unit of encapsulation conductive wire frame strip 100 can be
Identical design arrangement, it is also possible to be different design arrangements.
Refer to shown in Fig. 3 and 3A, the semiconductor-sealing-purpose conductive wire frame strip 100 of another embodiment of the present invention
Similar in appearance to Fig. 1 embodiment of the present invention, and approximately along by similar elements title and figure number, but the present embodiment
Difference characteristic is: described lead frame unit 3 comprises several pin, and described pin comprises the first pin 33
And several second pin 33 ', described first pin 33 is different from the length of the second pin 33 ', and each other
It is staggered and is connected to connect accordingly on support 2.
As it has been described above, during the chip of encapsulation is fixed and is electrically connected with, described lead frame unit 3
Chip carrier 31 is provided for one or several chip 4 is fixed, and combines (wire followed by routing
Bonding) bonding wire (not illustrating) juncture；Or as shown in Fig. 3 A, Fig. 4, utilize flip-chip 4 (flip
Chip) projection 41 (bump, Fig. 3 A is illustrated in figure with dotted line ball) combination, by described chip
4 are electrically connected with, by described first pin 33 and second with described first pin 33 and the second pin 33 '
The design that the length of pin 33 ' is different, can improve the junction point space of electric connection, and then can increase electricity
Property the closeness of junction point that connects, thus described first pin 33 and the second pin can be improved further
The quantity of 33 '.
The described semiconductor-sealing-purpose conductive wire frame strip 100 of above example can be applied at square surface without outward
Leaded semiconductor packaging structure (QFN, Quad Flat No lead), has through-hole section design it addition, this
Semiconductor-sealing-purpose conductive wire frame strip be equally useful in any non-exterior pin semiconductor packaging construction, no
It is limited to square surface non-exterior pin semiconductor packaging construction, it is also possible to be applicable to both sides and have the half of pin
Conductor packaging structure, the least profile non-exterior pin semiconductor packaging construction (SON, Small Outline No
Lead), or, three limits there is the non-exterior pin semiconductor packaging construction of pin.As long as without outer pin
Semiconductor packaging structure need cut processing procedure, this kind have through-hole section design semiconductor-sealing-purpose wire
Frame bar plays the burr phenomena produced when preventing or reduce cutting the most equally.
Refer to shown in Fig. 5, the semiconductor-sealing-purpose conductive wire frame strip 100 of further embodiment of this invention is similar
In Fig. 1 embodiment of the present invention, and approximately along by similar elements title and figure number, but the difference of the present embodiment
Be characterised by: described semiconductor-sealing-purpose conductive wire frame strip 100 only comprise a housing 1, several connect support 2
And several lead frame unit 3, described connection support 2 is staggered in the range of described housing 1, institute
State in the space 20 that lead frame unit 3 is arranged in the definition of described connection support 2, each lead frame unit 3
Comprising several spaced pin, described pin comprises the first pin 33 and the second pin 33 ', but not
Having chip carrier, described first pin 33 and the second pin 33 ' are connected to described connection support 2, described
The length of the first pin 33 and the second pin 33 ' is different, and arrangement interlaced with each other, described connection support 2
Having a through-hole section 21, described through-hole section 21 is a long slot bore, and described through-hole section 21 is that a border is concavo-convex
Spaced long slot bore.
As it has been described above, in cutting process after packaging, the present embodiment is by concavo-convex interval, described border row
The design of the long slot bore of row, can reduce cutter cutting and connect burr phenomena produced by support 2, Jin Eryou
Effect promotes package quality and the process rate of final finished of described chip 4.
Please coordinate with reference to Fig. 1, its display is according to the semiconductor-sealing-purpose lead frame of one embodiment of the invention
Bar 100.The manufacture method of the semiconductor-sealing-purpose conductive wire frame strip 100 of the present embodiment can comprise the steps:
Purchase a conductive wire frame strip 100, wherein said conductive wire frame strip comprise a housing 1, several connect support 2
And several lead frame unit 3, described connection support 2 is staggered in the range of described housing 1, institute
State in the space 20 that lead frame unit 3 is arranged in the definition of described connection support 2, each lead frame unit 3
Comprising a chip carrier 31, several spaced pin, described pin comprises the first pin 33, and described
One pin 33 is connected to described connection support 2, and wherein said connection support 2 has a through-hole section 21, shape
Become on the position that described connection support 2 connects described first pin 33.
Several chips (not illustrating) are separately fixed on the chip carrier 31 of described lead frame unit 3, then
Utilize routing combine the mode of (wire bonding) with several conducting elements (such as bonding wire) be electrically connected with as described in the
One pin 33 and chip.
Described conductive wire frame strip 100 is positioned in a mould (not illustrating), and fills colloid (not illustrating)
It is coated with described chip, and makes described colloid solidify, followed by a cutter (not illustrating), each connection is propped up
Frame 2 is cut along described through-hole section 21 is the most disconnected, makes two adjacent lead frame unit 3 separately, i.e. can complete
The packaging operation of quasiconductor.
If it addition, use Fig. 5, the conductive wire frame strip 100 of 6, then be a chip 4 is directly anchored to described
On first pin 33 and the second pin 33 ', and it is electrically connected with several conducting elements (such as wire or projection)
Described first, second pin 33,33 ' and described chip 4, more described conductive wire frame strip 100 is positioned over one
In mould (not illustrating), and fill the colloid described chip 4 of cladding and conducting element, finally by each company
Connect support 2 to cut along described through-hole section 21 is the most disconnected, make two adjacent lead frame unit 3 separately.
As it has been described above, in cutting process after packaging, the present invention is by being formed at described connection support 2
Through-hole section 21, can reduce cutter cutting and connect burr phenomena produced by support 2, relatively avoid two phases
The first adjacent pin 33 causes the risk of product short-circuit failure because of burr contact, can effectively promote chip envelope
Packing quality and the process rate of final finished.
The present invention is been described by by above-mentioned related embodiment, but above-described embodiment only implements the present invention
Example.It must be noted that, it has been disclosed that embodiment be not limiting as the scope of the present invention.On the contrary,
The amendment and the equalization that are contained in the spirit and scope of claims arrange and are all included in the scope of the present invention
In.
Claims (5)
1. a semiconductor-sealing-purpose conductive wire frame strip, it is characterised in that: described semiconductor-sealing-purpose conductive wire frame strip bag
Contain:
One housing；
Several connect support, are staggered in the range of described housing；And
Several lead frame unit, are arranged in the space of described connection support definition, each lead frame unit bag
Contain: a chip carrier；At least one support bar, connects described chip carrier to described connection support；And it is several
Spaced pin, described pin comprises several first pin and several second pin, and described first
Pin is different from the length of described second pin, and arrangement interlaced with each other and be connected to described connection support
On；
At least one through-hole section, the connection being formed between the lead frame unit that described connection at least two is adjacent is propped up
On frame；
Wherein, several through-hole section are formed at the connection support between the described lead frame unit that any two is adjacent
On；
Described through-hole section is at least one long slot bore and the combination of at least one short slotted eye.
2. semiconductor-sealing-purpose conductive wire frame strip as claimed in claim 1, it is characterised in that described short slotted eye has
Several, and be arranged on and connect on support between the corresponding pin of adjacent two lead frame unit.
3. semiconductor-sealing-purpose conductive wire frame strip as claimed in claim 1, it is characterised in that described long slot bore and
Described short slotted eye is staggered.
4. a semiconductor-sealing-purpose conductive wire frame strip, it is characterised in that: described semiconductor-sealing-purpose conductive wire frame strip bag
Contain:
One housing；
Several connect support, are staggered in the range of described housing；And
Several lead frame unit, are arranged in the space of described connection support definition, each lead frame unit bag
Containing: several spaced pins, described pin comprises several first pin and several second pin,
Described first pin is different from the length of described second pin, and arrangement interlaced with each other and be connected to described
Connect on support；
At least one through-hole section, the connection support being formed between the lead frame unit that described at least two is adjacent
On；
Wherein, several through-hole section are formed at the connection support between the described lead frame unit that any two is adjacent
On；
Described through-hole section is at least one long slot bore and the combination of at least one short slotted eye.
5. a method for packing, it is characterised in that: described method comprises step
Purchase a conductive wire frame strip, described conductive wire frame strip comprise a housing, several connect support, be staggered
In the range of described housing；And several lead frame unit, it is arranged in the space of described connection support definition
In, each lead frame unit comprises: several pins are connected to described connection support；At least one through-hole section,
It is formed on the connection support between the described lead frame unit that at least two is adjacent；
Several chips are separately fixed in described lead frame unit；
It is electrically connected with described pin and chip with several conducting elements；
Described conductive wire frame strip is positioned in a mould, and fills the colloid described chip of cladding；And
Cut disconnected for each connection support, make two adjacent lead frame unit separately；
Wherein, several through-hole section are formed at the connection support between the described lead frame unit that any two is adjacent
On；
Described through-hole section is at least one long slot bore and the combination of at least one short slotted eye.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210585689.XA CN103066047B (en) | 2012-12-28 | 2012-12-28 | Semiconductor-sealing-purpose conductive wire frame strip and method for packing |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210585689.XA CN103066047B (en) | 2012-12-28 | 2012-12-28 | Semiconductor-sealing-purpose conductive wire frame strip and method for packing |
Publications (2)
| Publication Number | Publication Date |
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| CN103066047A CN103066047A (en) | 2013-04-24 |
| CN103066047B true CN103066047B (en) | 2016-09-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210585689.XA Expired - Fee Related CN103066047B (en) | 2012-12-28 | 2012-12-28 | Semiconductor-sealing-purpose conductive wire frame strip and method for packing |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111584456A (en) * | 2020-05-08 | 2020-08-25 | 武汉华星光电半导体显示技术有限公司 | Chip on film |
| US11373943B2 (en) | 2020-05-08 | 2022-06-28 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Flip-chip film |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW411598B (en) * | 1997-08-19 | 2000-11-11 | Mitsubishi Electric Corp | Lead frame, semiconductor device using the lead frame and method for manufacturing the semiconductor device |
| CN101894822A (en) * | 2010-05-28 | 2010-11-24 | 日月光封装测试(上海)有限公司 | Lead frame band construction for semiconductor packaging |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114756A (en) * | 1998-04-01 | 2000-09-05 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit leadframes |
| US6608366B1 (en) * | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
| JP2006179760A (en) * | 2004-12-24 | 2006-07-06 | Yamaha Corp | Semiconductor package and lead frame used therefor |
| TW200937597A (en) * | 2008-02-20 | 2009-09-01 | Chipmos Technologies Inc | Quad flat non-leaded package structure |
| JP5762078B2 (en) * | 2011-03-28 | 2015-08-12 | 新光電気工業株式会社 | Lead frame |
| CN202308051U (en) * | 2011-11-03 | 2012-07-04 | 广东德豪润达电气股份有限公司 | LED packaging support and LED device |
| CN203134784U (en) * | 2012-12-28 | 2013-08-14 | 日月光封装测试(上海)有限公司 | Lead frame strip for semiconductor packaging |
-
2012
- 2012-12-28 CN CN201210585689.XA patent/CN103066047B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW411598B (en) * | 1997-08-19 | 2000-11-11 | Mitsubishi Electric Corp | Lead frame, semiconductor device using the lead frame and method for manufacturing the semiconductor device |
| CN101894822A (en) * | 2010-05-28 | 2010-11-24 | 日月光封装测试(上海)有限公司 | Lead frame band construction for semiconductor packaging |
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| Publication number | Publication date |
|---|---|
| CN103066047A (en) | 2013-04-24 |
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