CN113380632A - Semiconductor packaging device and preparation method thereof - Google Patents

Semiconductor packaging device and preparation method thereof Download PDF

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Publication number
CN113380632A
CN113380632A CN202110495583.XA CN202110495583A CN113380632A CN 113380632 A CN113380632 A CN 113380632A CN 202110495583 A CN202110495583 A CN 202110495583A CN 113380632 A CN113380632 A CN 113380632A
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CN
China
Prior art keywords
metal block
groove
metal
block
packaging
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Pending
Application number
CN202110495583.XA
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Chinese (zh)
Inventor
张志龙
吴品忠
成秀清
陈肖瑾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nantong Fujitsu Microelectronics Co Ltd
Tongfu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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Priority to CN202110495583.XA priority Critical patent/CN113380632A/en
Publication of CN113380632A publication Critical patent/CN113380632A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H01L21/4896—Mechanical treatment, e.g. cutting, bending
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The application discloses a semiconductor packaging device and a preparation method thereof, comprising the following steps: providing a packaging body, wherein the packaging body comprises a plastic packaging layer and a plurality of packaging units arranged on the same layer, the plastic packaging layer covers the front sides of the packaging units, and the back sides of the packaging units are exposed out of the plastic packaging layer; a shared pin is arranged between the adjacent packaging units and comprises a first metal block and a second metal block which are arranged in a stacked mode, the surface of one side of the first metal block is flush with the back surface, and the average width of the first metal block is larger than that of the second metal block; the second metal block is a rectangular block; cutting the common pin from the back side to form a first groove on the common pin, wherein the first groove continuously penetrates through the first metal block and the adjacent part of the second metal block; forming a solderable layer on the surface of the common lead exposed from the back side; the package body is cut from the front side and the position corresponding to the first groove to split the adjacent package units, so that a single semiconductor package device is obtained, and the contact area with the solder can be increased.

Description

Semiconductor packaging device and preparation method thereof
Technical Field
The application belongs to the technical field of semiconductor packaging devices, and particularly relates to a semiconductor packaging device and a preparation method thereof.
Background
Typically, quad flat no lead (QFN)/dual flat no lead (DFN) packages are not side wettable, and wettable conductive layers provide wettable sides for solder to wick upward when the packaged device is mounted to a substrate using SMT. Specifically, the solder used to join the wiring board PCB and the packaged device wicks up the sides of the wettable conductive layer along the side surfaces of the packaged device. In order to increase the wettability of the pins on the side surface of the package, tin or tin alloy is plated on the side surface of the package after cutting, and in the prior art, two times of mechanical cutting and one time of laser cutting are adopted to form a step.
The inventor in the application finds that the above method easily causes no solderable layer on the side surface of the lead in the long-term research process, and although the solderable layer can be plated on a single product by adopting a electroless plating method, the process is complex and the efficiency is not high.
Disclosure of Invention
The technical problem that the application mainly solves is to provide a semiconductor packaging device and a preparation method thereof, and a weldable layer can be fully formed on the side face of a pin.
In order to solve the technical problem, the application adopts a technical scheme that: the preparation method of the semiconductor packaging device comprises the steps of providing a packaging body, wherein the packaging body comprises a plastic packaging layer and a plurality of packaging units arranged on the same layer, the plastic packaging layer covers the front surfaces of the packaging units, and the back surfaces of the packaging units are exposed out of the plastic packaging layer; a common pin is arranged between the adjacent packaging units, the common pin comprises a first metal block and a second metal block which are arranged in a stacked mode, one side surface of the first metal block is flush with the back surface, and the average width of the first metal block is larger than that of the second metal block; the second metal block is a rectangular block; cutting the common pin from the back side to form a first groove on the common pin; the first groove continuously penetrates through the first metal block and the adjacent part of the second metal block; forming a solderable layer on the surface of the common lead exposed from the back side; and cutting the packaging body from one side of the front surface and the position corresponding to the first groove to split the adjacent packaging units so as to obtain a single semiconductor packaging device.
Wherein the step of cutting the package body from the front side and the position corresponding to the first groove to split the adjacent package units comprises: cutting the packaging body from the position of the front side corresponding to the first groove to form a second groove on the second metal block; the first groove is communicated with the second groove, and the width of the first groove is the same as that of the second groove.
Wherein the step of cutting the package body from the front side and the position corresponding to the first groove to split the adjacent package units comprises: cutting the packaging body from the position of the front side corresponding to the first groove to form a second groove on the second metal block; the first groove is communicated with the second groove, and the width of the first groove is larger than that of the second groove.
Wherein the step of cutting the package body from the front side and the position corresponding to the first groove to split the adjacent package units comprises: cutting the packaging body from the position of the front side corresponding to the first groove to continuously remove the second metal block and the adjacent part of the first metal block; and a second groove is formed on one side of the first metal block, which is far away from the back surface, the first groove is communicated with the second groove, and the width of the first groove is smaller than that of the second groove.
The second metal block comprises a plurality of metal sub-blocks which are arranged in a stacked mode, and the width of the metal sub-block close to the first metal block is larger than the width of the other metal sub-blocks.
Wherein, when the second metal block includes a plurality of metal sub-blocks arranged in a stacked manner, the common lead is cut from the back side so that the first groove formed on the common lead continuously penetrates through the first metal block and a portion of the metal sub-block closest thereto.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a semiconductor package device including: a package unit including a plurality of pins located at a side of the package unit; the pins comprise a first metal block and a second metal block which are arranged in a stacked mode, the bottom surface of the first metal block is flush with the back surface of the packaging unit, and the average width of the first metal block is larger than that of the second metal block; the second metal block is a rectangular block; the plastic packaging layer covers the front surface of the packaging unit, and the surface of the pin, which is close to the back surface and the side surface, is exposed from the plastic packaging layer; the weldable layer covers the surface of the first metal block exposed from the plastic package layer and the surface of part of the second metal block exposed from the plastic package layer.
Wherein the first metal block, the second metal block and the side surfaces of the plastic package layer are flush; the solderable layer covers a bottom surface of the first metal block, side surfaces of the first metal block, and portions of side surfaces of the second metal block adjacent to the first metal block.
The second metal block is flush with the side face of the plastic package layer, the side face of the first metal block is retracted relative to the side face of the second metal block, and the bottom face, facing the first metal block, of the second metal block is provided with a first area exposed out of the first metal block; the solderable layer covers a bottom surface of the first metal block, side surfaces of the first metal block, and a surface of the first region.
The second metal block comprises a plurality of metal sub-blocks which are arranged in a stacked mode, and the width of the metal sub-block close to the first metal block is larger than the width of the other metal sub-blocks.
The beneficial effect of this application is: adopt the first time cutting to cut the first recess of formation from back one side to sharing pin in this application, but fully form the layer of welding in the side of pin, the second time cutting is from openly one side and cutting the packaging body from the position of corresponding first recess and form the second recess, can prevent to destroy the layer of welding that forms after the second time cutting and cause short circuit between the pin like this, can reduce production cost, and can make the side of pin form the layer of welding completely, the wettability of encapsulation side pin has been increased, thereby increase the area of contact with the solder.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a schematic flow chart diagram of one embodiment of a semiconductor package device of the present application;
FIG. 2 is a schematic structural diagram of an embodiment corresponding to steps S1-S4 in FIG. 1;
FIG. 3 is a schematic structural diagram of another embodiment of step S4 in FIG. 1;
FIG. 4 is a schematic structural diagram of another embodiment of step S4 in FIG. 1;
fig. 5 is a schematic structural diagram of another embodiment of the corresponding package in step S1 in fig. 1;
FIG. 6 is a schematic structural diagram of another embodiment of step S2 in FIG. 1;
FIG. 7 is a schematic diagram of the structure of one embodiment of the semiconductor package device of the present application;
FIG. 8 is a schematic structural diagram of another embodiment of a semiconductor package device of the present application;
fig. 9 is a schematic structural diagram of another embodiment of a semiconductor package device according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1-2, fig. 1 is a schematic flow chart illustrating an embodiment of a method for manufacturing a semiconductor package device according to the present application, and fig. 2 is a schematic structural diagram illustrating an embodiment corresponding to steps S1-S4 in fig. 1. The preparation method comprises the following steps:
s1: a package 1 is provided.
Specifically, referring to fig. 2a, the package 1 may be prepared by any method in the prior art, which is not described herein again. In the present embodiment, the package 1 includes a molding layer 10 and a plurality of package units 12 disposed on the same layer. The molding layer 10 covers the front surfaces 120 of the plurality of package units 12, and the back surfaces 122 of the plurality of package units 12 are exposed from the molding layer 10. The material of the molding compound layer 10 may be one or more of polyimide, silicone, epoxy resin, etc., which is not limited in this application.
Specifically, the package unit 12 includes a metal layer 124 and a chip 126, wherein the chip 126 is stacked on the metal layer 124, and the metal layer 124 may be copper, and the like, which is not limited herein. In addition, in the present embodiment, a common lead 14 is provided between adjacent package units 12 for electrical connection with other components. The common lead 14 includes a first metal block 140 and a second metal block 142 stacked one on another. Specifically, one side surface 1400 of the first metal block 140 is flush with the back surface 122, and the average width of the first metal block 140 is greater than the average width of the second metal block 142. As shown in fig. 2a, the chip 126 and the common lead 14 are electrically connected by a bonding wire 128, specifically, the chip 126 and the first metal block 140 are electrically connected by a bonding wire 128, and the material of the bonding wire 128 may be gold, copper, aluminum, etc., which is not limited herein.
In addition, in the embodiment, the material of the first metal block 140 may be the same as or different from that of the second metal block 142. The material of the first metal block 140 and the second metal block 142 may be copper, or may be formed of copper and plated with other metals, such as palladium PPF, silver Ag, and the like, which is not limited herein.
S2: common lead 14 is cut from the back surface 122 side to form first grooves 16 on common lead 14.
Specifically, as shown in fig. 2b, the first groove 16 continuously penetrates the first metal block 140 and the adjacent part of the second metal block 142. Specifically, in the present embodiment, the cutting tool having a predetermined width may cut upward from one side surface 1400 of the first metal block 140, and the cutting depth is slightly greater than the height of the first metal block 140 and less than the sum of the heights of the first metal block 140 and the second metal block 142 to form the first groove 16, but the first groove 16 may also be formed in other manners, which is not limited herein.
S3: a solderable layer 18 is formed on the surface (not shown) of the common lead 14 exposed from the back surface 122 side.
Specifically, as shown in fig. 2c, the solderable layer 18 covers the surfaces (not shown) of the first metal block 140 and the second metal block 142 exposed from the back surface 122 side. In addition, in the present embodiment, the solderable layer 18 may be formed by electroplating, electrodeposition, or the like, and the present application is not limited thereto. Specifically, the material of solderable layer 18 may be tin, a tin alloy, etc., and only needs to be able to increase the wettability of the surface of common lead 14, which is not limited herein.
S4: the package is cut from the front surface 120 side and at a position corresponding to the first groove 16 to split the adjacent package units 12, thereby obtaining a single semiconductor package device 11.
Through the design mode, the common pins 14 are cut from the back surface 122 side in the first cutting, the package body 1 is cut from the front surface 120 side in the second cutting corresponding to the first groove 16, and the solderable layer 18, namely tin or tin alloy, is made of soft material, so that short circuit among the common pins 14 caused by damage to the formed solderable layer 18 after the second cutting can be prevented, and the solderable layer 18 can be completely formed on the side surfaces of the common pins 14, so that the wettability of the side surfaces of the common pins 14 is increased, and solder can be adsorbed on the solderable layer more easily.
In one embodiment, as shown in fig. 2b and 2d, the package body 1 is cut from the front surface 120 side at a position corresponding to the first groove 16 to form the second groove 13 on the second metal block 142. Specifically, in the present embodiment, the second groove 13 may be formed by cutting the top portion 100 of the molding layer 10 from the position corresponding to the first groove 16 by a cutting tool having a preset width, or the second groove 13 may be formed by other methods, which is not limited herein. Specifically, the first groove 16 communicates with the second groove 13, and the width of the first groove 16 is the same as the width of the second groove 13, so as to split the adjacent package units 12, thereby obtaining a single semiconductor package device 11.
In another embodiment, please refer to fig. 3, wherein fig. 3 is a schematic structural diagram of another embodiment of step S4 in fig. 1. Specifically, after forming the solderable layer 18 on the surface (not shown) of the common lead 14 exposed from the back surface 122 side, the package is cut from the front surface 120 side at a position corresponding to the first recess 16 to form the second recess 20 on the second metal block 142. Specifically, in the present embodiment, the second groove 20 may be formed by cutting the top portion 100 of the molding layer 10 from the position corresponding to the first groove 16 by a cutting tool having a preset width, or the second groove 20 may be formed by other methods, which is not limited herein. Specifically, in the present embodiment, the first groove 16 communicates with the second groove 20, and the width of the first groove 16 is greater than the width of the second groove 20, so as to split the adjacent packaging units 12, thereby obtaining a single semiconductor package device 21.
In another embodiment, please refer to fig. 4, fig. 4 is a schematic structural diagram of another embodiment of step S4 in fig. 1. Specifically, in the present embodiment, after the solderable layer 18 is formed on the surface (not shown) of the common lead 14 exposed from the back surface 122 side, the package body is cut from the front surface 120 side corresponding to the position of the first groove 16 to continuously remove the second metal block 142 and the adjacent portion of the first metal block 140. Specifically, in the present embodiment, the second groove 22 may be formed by cutting the top portion 100 of the molding layer 10 from the position corresponding to the first groove 16 by a cutting tool having a preset width, or the second groove 22 may be formed by other methods, which is not limited herein. Specifically, in the present embodiment, the second groove 22 is formed on the side of the first metal block 140 away from the back surface 122, the first groove 16 is communicated with the second groove 22, and the width of the first groove 16 is smaller than the width of the second groove 22, so as to split the adjacent packaging units 12, thereby obtaining a single semiconductor packaging device 23.
Specifically, in the present embodiment, as shown in fig. 2a, the second metal block 142 is a rectangular block, but in other embodiments, the second metal block 142 may also be in other shapes, and is not limited herein. Specifically, the second metal block 142 may include a plurality of metal sub-blocks (not shown) stacked one on another, and a width of the metal sub-block close to the first metal block 140 is greater than widths of the other metal sub-blocks. The number of the metal sub-blocks may be one, or may be multiple, for example, two, three, four, and the like, which is not limited herein. When the number of the metal sub-blocks is one, as shown in fig. 2a, the width of the metal sub-block, i.e., the second metal block 142, is smaller than the width of the first metal block 140.
Referring to fig. 5, when the number of the metal sub-blocks is two, fig. 5 is a schematic structural diagram of another embodiment of the package body corresponding to step S1 in fig. 1. Compared with the package 1 in fig. 2a, the rest of the structure is the same as that in fig. 2a except for the second metal block 302, and is not repeated herein. As shown in fig. 5, the common pin 30 includes a first metal block 300 and a second metal block 302 arranged in a stacked manner, specifically, the second metal block 302 is formed by stacking a first metal sub-block 3020 and a second metal sub-block 3022, and the width of the first metal sub-block 3020 close to the first metal block 300 is greater than the width of the second metal sub-block 3022. By analogy, when the second metal block 302 includes a plurality of metal sub-blocks, the width of the metal sub-block close to the first metal block 300 is designed to be larger than the width of other metal sub-blocks, which is not described herein again.
In one embodiment, please refer to fig. 6, where fig. 6 is a schematic structural diagram of another embodiment of step S2 in fig. 1. As shown in fig. 5, when the second metal block 302 includes the first metal sub-block 3020 and the second metal sub-block 3022 which are stacked, the common lead 30 is cut from the back side of the package unit 32 such that the first grooves 34 formed on the common lead 30 continuously penetrate through the portion of the first metal sub-block 3020 adjacent to the first metal block 300, the first metal sub-block 3020 partially remains, and the second metal sub-block 3022 completely remains, so that the subsequent cutting step is performed such that the solderable layer is completely formed on the side surface of the common lead 30.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a semiconductor package device according to an embodiment of the present application. The semiconductor package device provided by the present application includes:
the package unit (not shown), specifically, in the present embodiment, the package unit includes a plurality of pins 46 located at a side surface (not shown) of the package unit. Specifically, the package unit further includes a metal layer 400 and a chip 402, wherein the chip 402 is stacked on the metal layer 400, and the metal layer 400 may be copper, and the like, which is not limited herein. In addition, in the embodiment, the lead 46 includes a first metal block 460 and a second metal block 462 which are stacked, a bottom surface 4600 of the first metal block 460 is flush with the back surface 404 of the packaging unit, an average width of the first metal block 460 is greater than an average width of the second metal block 462, and the first metal block 460 and the second metal block 462 may be made of copper or the like, which is not limited herein.
The molding layer 42 covers the front surface 406 of the package unit, and the surface of the leads 46 near the back surface 404 of the package unit and the side surface (not shown) of the package unit is exposed from the molding layer 42. Specifically, in the present embodiment, the material of the molding layer 42 may be one or more of polyimide, silicone, epoxy resin, and the like, which is not limited in the present application.
The solderable layer 44 covers the surface of the first metal block 460 exposed from the molding layer 42 and the surface of the second metal block 462 exposed from the molding layer 42, and specifically, the material of the solderable layer 44 may be at least one of tin or tin alloy, which is not limited herein.
When the width of the first groove is equal to the width of the second groove when cutting, as shown in fig. 7, the first metal block 460, the second metal block 462 and the side surface 420 of the molding layer 42 are flush, and the solderable layer 44 covers the bottom surface 4600 of the first metal block 460, the side surface 4602 of the first metal block 460 and the side surface 4620 of the portion of the second metal block 462 adjacent to the first metal block 460. In addition, in this embodiment, solderable layer 44 also covers bottom surface 4000 of metal layer 400. In subsequent processing, the remaining surface of side 4620 of second metal block 462 may be covered with a solderable layer 44. By this design, the side of the lead 46 can be completely covered with the solderable layer 44, which increases the wettability of the lead 46 on the side of the package, and thus increases the contact area with the solder.
In one embodiment, please continue to refer to fig. 5, the second metal block 302 is a rectangular block, but the second metal block 302 may have other shapes in other embodiments, which is not limited herein. Specifically, the second metal block 302 may include a plurality of metal sub-blocks arranged in a stack, and a width of a metal sub-block adjacent to the first metal block 300 is greater than widths of other metal sub-blocks, for example, as shown in fig. 5, when the second metal block 302 includes a first metal sub-block 3020 and a second metal sub-block 3022 arranged in a stack, a width of the first metal sub-block 3020 adjacent to the first metal block 300 is greater than a width of the second metal sub-block 3022.
When the width of the first groove is greater than the width of the second groove during dicing and the second metal block 562 of the lead 56 includes a metal sub-block (not shown), please refer to fig. 8, in which fig. 8 is a schematic structural diagram of another embodiment of the semiconductor package device of the present application. Compared with the semiconductor package device in fig. 7, the rest parts except the leads 56 are the same as those in fig. 7, and are not described again. In this embodiment, the second metal block 562 is flush with the side surface 520 of the molding layer 52, the side surface 5600 of the first metal block 560 is recessed relative to the side surface 5620 of the second metal block 562, and the bottom surface 5602 of the second metal block 562 facing the first metal block 560 has a first region 564 exposed from the first metal block 560. The solderable layer 54 covers the bottom surface 5602 of the first metal block 560, the side surfaces of the first metal block 560, and the surface of the first region 564. In addition, in this embodiment, solderable layer 54 also covers bottom surface 5000 of metal layer 500. In subsequent processing, the surface of the side face 5620 of the second metal block 562 may be covered with the solderable layer 54. By this design, the side of the leads 56 can be completely formed with the solderable layer 54, increasing the wettability of the package side leads 56 and thus increasing the contact area with the solder.
When the width of the first groove is greater than the width of the second groove during dicing and the second metal block 662 of the lead 66 includes the first metal sub-block 6620 and the second metal sub-block 6622 which are stacked, please refer to fig. 9, where fig. 9 is a schematic structural diagram of another embodiment of the semiconductor package device of the present application. Compared with the semiconductor package device in fig. 7, the rest parts except the pins 66 are the same as those in fig. 7, and are not described again. In this embodiment, the second metal block 662 is flush with the side surface 620 of the molding layer 62, the side surface 6600 of the first metal block 660 is recessed relative to the side surface 6621 of the first metal sub-block 6620 in the second metal block 662, and the bottom surface 6600 of the second metal block 662 facing the first metal block 660 has a first region 664 exposed from the first metal block 660. The solderable layer 64 covers a bottom surface 6602 of the first metal block 660, a side surface 6600 of the first metal block 660, and a surface (not shown) of the first region 664. In addition, in the present embodiment, the solderable layer 64 also covers the bottom surface 6000 of the metal layer 600. In subsequent processing, the surface of side 6621 of first metal sub-block 6620 and the surface of side 6623 of second metal sub-block 6622 may be covered with solderable layer 64. By this design, the side of the lead 66 can be completely formed with the solderable layer 64, increasing the wettability of the lead 66 on the side of the package, thereby increasing the contact area with the solder.
In summary, different from the situation of the prior art, the first cutting is to cut the first groove from the back side of the common pin, the solderable layer is fully formed on the side surface of the common pin, and the second cutting is to cut the package body from the front side and the position corresponding to the first groove to form the second groove, so that the solderable layer formed by destroying after the second cutting can be prevented from causing short circuit between the pins, the production cost can be reduced, the solderable layer can be completely formed on the side surface of the pin, the wettability of the pin on the side surface of the package is increased, and the contact area with the solder is increased.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings, or which are directly or indirectly applied to other related technical fields, are intended to be included within the scope of the present application.

Claims (10)

1. A method for manufacturing a semiconductor package device, comprising:
providing a packaging body, wherein the packaging body comprises a plastic packaging layer and a plurality of packaging units arranged on the same layer, the plastic packaging layer covers the front sides of the packaging units, and the back sides of the packaging units are exposed out of the plastic packaging layer; a common pin is arranged between the adjacent packaging units, the common pin comprises a first metal block and a second metal block which are arranged in a stacked mode, one side surface of the first metal block is flush with the back surface, and the average width of the first metal block is larger than that of the second metal block; the second metal block is a rectangular block;
cutting the common pin from the back side to form a first groove on the common pin; the first groove continuously penetrates through the first metal block and the adjacent part of the second metal block;
forming a solderable layer on the surface of the common lead exposed from the back side;
and cutting the packaging body from one side of the front surface and the position corresponding to the first groove to split the adjacent packaging units so as to obtain a single semiconductor packaging device.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of cutting the package body from the front surface side and the position corresponding to the first groove to split the adjacent package units comprises:
cutting the packaging body from the position of the front side corresponding to the first groove to form a second groove on the second metal block; the first groove is communicated with the second groove, and the width of the first groove is the same as that of the second groove.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the step of cutting the package body from the front surface side and the position corresponding to the first groove to split the adjacent package units comprises:
cutting the packaging body from the position of the front side corresponding to the first groove to form a second groove on the second metal block; the first groove is communicated with the second groove, and the width of the first groove is larger than that of the second groove.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the step of cutting the package body from the front surface side and the position corresponding to the first groove to split the adjacent package units comprises:
cutting the packaging body from the position of the front side corresponding to the first groove to continuously remove the second metal block and the adjacent part of the first metal block; and a second groove is formed on one side of the first metal block, which is far away from the back surface, the first groove is communicated with the second groove, and the width of the first groove is smaller than that of the second groove.
5. The production method according to claim 1,
the second metal block comprises a plurality of metal sub-blocks which are arranged in a stacked mode, and the width of the metal sub-block close to the first metal block is larger than the width of the other metal sub-blocks.
6. The production method according to claim 5,
when the second metal block includes a plurality of metal sub-blocks arranged in a stacked manner, the common lead is cut from the back surface side so that the first groove formed in the common lead continuously penetrates through the first metal block and a portion of the metal sub-block closest to the first metal block.
7. A semiconductor package device, comprising:
a package unit including a plurality of pins located at a side of the package unit; the pins comprise a first metal block and a second metal block which are arranged in a stacked mode, the bottom surface of the first metal block is flush with the back surface of the packaging unit, and the average width of the first metal block is larger than that of the second metal block; the second metal block is a rectangular block;
the plastic packaging layer covers the front surface of the packaging unit, and the surface of the pin, which is close to the back surface and the side surface, is exposed from the plastic packaging layer;
the weldable layer covers the surface of the first metal block exposed from the plastic package layer and the surface of part of the second metal block exposed from the plastic package layer.
8. The semiconductor package device of claim 7,
the side surfaces of the first metal block, the second metal block and the plastic packaging layer are flush;
the solderable layer covers a bottom surface of the first metal block, side surfaces of the first metal block, and portions of side surfaces of the second metal block adjacent to the first metal block.
9. The semiconductor package device of claim 7,
the second metal block is flush with the side face of the plastic package layer, the side face of the first metal block is retracted relative to the side face of the second metal block, and the bottom face, facing the first metal block, of the second metal block is provided with a first area exposed out of the first metal block;
the solderable layer covers a bottom surface of the first metal block, side surfaces of the first metal block, and a surface of the first region.
10. The semiconductor package device of any one of claims 7-9,
the second metal block comprises a plurality of metal sub-blocks which are arranged in a stacked mode, and the width of the metal sub-block close to the first metal block is larger than the width of the other metal sub-blocks.
CN202110495583.XA 2021-05-07 2021-05-07 Semiconductor packaging device and preparation method thereof Pending CN113380632A (en)

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