CN104064553A - Semiconductor Device And Manufacturing Method Of The Semiconductor Device - Google Patents
Semiconductor Device And Manufacturing Method Of The Semiconductor Device Download PDFInfo
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- CN104064553A CN104064553A CN201310364758.9A CN201310364758A CN104064553A CN 104064553 A CN104064553 A CN 104064553A CN 201310364758 A CN201310364758 A CN 201310364758A CN 104064553 A CN104064553 A CN 104064553A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
A semiconductor device capable of being formed on a sealing part easily and having a shielding effect, and a manufacturing method of the semiconductor device are provided. The manufacturing method of the semiconductor device related by the embodiment comprises the following steps: placing semiconductor chips on installation parts of lead frames which enable first terminals and second terminals thinner than the first terminals to be arranged at intervals aiming at the surroundings of the installation parts, sealing the semiconductor chips and the lead frames through resin, enabling resin forming bottom surfaces to be located in ditches between upper surfaces of the first terminals and upper surfaces of the second terminals, filling the ditches, covering surfaces of the resin, forming conductor layers in a manner that the conductor layers are connected with the first terminals and electrically insulated with the second terminals, and cutting off resin in the thickness direction in a manner that cross sections of conductor layers filled in the ditches are exposed.
Description
Related application
The application enjoys usings No. 2013-56060 (applying date: the priority of on March 19th, 2013) applying for as basis of Japanese publication patent.The application is by the whole content that comprises basis application with reference to this basis application.
Technical field
Embodiments of the present invention relate to the manufacture method of semiconductor device and semiconductor device.
Background technology
In semiconductor device in the past, the seal member of resin semiconductor chip being sealed by metal material covering etc., not sneak into as far as possible from outside noise, or as far as possible discharges noise (following, to be recited as shield effectiveness) to outside.In order to obtain sufficient shield effectiveness, need metal material ground connection.Therefore, propose except the terminal of lead frame to be provided for making at the angle (encapsulation bight) of the bottom surface of semiconductor device the terminal (for example, No. 2002-33444, Japanese Patent Publication communique) of metal material ground connection.
Also have, thin little outline packages) and/or QFP (quad flat package: the occasion of semiconductor device of the structure of terminal is exposed in the side of seal member quad-flat-pack) from as TSOP (Thin small outline package:, if covered until the side of seal member, metal material and terminal conducting by metal material.The area that therefore, can be covered by metal material narrows down.Its result, generation can not obtain the worry of sufficient shield effectiveness.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method that can easily be formed on semiconductor device and the semiconductor device of the conductor layer on seal member with shield effectiveness.
The manufacture method of the semiconductor device that execution mode relates to comprises the following steps: in the 2nd terminal pins that the 1st terminal, Thickness Ratio the 1st terminal is thin, load semiconductor chip on to the installation portion of the lead frame of the spaced apart configuration of the surrounding of installation portion; By resin, semiconductor chip and lead frame are sealed; Make resin form the ditch of bottom surface between the upper surface of the 1st terminal and the upper surface of the 2nd terminal; Fill ditch, and the surface of covering resin, to conduct with the 1st terminal and to form conductor layer with the mode of the 2nd terminal electric insulation; To be filled in the mode of exposing in the cross section of the conductor layer of ditch, at thickness direction, cut off resin.
Embodiment
Below, with reference to accompanying drawing, about execution mode, explain.
(the 1st execution mode)
Fig. 1 is the calcspar of the semiconductor device 100 that relates to of the 1st execution mode.Fig. 1 (a) is the vertical view of semiconductor device 100, and Fig. 1 (b) is the sectional view at the semiconductor device 100 of the line segment X-X of Fig. 1 (a).As shown in Figure 1, semiconductor device 100 is that lead terminal is not from the outstanding QFP of seal member (quad flat non-lead package: the quad flat no-leads encapsulation) semiconductor device of type.Below, with reference to Fig. 1, about the formation of semiconductor device 100, illustrate.
Semiconductor device 100 possesses: lead frame 101, semiconductor chip 102, closing line 103, seal member 104, conductor layer 105.Lead frame 101 possesses: for terminal (the 1st terminal) 101b, other terminal for the installation portion 101a of mounting semiconductor chip 102, ground connection (GND), for example, the 2nd terminal 101c of terminal etc. for signal.
1st, the 2nd terminal 101b, 101c are for the spaced apart configuration of surrounding of installation portion 101a.The point of the 2nd terminal 101c, carries out thinning by etching method and/or stamped method etc.Therefore, the thickness D1 of the 1st terminal 101b, the thickness D2 of point of the 2nd terminal 101c of terminal that is compared to other is thicker.The thickness D2 of the point of the 2nd terminal 101c, thinner than the thickness D1 of the 1st terminal 101b conversely speaking.The thickness D1 of the 1st terminal 101b for example, is 200 μ m ± 10 μ m.The thickness D2 of the point of the 2nd terminal 101c for example, is 100 μ m ± 25 μ m.Moreover back side R1, the R2 of the 1st, the 2nd terminal 101b, 101c, expose from seal member 104.
Semiconductor chip 102 is used small pieces bond material to be bonded on installation portion 101a.The outside of semiconductor chip 102 connects the pad (not shown) of use and the 1st, the 2nd terminal of lead frame 101, by closing line 103 electricity, engages.
Seal member 104, by usining epoxy resin as main component, the thermosetting moulding material that applies silica filled material etc. forms.Seal member 104 is by semiconductor chip 102 and lead frame 101 sealings.Moreover the 1st, the 2nd terminal 101b, 101c, so that the mode that back side R1, R2 expose seals by seal member 104.
At the end face 104a of seal member 104, the position between the upper surface T1 of the 1st terminal 101b and a low side's of the 2nd terminal 101c upper surface T2 (following, to be only recited as upper surface T2) forms step (jump) 104b.Height (thickness) D3 from the lower surface 104c of seal member 104 or the back side R2 of the 2nd terminal 101c to step 104b, thinner than the thickness D1 of the 1st terminal 101b, thicker than the thickness D2 of the 2nd terminal 101c.In a word, thickness D1～D3 meets following (1) formula.
D1>D3>D2···(1)
Also have, height (thickness) D3 from the lower surface 104c of seal member 104 to step 104b, preferably, than the thickness D1 of the 1st terminal 101b thin (low) 20 μ m left and right.Conductor layer 105 described later and the 1st terminal 101b conducting reliably, become the state of electrical connection that is.Also have, height (thickness) D3 from the lower surface 104c of seal member 104 to step 104b, preferably, than the thickness D2 of the 2nd terminal 101c thick (height) 35 μ m left and right.Therefore, conductor layer 105 described later and the 2nd not conducting of terminal 101c.
Conductor layer 105 covers compares the seal member 104 of upside with step 104b.Conductor layer 105, in the step 104b of the end face 104a of seal member 104, directly contacts with the 1st terminal 101b.Conductor layer 105, is formed by the material with electric conductivity.Therefore, conductor layer 105, is directly electrically connected to the 1st terminal 101b.Conductor layer 105, can form by sintering or sclerosis after coating conductive paste, by chemical plating, forms.
Fig. 2 is the vertical view by the state of seal member 104 sealing wire frames 101 and semiconductor chip 102.As shown in Figure 2, in the manufacture of semiconductor device, once by a plurality of semiconductor chip sealings.Moreover, in Fig. 2, with solid line, represent the 1st line of cut (hemisection), dot the 2nd line of cut (entirely cutting).
Fig. 3～Fig. 5 is the sectional view of the line segment Y-Y of Fig. 2.Below, with reference to Fig. 3～Fig. 5, about the manufacture method of semiconductor device 100, illustrate.Moreover, from the state by seal member 104 sealing semiconductor chips 102 and lead frame 101, about the manufacture method of semiconductor device 100, (Fig. 3 (a) with reference to) is described.
When starting, use blade B, along the 1st line of cut (solid line) as shown in Figure 2, carry out hemisection (with reference to Fig. 3 (b)).Here, as shown in Fig. 4 (a), the height of adjusting blade B carries out hemisection, so that the height D3 from the lower surface 104c of seal member 104 to the lower end of blade B is thinner than the thickness D1 of the 1st terminal 101b, thicker than the thickness D2 of the 2nd terminal 101c.According to this hemisection, at 104 two ends of seal member 104, form ditch G (with reference to Fig. 4 (b)).As shown in Fig. 4 (b), the lower surface S1 of ditch G, is positioned between the upper surface T1 of the 1st terminal 101b and a low side's of the 2nd terminal 101c upper surface T2.
Moreover, as narrated, from the lower surface 104c of seal member 104 till the height D3 of the lower end of blade B, preferably, than the low 20 μ m left and right of the thickness D1 of the 1st terminal 101b.Due to low 20 μ m left and right, can make reliably the 1st terminal 101b expose.Its result, the 1st terminal 101b and conductor layer 105 conducting reliably.Also have, from the lower surface 104c of seal member 104 till the height D3 of the lower end of blade B, preferably, than the thickness D2 of the 2nd terminal 101c thick (height) 35 μ m left and right.Therefore, conductor layer 105 and the 2nd not conducting of terminal 101c.
Secondly, on the surface of seal member 104, by print process, be coated with conductivity sizing.At this moment, in ditch G, also fill conductor sizing.Secondly, sintering or sclerosis conductor sizing, obtain conductor layer 105 (with reference to Fig. 4 (c)).Conductor sizing is the material disperseing such as the high powder of the conductivity that makes silver (Ag) and/or copper (Cu) etc. in thermosetting resin.For example, moreover the surface-coated chemical plating catalyst (, palladium (Pa)) of the seal member 104 that conductor layer 105 also can be within comprising ditch G afterwards, carries out electroless copper and forms.
Secondly, use blade B, along the 2nd line of cut (dotted line) as shown in Figure 2, entirely cut (with reference to Fig. 5 (a)).By this, entirely cut, cut off lead frame 101, can obtain the semiconductor device 100 (with reference to Fig. 5 (b)) of the individuation of the cross section of conductor layer 105 exposing.
As more than, in semiconductor device 100, make the thickness D1 of ground connection (GND) the terminal 101b of lead frame 101, the thickness D2 of the 2nd terminal 101c that is compared to other terminals is thicker, by seal member 104 hemisections, forms thus the ditch G that only makes the 1st terminal 101b expose.After this, to fill the mode of ditch G, form conductor layer 105.
Therefore, can easily on seal member 104, form the conductor layer 105 with shield effectiveness.Also have, due to until the end face 104a of seal member 104 by conductor layer 105, covered, so improve the shield effectiveness based on conductor layer 105.And, as former semiconductor device, due to conductor layer 105 ground connection, do not need to arrange other terminal etc., can suppress the increase of number of steps.Its result, can suppress to possess the manufacturing cost of the semiconductor device 100 of conductor layer 105.
(the 2nd execution mode)
Fig. 6 is the calcspar of the semiconductor device 200 that relates to of the 2nd execution mode.Fig. 6 (a) is the vertical view of semiconductor device 200, and Fig. 6 (b) is the sectional view of semiconductor device 200 of the line segment Z-Z of Fig. 6 (a).Semiconductor device 200 is that lead terminal is not from the outstanding QFP of seal member (quad flatnon-lead package: the quad flat no-leads encapsulation) semiconductor device of type.Below, with reference to Fig. 6, about the formation of semiconductor device 200, illustrate.Moreover for the identical formation of the semiconductor device 100 with reference to Fig. 1～Fig. 5 explanation, the repetitive description thereof will be omitted for additional same symbol.
Semiconductor device 200 possesses: lead frame 201, semiconductor chip 102, closing line 103, seal member 204, conductor layer 105.Lead frame 201 possesses: other terminal (the 2nd terminal) 201c for installation portion 201a, ground connection (GND) terminal (the 1st terminal) 201b of mounting semiconductor chip 102, signal with terminal etc.
1st, the 2nd terminal 201b, 201c are for the spaced apart configuration of surrounding of installation portion 201a.In the 2nd execution mode, the point of the 2nd terminal 201c is not by thinning, and the thickness D5 of the thickness D4 of the 1st terminal 201b and the 2nd terminal 201c is identical haply.
Therefore,, in this semiconductor device 200, at seal member 204, the hole H that formation is exposed the upper surface T1 of the 1st terminal 201b, is filled in the H of this hole by conductor layer 205, makes thus the 1st terminal 201b and conductor layer 105 conductings as ground connection (GND) terminal.Moreover hole H also can form for every the 1st terminal 201b.Also have, in the occasion that can obtain sufficient conducting, the number of hole H also can be few unlike the number of the 1st terminal 201b.
Seal member 204, is to using epoxy resin as main component, applies the thermosetting moulding material of silica filled material etc., by semiconductor chip 102 and lead frame 201 sealings.Also have, at the end face 204a of seal member 204, form step 204b.In this execution mode, step 204b is in the high position of upper surface T2 than the 2nd terminal 201c, so that conductor layer 105 and the 2nd not conducting of terminal 201c.
Fig. 7, Fig. 8 are the manufacturing step figure of semiconductor device 200.Below, about the manufacture method of semiconductor device 200 as shown in Figure 6 with reference to Fig. 2, Fig. 7, Fig. 8 explanation.Moreover, from the state by seal member 204 sealing semiconductor chips 102 and lead frame 201, about the manufacture method of semiconductor device 200, (with reference to Fig. 7 (a)) is described.
When starting, use blade B, along the 1st line of cut (solid line) as shown in Figure 2, carry out hemisection (with reference to Fig. 7 (b)).According to this hemisection, at the two ends of seal member 204, form ditch G (with reference to Fig. 7 (c)).Also have, use laser, at seal member 204, the hole H (with reference to Fig. 7 (c)) that formation is exposed the upper surface T1 of the 1st terminal 201b.
Moreover, the position of the lower end of blade B, preferably, from the high 35 μ m left and right of upper surface T2 of the 2nd terminal 201c.Make conductor layer 105 and the 2nd not conducting of terminal 201c.
Secondly, on the surface of seal member 204, by print process, be coated with conductivity sizing.At this moment, in the ditch G forming at seal member 204 and also can fill conductor sizing in the H of hole.Secondly, sintering or sclerosis conductor sizing obtain conductor layer 105 (with reference to Fig. 8 (a)).For example, moreover the surface-coated chemical plating catalyst (, palladium (Pa)) of the seal member 204 that conductor layer 105 also can be within comprising ditch G and hole H afterwards, carries out electroless copper and forms.
Secondly, use blade B, along the 2nd line of cut (dotted line) as shown in Figure 2, entirely cut (with reference to Fig. 8 (b)).By this, entirely cut, cut off lead frame 201, can obtain the semiconductor device 200 (with reference to Fig. 8 (c)) of the individuation of the cross section of conductor layer 105 exposing.
As more than, in semiconductor device 200, at seal member 204, after forming and make hole H that the upper surface T1 as the 1st terminal 201b of ground connection (GND) terminal exposes by laser, in the mode of filling in the H of this hole, form conductor layer 105.
Therefore, at the thickness D4 of the 1st terminal 201b as ground connection (GND) terminal with as other the thickness D5 identical occasion haply of the 2nd terminal 201c of terminal, also can easily on seal member 204, form the conductor layer 105 with shield effectiveness.Other effect, the effect of the semiconductor device 100 relating to the 1st execution mode is identical.
(variation of execution mode)
In the manufacturing step of the semiconductor device 200 that the semiconductor device 100 that above-mentioned the 1st execution mode relates to and the 2nd execution mode relate to, the 1st line of cut (hemisection), the 2nd line of cut (entirely cutting), in different positions, still also can make the 1st, the 2nd line of cut identical.In this occasion, in the side of seal member 104,204, also form conductor layer 105, therefore, the thickness of the thickness of the blade that (during hemisection) used for the first time blade that preferably (while entirely cutting) used than is for the second time thicker.Also have, about lead terminal, from the semiconductor device of the outstanding QFP of seal member (quad flat non-lead package: quad flat no-leads encapsulates) type, be not illustrated, for example, but about other semiconductor device, the semiconductor device of TSOP type also can be suitable for.
And, in the semiconductor device 200 that the 2nd execution mode relates to, about the thickness of ground connection (GND) terminal (the 1st terminal 201b) and the thickness of terminal in addition (the 2nd terminal 201c) haply identical occasion be illustrated.Yet, in the semiconductor device 100 relating at the 1st execution mode, in order to make the conducting of the 1st terminal 101b and conductor layer 105 more reliable, also can adopt laser, at seal member 104, the hole H that formation is exposed the upper surface T1 of the 1st terminal 101b.
(other execution mode)
Above, although explanation several embodiments of the present invention, these embodiment are just as illustration, rather than restriction scope of invention.These embodiment can various forms implement, and in the scope that does not depart from the main idea of invention, can carry out various omissions, displacement, change.These embodiment and distortion thereof are also that scope of invention, main idea comprise, and are also simultaneously that invention and the impartial scope thereof described in the scope of claim comprises.
Accompanying drawing explanation
Fig. 1 is the calcspar of the semiconductor device that relates to of the 1st execution mode.
Fig. 2 is vertical view in the manufacture way of the semiconductor device that relates to of the 1st execution mode.
Fig. 3 is the manufacturing step figure of the semiconductor device that relates to of the 1st execution mode.
Fig. 4 is the manufacturing step figure of the semiconductor device that relates to of the 1st execution mode.
Fig. 5 is the manufacturing step figure of the semiconductor device that relates to of the 1st execution mode.
Fig. 6 is the calcspar of the semiconductor device that relates to of the 2nd execution mode.
Fig. 7 is the manufacturing step figure of the semiconductor device that relates to of the 2nd execution mode.
Fig. 8 is the manufacturing step figure of the semiconductor device that relates to of the 2nd execution mode.
The explanation of symbol
100,200 ... semiconductor device, 101,201 ... lead frame, 101a, 201a ... installation portion, 101b, 201b ... the 1st terminal, 101c, 201c ... the 2nd terminal, 102 ... semiconductor chip, 103 ... closing line, 104,204 ... seal member, 104a, 204a ... end face, 104b, 204b ... step, 104c, 204c ... bottom surface, 105,205 ... conductor layer.
Claims (6)
1. a manufacture method for semiconductor device, is characterized in that, comprises the following steps:
The 1st terminal, the 2nd terminal that above-mentioned the 1st terminal of Thickness Ratio is thin are being loaded to semiconductor chip on the above-mentioned installation portion of the lead frame of the spaced apart configuration of surrounding of installation portion;
By resin, above-mentioned semiconductor chip and above-mentioned lead frame are sealed;
At above-mentioned resin, form the ditch of bottom surface between the upper surface of above-mentioned the 1st terminal and the upper surface of above-mentioned the 2nd terminal;
Fill above-mentioned ditch, and, the surface of above-mentioned resin covered, to conduct and to form conductor layer with the mode of above-mentioned the 2nd terminal electric insulation with above-mentioned the 1st terminal;
To be filled in the mode of exposing in the cross section of the conductor layer of above-mentioned ditch, at thickness direction, cut off above-mentioned resin.
2. a semiconductor device, is characterized in that, comprising:
Lead frame by thin the 2nd terminal of the 1st terminal, above-mentioned the 1st terminal of Thickness Ratio in the spaced apart configuration of surrounding of installation portion;
The semiconductor chip of installing at above-mentioned installation portion;
Seal member, by above-mentioned semiconductor chip and the sealing of above-mentioned lead frame, has the step forming in the upper surface of above-mentioned the 1st terminal and the position between the upper surface of above-mentioned the 2nd terminal of end face;
Conductor layer contacts with the upper surface of above-mentioned the 1st terminal in above-mentioned step, and covers above-mentioned seal member.
3. a semiconductor device, is characterized in that, comprising:
Lead frame by thin the 2nd terminal of the 1st terminal, above-mentioned the 1st terminal of Thickness Ratio in the spaced apart configuration of surrounding of installation portion;
The semiconductor chip of installing at above-mentioned installation portion;
Seal member, by the sealing of above-mentioned semiconductor chip and above-mentioned lead frame, has at upper surface and makes the hole that above-mentioned the 1st terminal exposes and the step forming at end face;
Conductor layer, is filled in above-mentioned hole, from the above-mentioned seal member of above-mentioned Step Coverage upside.
4. semiconductor device as claimed in claim 2 or claim 3, is characterized in that,
Expose from above-mentioned seal member at the back side above-mentioned the 1st, the 2nd terminal.
5. semiconductor device as claimed in claim 2 or claim 3, is characterized in that,
Above-mentioned end face is the cross section of cutting being formed by cutting blade.
6. a manufacture method for semiconductor device, is characterized in that, comprises the following steps:
The 1st terminal and the 2nd terminal are being loaded to semiconductor chip on the above-mentioned installation portion of the lead frame of the spaced apart configuration of surrounding of installation portion;
By resin, above-mentioned semiconductor chip and above-mentioned lead frame are sealed;
At above-mentioned resin, in bottom surface, be positioned at the position formation ditch that the upper surface of above-mentioned the 1st terminal and the upper surface of above-mentioned the 2nd terminal do not expose;
The position of exposing at the upper surface of above-mentioned the 1st terminal at above-mentioned resin forms opening;
Fill above-mentioned ditch and opening, and, the surface of above-mentioned resin covered, to conduct and to form conductor layer with the mode of above-mentioned the 2nd terminal electric insulation with above-mentioned the 1st terminal;
To be filled in the mode of exposing in the cross section of the conductor layer of above-mentioned ditch, at thickness direction, cut off above-mentioned resin.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013056060A JP5802695B2 (en) | 2013-03-19 | 2013-03-19 | Semiconductor device and method for manufacturing semiconductor device |
| JP056060/2013 | 2013-03-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104064553A true CN104064553A (en) | 2014-09-24 |
Family
ID=51552195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310364758.9A Pending CN104064553A (en) | 2013-03-19 | 2013-08-20 | Semiconductor Device And Manufacturing Method Of The Semiconductor Device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP5802695B2 (en) |
| CN (1) | CN104064553A (en) |
| TW (1) | TWI552235B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107004648A (en) * | 2014-11-20 | 2017-08-01 | 日本精工株式会社 | Electro part carrying heat-radiating substrate |
| CN107004647A (en) * | 2014-11-20 | 2017-08-01 | 日本精工株式会社 | Electro part carrying heat-radiating substrate |
| CN107546196A (en) * | 2016-06-29 | 2018-01-05 | 三菱电机株式会社 | Semiconductor device and its manufacture method |
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| CN109698187A (en) * | 2017-10-20 | 2019-04-30 | 日月光半导体制造股份有限公司 | Semiconductor device packages |
| CN114657528A (en) * | 2020-12-22 | 2022-06-24 | 江苏长电科技股份有限公司 | Temporary carrier plate for coating QFN packaging part and coating method of QFN packaging part |
| US11557566B2 (en) | 2016-11-03 | 2023-01-17 | Stmicroelectronics (Grenoble 2) Sas | Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107004648B (en) * | 2014-11-20 | 2019-04-23 | 日本精工株式会社 | Electro part carrying heat-radiating substrate |
| CN107004647A (en) * | 2014-11-20 | 2017-08-01 | 日本精工株式会社 | Electro part carrying heat-radiating substrate |
| CN107004647B (en) * | 2014-11-20 | 2019-05-03 | 日本精工株式会社 | Electro part carrying heat-radiating substrate |
| CN107004648A (en) * | 2014-11-20 | 2017-08-01 | 日本精工株式会社 | Electro part carrying heat-radiating substrate |
| CN107851619A (en) * | 2015-07-07 | 2018-03-27 | 青井电子株式会社 | The manufacture method of semiconductor device and semiconductor device |
| CN108352361A (en) * | 2015-10-12 | 2018-07-31 | 英帆萨斯公司 | Wire bonding line for interference shielding |
| CN108352361B (en) * | 2015-10-12 | 2021-05-04 | 英帆萨斯公司 | Lead bonding wire for interference shielding |
| CN107546196A (en) * | 2016-06-29 | 2018-01-05 | 三菱电机株式会社 | Semiconductor device and its manufacture method |
| CN108022909A (en) * | 2016-11-03 | 2018-05-11 | 意法半导体(格勒诺布尔2)公司 | The method being electrically connected and electronic device are formed between electronic chip and carrier substrates |
| US11557566B2 (en) | 2016-11-03 | 2023-01-17 | Stmicroelectronics (Grenoble 2) Sas | Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device |
| CN109698187A (en) * | 2017-10-20 | 2019-04-30 | 日月光半导体制造股份有限公司 | Semiconductor device packages |
| CN114657528A (en) * | 2020-12-22 | 2022-06-24 | 江苏长电科技股份有限公司 | Temporary carrier plate for coating QFN packaging part and coating method of QFN packaging part |
| CN114657528B (en) * | 2020-12-22 | 2023-12-05 | 江苏长电科技股份有限公司 | Temporary carrier plate for coating QFN package and QFN package coating method |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI552235B (en) | 2016-10-01 |
| JP5802695B2 (en) | 2015-10-28 |
| TW201438119A (en) | 2014-10-01 |
| JP2014183142A (en) | 2014-09-29 |
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