TWI552235B - Semiconductor device, semiconductor device manufacturing method - Google Patents
Semiconductor device, semiconductor device manufacturing method Download PDFInfo
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- TWI552235B TWI552235B TW102129025A TW102129025A TWI552235B TW I552235 B TWI552235 B TW I552235B TW 102129025 A TW102129025 A TW 102129025A TW 102129025 A TW102129025 A TW 102129025A TW I552235 B TWI552235 B TW I552235B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Description
本申請案享有將日本專利申請案第2013-56060號(申請日:2013年3月19日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。 This application claims priority from Japanese Patent Application No. 2013-56060 (filing date: March 19, 2013) as a basic application. This application contains the entire contents of the basic application by reference to the basic application.
本發明之實施形態係關於半導體裝置及半導體裝置之製造方法。 Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the semiconductor device.
於先前之半導體裝置中,存在將為盡量不混入來自外部之雜訊,或盡量不向外部放出雜訊(以下,記述為「屏蔽效果」)而密封半導體晶片之樹脂等之密封構件以金屬材料覆蓋者。為得到充分之屏蔽效果,必需將金屬材料接地。因此,提出有有別於引線框架之端子,而將用於使金屬材料接地之端子另外設置於半導體裝置之底面之角(封裝角部)(例如,日本專利公開公報2002-33444號)。 In the conventional semiconductor device, there is a sealing member which is a resin which seals a semiconductor wafer so as not to mix noise from the outside as much as possible, or to emit noise (hereinafter, referred to as "shielding effect" as much as possible). Coverage. In order to obtain adequate shielding, it is necessary to ground the metal material. Therefore, a terminal different from the lead frame is proposed, and a terminal for grounding the metal material is additionally provided at the corner (package corner) of the bottom surface of the semiconductor device (for example, Japanese Patent Laid-Open Publication No. 2002-33444).
又,如TSOP(Thin small outline package:薄型小尺寸封裝)或QFP(quad flat package:四邊平面封裝)般自密封構件之側面露出端子之構造之半導體裝置之情形時,若以金屬材料覆蓋密封構件之側面為止,則金屬材料與端子會導通。因此,可以金屬材料覆蓋之面積變窄。其結果,產生無法得到充分之屏蔽效果之顧慮。 Further, in the case of a semiconductor device having a structure in which a terminal is exposed from a side surface of a sealing member like a TSOP (Thin small outline package) or a QFP (quad flat package), the sealing member is covered with a metal material. The metal material and the terminal are electrically connected to the side. Therefore, the area covered by the metal material can be narrowed. As a result, there is a concern that a sufficient shielding effect cannot be obtained.
本發明之目的在於提供一種可於密封構件上,容易地形成具有屏蔽效果之導體層之半導體裝置及半導體裝置之製造方法。 An object of the present invention is to provide a semiconductor device and a method of manufacturing a semiconductor device which can easily form a conductor layer having a shielding effect on a sealing member.
實施形態之半導體裝置之製造方法包含以下步驟:將半導體晶片載置於在安裝部之周圍相離配置有第1端子及厚度較第1端子更薄之第2端子之引線框架之安裝部上;以樹脂密封半導體晶片及引線框架;於樹脂中形成底面位於第1端子之上表面與第2端子之上表面之間之槽;填充槽且被覆樹脂之表面,並以與第1端子電性導通且與第2端子電性絕緣之方式形成導體層;及以填充於槽內之導體層之剖面露出之方式將樹脂於厚度方向上切斷。 A method of manufacturing a semiconductor device according to an embodiment includes the steps of: placing a semiconductor wafer on a mounting portion of a lead frame in which a first terminal and a second terminal having a thickness smaller than a first terminal are disposed apart from each other around a mounting portion; Sealing the semiconductor wafer and the lead frame with a resin; forming a groove in the resin between the upper surface of the first terminal and the upper surface of the second terminal; filling the groove and covering the surface of the resin, and electrically conducting with the first terminal Further, the conductor layer is formed to be electrically insulated from the second terminal; and the resin is cut in the thickness direction so that the cross section of the conductor layer filled in the groove is exposed.
100‧‧‧半導體裝置 100‧‧‧Semiconductor device
101‧‧‧引線框架 101‧‧‧ lead frame
101a‧‧‧安裝部 101a‧‧‧Installation Department
101b‧‧‧第1端子 101b‧‧‧1st terminal
101c‧‧‧第2端子 101c‧‧‧2nd terminal
102‧‧‧半導體晶片 102‧‧‧Semiconductor wafer
103‧‧‧焊接線 103‧‧‧welding line
104‧‧‧密封構件 104‧‧‧ Sealing member
104a‧‧‧端面 104a‧‧‧ end face
104b‧‧‧階差 104b‧‧ ‧ step
104c‧‧‧底面 104c‧‧‧ bottom
105‧‧‧導體層 105‧‧‧Conductor layer
200‧‧‧半導體裝置 200‧‧‧Semiconductor device
201‧‧‧引線框架 201‧‧‧ lead frame
201a‧‧‧安裝部 201a‧‧‧Installation Department
201b‧‧‧第1端子 201b‧‧‧1st terminal
201c‧‧‧第2端子 201c‧‧‧2nd terminal
204‧‧‧密封構件 204‧‧‧ Sealing members
204a‧‧‧端面 204a‧‧‧ end face
204b‧‧‧階差 204b‧‧ ‧ step
205‧‧‧導體層 205‧‧‧ conductor layer
B‧‧‧刀片 B‧‧‧blade
D1‧‧‧第1端子之厚度 D1‧‧‧ thickness of the first terminal
D2‧‧‧第2端子之前端部之厚度 D2‧‧‧ Thickness of the front end of the 2nd terminal
D3‧‧‧自密封構件之底面至階差之高度(厚度) D3‧‧‧ Height from the bottom of the self-sealing member to the step (thickness)
D3‧‧‧自密封構件之底面至刀片之下端之高度 D3‧‧‧ Height from the bottom of the sealing member to the lower end of the blade
D4‧‧‧第1端子之厚度 D4‧‧‧ thickness of the first terminal
D5‧‧‧第2端子之厚度 D5‧‧‧ thickness of the second terminal
G‧‧‧槽 G‧‧‧ slot
H‧‧‧孔 H‧‧‧ hole
R1‧‧‧第1端子之底背面 The bottom of the R1‧‧1 first terminal
R2‧‧‧第2端子之底背面 R2‧‧‧ bottom of the second terminal
S1‧‧‧槽之底面 S1‧‧‧ underside of the trough
T1‧‧‧第1端子之上表面 Top surface of T1‧‧‧1st terminal
T2‧‧‧第2端子之較低部位之上表面 T2‧‧‧ Upper surface of the lower part of the second terminal
圖1(a)、(b)係第1實施形態之半導體裝置之構成圖。 1(a) and 1(b) are configuration diagrams of a semiconductor device according to a first embodiment.
圖2係第1實施形態之半導體裝置之製造中途之俯視圖。 Fig. 2 is a plan view showing the middle of the manufacture of the semiconductor device of the first embodiment.
圖3(a)、(b)係第1實施形態之半導體裝置之製造流程圖。 3(a) and 3(b) are flowcharts showing the manufacture of the semiconductor device of the first embodiment.
圖4(a)~(c)係第1實施形態之半導體裝置之製造流程圖。 4(a) to 4(c) are flowcharts showing the manufacture of the semiconductor device of the first embodiment.
圖5(a)、(b)係第1實施形態之半導體裝置之製造流程圖。 5(a) and 5(b) are flowcharts showing the manufacture of the semiconductor device of the first embodiment.
圖6(a)、(b)係第2實施形態之半導體裝置之構成圖。 6(a) and 6(b) are views showing the configuration of a semiconductor device according to a second embodiment.
圖7(a)~(c)係第2實施形態之半導體裝置之製造流程圖。 7(a) to 7(c) are flowcharts showing the manufacture of the semiconductor device of the second embodiment.
圖8(a)~(c)係第2實施形態之半導體裝置之製造流程圖。 8(a) to 8(c) are flowcharts showing the manufacture of the semiconductor device of the second embodiment.
以下,參照圖式,針對實施形態進行詳細說明。 Hereinafter, embodiments will be described in detail with reference to the drawings.
(第1實施形態) (First embodiment)
圖1係第1實施形態之半導體裝置100之構成圖。圖1(a)係半導體裝置100之俯視圖,圖1(b)係圖1(a)之線段X-X之半導體裝置100之剖面圖。如圖1所示般,半導體裝置100係引線端子不自密封構件凸出之QFP(quad flat non-lead package:無引線四邊平面封裝)型之半導體裝 置。以下,參照圖1針對半導體裝置100之構成進行說明。 Fig. 1 is a configuration diagram of a semiconductor device 100 according to the first embodiment. 1(a) is a plan view of a semiconductor device 100, and FIG. 1(b) is a cross-sectional view of the semiconductor device 100 of the line segment X-X of FIG. 1(a). As shown in FIG. 1 , the semiconductor device 100 is a QFP (quad flat non-lead package) type semiconductor device in which the lead terminals are not protruded from the sealing member. Set. Hereinafter, the configuration of the semiconductor device 100 will be described with reference to FIG. 1 .
半導體裝置100包含引線框架101、半導體晶片102、焊接線103、密封構件104、及導體層105。引線框架101包含用於安裝半導體晶片102之安裝部101a、接地(GND:Ground)用端子(第1端子)101b、及其他端子例如,訊號用端子等第2端子101c。 The semiconductor device 100 includes a lead frame 101, a semiconductor wafer 102, a bonding wire 103, a sealing member 104, and a conductor layer 105. The lead frame 101 includes a mounting portion 101a for mounting the semiconductor wafer 102, a ground (GND: ground) terminal (first terminal) 101b, and other terminals such as a second terminal 101c such as a signal terminal.
第1,第2端子101b、101c係離間於安裝部101a之周圍而配置。第2端子101c之前端部係藉由蝕刻或壓印加工等進行薄化。因此,第1端子101b之厚度D1較其他端子即第2端子101c之前端部之厚度D2更厚。相反而言,第2端子101c之前端部之厚度D2較第1端子101b之厚度D1更薄。第1端子101b之厚度D1例如為200μm±10μm。第2端子101c之前端部之厚度D2例如為100μm±25μm。另,第1、第2端子101b、101c之底背面R1、R2自密封構件104露出。 The first and second terminals 101b and 101c are disposed apart from each other around the mounting portion 101a. The front end of the second terminal 101c is thinned by etching or imprinting or the like. Therefore, the thickness D1 of the first terminal 101b is thicker than the thickness D2 of the front end portion of the second terminal 101c which is another terminal. On the contrary, the thickness D2 of the front end portion of the second terminal 101c is thinner than the thickness D1 of the first terminal 101b. The thickness D1 of the first terminal 101b is, for example, 200 μm ± 10 μm . The thickness D2 of the front end portion of the second terminal 101c is, for example, 100 μm ± 25 μm . Further, the bottom and back surfaces R1 and R2 of the first and second terminals 101b and 101c are exposed from the sealing member 104.
半導體晶片102使用黏晶接著於安裝部101a上。半導體晶片102之外部連接用之焊墊(未圖示)與引線框架101之第1、第2端子係藉由焊接線103而電性接合。 The semiconductor wafer 102 is bonded to the mounting portion 101a using a die bond. A pad (not shown) for external connection of the semiconductor wafer 102 and the first and second terminals of the lead frame 101 are electrically joined by a bonding wire 103.
密封構件104以環氧樹脂作為主成分,以添加有氧化矽填充材等之熱硬化性成形材料構成。密封構件104密封半導體晶片102及引線框架101。另,第1、第2端子101b、101c露出底背面R1、R2,並藉由密封構件104密封。 The sealing member 104 is made of a thermosetting molding material to which a cerium oxide filler or the like is added, using an epoxy resin as a main component. The sealing member 104 seals the semiconductor wafer 102 and the lead frame 101. Further, the first and second terminals 101b and 101c expose the bottom and back sides R1 and R2, and are sealed by the sealing member 104.
於密封構件104之端面104a上,在第1端子101b之上表面T1與第2端子101c之較低部位之上表面T2(以下,簡單記述為「上表面T2」)之間形成階差104b。自密封構件104之底面104c或第2端子101c之底背面R2至階差104b之高度(厚度)D3,較第1端子101b之厚度D1更薄,而較第2端子101c之厚度D2更厚。即,厚度D1~D3滿足以下式(1)。 On the end surface 104a of the sealing member 104, a step 104b is formed between the upper surface T1 of the first terminal 101b and the upper surface T2 of the lower portion of the second terminal 101c (hereinafter simply referred to as "upper surface T2"). The height (thickness) D3 of the bottom surface 104c of the self-sealing member 104 or the bottom surface R2 of the second terminal 101c to the step 104b is thinner than the thickness D1 of the first terminal 101b and thicker than the thickness D2 of the second terminal 101c. That is, the thicknesses D1 to D3 satisfy the following formula (1).
D1>D3>D2‧‧‧(1) D1>D3>D2‧‧‧(1)
另,自密封構件104之底面104c至階差104b之高度(厚度)D3,以 較第1端子101b之厚度D1薄(低)20μm左右為佳。其係為使後述之導體層105與第1端子101b確實地導通,即成為電性連接之狀態。又,自密封構件104之底面104c至階差104b之高度(厚度)D3,以較第2端子101c之厚度D2厚(高)35μm左右為佳。其係為使後述之導體層105與第2端子101c不導通。 In addition, the height (thickness) D3 of the bottom surface 104c of the self-sealing member 104 to the step 104b is It is preferable that the thickness D1 of the first terminal 101b is thin (low) about 20 μm. This is a state in which the conductor layer 105 to be described later and the first terminal 101b are surely electrically connected, that is, in a state of being electrically connected. Further, the height (thickness) D3 of the bottom surface 104c of the self-sealing member 104 to the step 104b is preferably about 35 μm thicker than the thickness D2 of the second terminal 101c. This is to prevent the conductor layer 105, which will be described later, from being electrically disconnected from the second terminal 101c.
導體層105自階差104b被覆上側之密封構件104。導體層105於密封構件104之端面104a之階差104b上,與第1端子101b直接接觸。導體層105係以具有電性導電性之材料形成。因此,導體層105與第1端子101b直接電性連接。導體層105可藉由塗佈導電性糊料後進行燒結或硬化而形成,或藉由無電解電鍍形成。 The conductor layer 105 is covered with the sealing member 104 on the upper side from the step difference 104b. The conductor layer 105 is in direct contact with the first terminal 101b on the step 104b of the end surface 104a of the sealing member 104. The conductor layer 105 is formed of a material having electrical conductivity. Therefore, the conductor layer 105 is directly electrically connected to the first terminal 101b. The conductor layer 105 can be formed by applying a conductive paste, sintering or hardening, or by electroless plating.
圖2係將引線框架101及半導體晶片102以密封構件104密封之狀態之俯視圖。如圖2所示般,在半導體裝置之製造中將複數片半導體晶片一次密封。另,圖2係以實線表示第1切割線(半切割),以虛線表示第2切割線(全切割)。 2 is a plan view showing a state in which the lead frame 101 and the semiconductor wafer 102 are sealed by a sealing member 104. As shown in FIG. 2, a plurality of semiconductor wafers are once sealed in the manufacture of a semiconductor device. In addition, in FIG. 2, the 1st cut line (half cut) is shown by the solid line, and the 2nd cut line (full cut) is shown by the broken line.
圖3~圖5係圖2之線段Y-Y之剖面圖。以下,參照圖3~圖5針對半導體裝置100之製造方法進行說明。另,根據以密封構件104密封半導體晶片102及引線框架101之狀態說明半導體裝置100之製造方法(參照圖3(a))。 3 to 5 are sectional views of the line segment Y-Y of Fig. 2. Hereinafter, a method of manufacturing the semiconductor device 100 will be described with reference to FIGS. 3 to 5 . Further, a method of manufacturing the semiconductor device 100 will be described based on a state in which the semiconductor wafer 102 and the lead frame 101 are sealed by the sealing member 104 (see FIG. 3(a)).
首先,使用刀片B沿著圖2所示之第1切割線(實線)進行半切割(參照圖3(b))。此處,如圖4(a)所示般,為使自密封構件104之底面104c至刀片B之下端之高度D3較第1端子101b之厚度D1更薄,且較第2端子101c之厚度D2更厚,調整刀片B之高度並進行半切割。藉由該半切割而於密封構件104之兩端形成槽G(參照圖4(b))。如圖4(b)所示般,槽G之底面S1位於第1端子101b之上表面T1與第2端子101c之較低部位之上表面T2之間。 First, the blade B is half-cut along the first cutting line (solid line) shown in Fig. 2 (see Fig. 3(b)). Here, as shown in FIG. 4(a), the height D3 of the bottom surface 104c of the self-sealing member 104 to the lower end of the blade B is thinner than the thickness D1 of the first terminal 101b, and is smaller than the thickness D2 of the second terminal 101c. Thicker, adjust the height of the blade B and perform a half cut. The groove G is formed at both ends of the sealing member 104 by the half cutting (refer to FIG. 4(b)). As shown in FIG. 4(b), the bottom surface S1 of the groove G is located between the upper surface T1 of the first terminal 101b and the upper surface T2 of the lower portion of the second terminal 101c.
另,如已闡述般,自密封構件104之底面104c至刀片B之下端之 高度D3,以較第1端子101b之厚度D1低20μm左右為佳。藉由低20μm左右,可確實地使第1端子101b露出。其結果,可確實地導通第1端子101b與導體層105。又,自密封構件104之底面104c至刀片B之下端之高度D3,以較第2端子101c之厚度D2厚(高)35μm左右為佳。其係為使導體層105與第2端子101c不導通。 In addition, as explained, the bottom surface 104c of the self-sealing member 104 to the lower end of the blade B The height D3 is preferably about 20 μm lower than the thickness D1 of the first terminal 101b. The first terminal 101b can be surely exposed by being lowered by about 20 μm. As a result, the first terminal 101b and the conductor layer 105 can be surely turned on. Further, the height D3 of the bottom surface 104c of the self-sealing member 104 to the lower end of the blade B is preferably about 35 μm thicker than the thickness D2 of the second terminal 101c. This is to prevent the conductor layer 105 from being electrically connected to the second terminal 101c.
接著,於密封構件104之表面上藉由印刷法塗佈導電性糊料。此時,於槽G內亦填充導體糊料。接著,將導體糊料進行燒結或硬化而得到導體層105(參照圖4(c))。導體糊料係例如使銀(Ag)或銅(Cu)等之導電性較高之粉末分散於熱硬化樹脂中者。另,導體層105亦可在於包含槽G內之密封構件104之表面上塗佈無電解電鍍催化劑(例如,鈀(Pa))後,進行無電解鍍銅而形成。 Next, a conductive paste is applied on the surface of the sealing member 104 by a printing method. At this time, the conductor paste is also filled in the groove G. Next, the conductor paste is sintered or cured to obtain a conductor layer 105 (see FIG. 4(c)). The conductor paste is, for example, a powder having a high conductivity such as silver (Ag) or copper (Cu) dispersed in a thermosetting resin. Alternatively, the conductor layer 105 may be formed by applying an electroless plating catalyst (for example, palladium (Pa)) to the surface of the sealing member 104 including the groove G, and then performing electroless copper plating.
接著,使用刀片B沿著圖2所示之第2切割線(虛線)進行全切割(參照圖5(a))。藉由該全切割將引線框架101切斷,可得到露出導體層105之剖面之經單片化之半導體裝置100(參照圖5(b))。 Next, the blade B is completely cut along the second cutting line (dashed line) shown in Fig. 2 (see Fig. 5(a)). By cutting the lead frame 101 by the full dicing, a singulated semiconductor device 100 having a cross section of the conductor layer 105 is obtained (see FIG. 5(b)).
如上述般,在半導體裝置100中,係藉由將引線框架101之接地(GND)端子101b之厚度D1設定成較其他端子即第2端子101c之厚度D2更厚,且將密封構件104半切割,以形成僅露出第1端子101b之槽G。其後,填充槽G而形成導體層105。 As described above, in the semiconductor device 100, the thickness D1 of the ground (GND) terminal 101b of the lead frame 101 is set to be thicker than the thickness D2 of the other terminal, that is, the second terminal 101c, and the sealing member 104 is half-cut. To form the groove G in which only the first terminal 101b is exposed. Thereafter, the trench G is filled to form the conductor layer 105.
因此,可於密封構件104上容易地形成具有屏蔽效果之導體層105。又,由於係以導體層105覆蓋至密封構件104之端面104a為止,故藉由導體層105產生之屏蔽效果提高。進而,無須如先前之半導體裝置般,為使導體層105接地而另外設置端子等,從而可抑制步驟數之增加。其結果,可抑制具備導體層105之半導體裝置100之製造成本。 Therefore, the conductor layer 105 having a shielding effect can be easily formed on the sealing member 104. Further, since the conductor layer 105 is covered to the end surface 104a of the sealing member 104, the shielding effect by the conductor layer 105 is improved. Further, it is not necessary to provide a terminal or the like in order to ground the conductor layer 105 as in the case of the conventional semiconductor device, and it is possible to suppress an increase in the number of steps. As a result, the manufacturing cost of the semiconductor device 100 including the conductor layer 105 can be suppressed.
(第2實施形態) (Second embodiment)
圖6係第2實施形態之半導體裝置200之構成圖。圖6(a)係半導體 裝置200之俯視圖,圖6(b)係圖6(a)之線段Z-Z之半導體裝置200之剖面圖。半導體裝置200係引線端子不自密封構件凸出之QFP(quad flat non-lead package:無引線四邊平面封裝)型之半導體裝置。以下,參照圖6針對半導體裝置200之構成進行說明。另,對與參照圖1~圖5所說明之半導體裝置100相同之構成,標註相同符號而省略重複之說明。 Fig. 6 is a view showing the configuration of a semiconductor device 200 according to the second embodiment. Figure 6 (a) is a semiconductor A plan view of the apparatus 200, and Fig. 6(b) is a cross-sectional view of the semiconductor device 200 of the line segment Z-Z of Fig. 6(a). The semiconductor device 200 is a QFP (quad flat non-lead package) type semiconductor device in which the lead terminals are not protruded from the sealing member. Hereinafter, the configuration of the semiconductor device 200 will be described with reference to FIG. 6 . The same components as those of the semiconductor device 100 described with reference to FIGS. 1 to 5 are denoted by the same reference numerals, and the description thereof will not be repeated.
半導體裝置200包含引線框架201、半導體晶片102、焊接線103、密封構件204、及導體層105。引線框架201包含用於安裝半導體晶片102之安裝部201a、接地(GND)用端子(第1端子)201b、及訊號用端子等其他端子(第2端子)201c。 The semiconductor device 200 includes a lead frame 201, a semiconductor wafer 102, a bonding wire 103, a sealing member 204, and a conductor layer 105. The lead frame 201 includes a mounting portion 201a for mounting the semiconductor wafer 102, a ground (GND) terminal (first terminal) 201b, and another terminal (second terminal) 201c such as a signal terminal.
第1、第2端子201b、201c係離間於安裝部201a之周圍而配置。在第2實施形態中,未將第2端子201c之前端部薄化,第1端子201b之厚度D4與第2端子201c之厚度D5大致相同。 The first and second terminals 201b and 201c are disposed apart from each other around the mounting portion 201a. In the second embodiment, the front end portion of the second terminal 201c is not thinned, and the thickness D4 of the first terminal 201b is substantially the same as the thickness D5 of the second terminal 201c.
因此,在此半導體裝置200中,於密封構件204形成有露出第1端子201b之上表面T1之孔H,藉由以導體層205填充該孔H內,使接地(GND)端子即第1端子201b與導體層105導通。另,孔H可依每第1端子201b而形成。又,在得到充分導通之情形時,亦可使孔H之數量少於第1端子201b之數量。 Therefore, in the semiconductor device 200, the hole H in which the upper surface T1 of the first terminal 201b is exposed is formed in the sealing member 204, and the inside of the hole H is filled with the conductor layer 205, so that the ground (GND) terminal is the first terminal. 201b is electrically connected to the conductor layer 105. Further, the hole H can be formed every first terminal 201b. Further, when sufficient conduction is obtained, the number of holes H may be made smaller than the number of the first terminals 201b.
密封構件204將環氧樹脂作為主成分,其係添加有氧化矽填充材等之熱硬化性成形材料,且密封半導體晶片102及引線框架201。又,於密封構件204之端面204a上形成階差204b。在此實施形態中,為使導體層105與第2端子201c不導通,而將階差204b設定於高於第2端子201c之上表面T2之位置上。 The sealing member 204 has an epoxy resin as a main component, and a thermosetting molding material such as a cerium oxide filler is added thereto, and the semiconductor wafer 102 and the lead frame 201 are sealed. Further, a step 204b is formed on the end surface 204a of the sealing member 204. In this embodiment, in order to prevent the conductor layer 105 from being electrically connected to the second terminal 201c, the step 204b is set to be higher than the upper surface T2 of the second terminal 201c.
圖7、圖8係半導體裝置200之製造流程圖。以下參照圖2、圖7、圖8針對圖6所示之半導體裝置200之製造方法進行說明。另,根據將半導體晶片102及引線框架201以密封構件204密封之狀態說明半導體 裝置200之製造方法(參照圖7(a))。 7 and 8 are manufacturing flowcharts of the semiconductor device 200. Hereinafter, a method of manufacturing the semiconductor device 200 shown in FIG. 6 will be described with reference to FIGS. 2, 7, and 8. In addition, the semiconductor is described in terms of sealing the semiconductor wafer 102 and the lead frame 201 with the sealing member 204. A method of manufacturing the device 200 (see Fig. 7(a)).
首先,使用刀片B沿著圖2所示之第1切割線(實線)進行半切割(參照圖7(b))。藉由該半切割於密封構件204之兩端上形成槽G(參照圖7(c))。又,使用雷射於密封構件204形成露出第1端子201b之上表面T1之孔H(參照圖7(c))。 First, the blade B is half-cut along the first cutting line (solid line) shown in Fig. 2 (see Fig. 7(b)). A groove G is formed on both ends of the sealing member 204 by the half cutting (refer to FIG. 7(c)). Further, a hole H that exposes the upper surface T1 of the first terminal 201b is formed by using a laser to the sealing member 204 (see FIG. 7(c)).
另,刀片B之下端之位置,係以自第2端子201c之上表面T2高35μm左右為佳。其係為使導體層105與第2端子201c不導通。 Further, the position of the lower end of the blade B is preferably about 35 μm higher than the upper surface T2 of the second terminal 201c. This is to prevent the conductor layer 105 from being electrically connected to the second terminal 201c.
接著,於密封構件204之表面上藉由印刷法塗佈導電性糊料。此時,於形成於密封構件204之槽G內及孔H內亦填充導體糊料。接著將導體糊料進行燒結或硬化而得到導體層105(參照圖8(a))。另,導體層105亦可在於包含槽G及孔H內之密封構件204之表面上塗佈無電解電鍍催化劑(例如,鈀(Pa))後,進行無電解鍍銅而形成。 Next, a conductive paste is applied onto the surface of the sealing member 204 by a printing method. At this time, the conductor paste is also filled in the groove G formed in the sealing member 204 and in the hole H. Next, the conductor paste is sintered or hardened to obtain a conductor layer 105 (see FIG. 8(a)). Further, the conductor layer 105 may be formed by applying an electroless plating catalyst (for example, palladium (Pa)) to the surface of the sealing member 204 including the groove G and the hole H, and then performing electroless copper plating.
接著,使用刀片B沿著圖2所示之第2切割線(虛線)進行全切割(參照圖8(b))。藉由該全切割將引線框架201切斷,可得到露出導體層105之剖面之經單片化之半導體裝置200(參照圖8(c))。 Next, the blade B is completely cut along the second cutting line (dashed line) shown in Fig. 2 (see Fig. 8(b)). By cutting the lead frame 201 by the full dicing, a singulated semiconductor device 200 in which the cross section of the conductor layer 105 is exposed can be obtained (see FIG. 8(c)).
如上述般,在半導體裝置200中,於密封構件204上藉由雷射形成使接地(GND)端子即第1端子201b之上表面T1露出之孔H後,填充該孔H內而形成導體層105。 As described above, in the semiconductor device 200, a hole H which exposes the ground (GND) terminal, that is, the upper surface T1 of the first terminal 201b, is formed on the sealing member 204, and then the hole H is filled in the hole H to form a conductor layer. 105.
因此,即使在接地(GND)端子即第1端子201b之厚度D4與其他之端子即第2端子201c之厚度D5大致相同之情形時,仍可於密封構件204上容易地形成具有屏蔽效果之導體層105。其他之效果與第1實施形態之半導體裝置100之效果相同。 Therefore, even when the ground (GND) terminal, that is, the thickness D4 of the first terminal 201b is substantially the same as the thickness D5 of the other terminal, that is, the second terminal 201c, the conductor having the shielding effect can be easily formed on the sealing member 204. Layer 105. Other effects are the same as those of the semiconductor device 100 of the first embodiment.
(實施形態之變化例) (variation of embodiment)
在上述第1實施形態之半導體裝置100及第2實施形態之半導體裝置200之製造步驟中,雖然第1切割線(半切割)與第2切割線(全切割)為不同之位置,但亦可將第1、第2切割線設定為相同位置。此情形時, 由於於密封構件104、204之側面上亦形成導體層105,故以預先將第1次(半切割時)使用之刀片之厚度設定為較第2次(全切割時)使用之刀片厚度更厚為佳。又,雖已針對引線端子不自密封構件突出之QFP(quad flat non-lead package:無引線四邊平面封裝)型之半導體裝置進行說明,但亦可應用於其他之半導體裝置,例如TSOP型之半導體裝置。 In the manufacturing steps of the semiconductor device 100 of the first embodiment and the semiconductor device 200 of the second embodiment, the first dicing line (half-cut) and the second dicing line (full-cut) are different positions. The first and second cutting lines are set to the same position. In this case, Since the conductor layer 105 is also formed on the side faces of the sealing members 104 and 204, the thickness of the blade used in the first (half-cut) is set to be thicker than the thickness of the blade used in the second (full-cut). It is better. Further, although a QFP (quad flat non-lead package) type semiconductor device in which a lead terminal does not protrude from a sealing member has been described, it can be applied to other semiconductor devices such as a TSOP type semiconductor. Device.
再者,已說明在第2實施形態之半導體裝置200中,接地(GND)端子(第1端子201b)之厚度與此外之端子(第2端子201c)之厚度大致相同之情形。但,在第1實施形態之半導體裝置100中,為將第1端子101b與導體層105更確實地導通,亦可使用雷射於密封構件104上形成使第1端子101b之上表面T1露出之孔H。 In the semiconductor device 200 of the second embodiment, the thickness of the ground (GND) terminal (first terminal 201b) is substantially the same as the thickness of the other terminal (second terminal 201c). However, in the semiconductor device 100 of the first embodiment, in order to electrically connect the first terminal 101b and the conductor layer 105 more reliably, the upper surface T1 of the first terminal 101b may be exposed by using a laser on the sealing member 104. Hole H.
(其他實施形態) (Other embodiments)
如上述般,雖已說明本發明之多個實施形態,但上述實施形態係作為例子而提示者,並非意圖限定發明之範圍者。上述實施形態可以其他各種形態予以實施,在不變更發明之主旨之範圍內,可進行各種省略、替換、變更。此等實施形態或變化與發明之範圍或主旨所包含者相同,皆係含在申請專利範圍所記述之發明及其均等之範圍內者。 As described above, the embodiments of the present invention have been described, but the above-described embodiments are presented as examples and are not intended to limit the scope of the invention. The above-described embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The scope of the invention and the scope of the invention are intended to be included within the scope of the invention and the scope of the invention.
100‧‧‧半導體裝置 100‧‧‧Semiconductor device
101‧‧‧引線框架 101‧‧‧ lead frame
101a‧‧‧安裝部 101a‧‧‧Installation Department
101b‧‧‧第1端子 101b‧‧‧1st terminal
101c‧‧‧第2端子 101c‧‧‧2nd terminal
102‧‧‧半導體晶片 102‧‧‧Semiconductor wafer
103‧‧‧焊接線 103‧‧‧welding line
104‧‧‧密封構件 104‧‧‧ Sealing member
104a‧‧‧端面 104a‧‧‧ end face
104b‧‧‧階差 104b‧‧ ‧ step
104c‧‧‧底面 104c‧‧‧ bottom
105‧‧‧導體層 105‧‧‧Conductor layer
D1‧‧‧第1端子之厚度 D1‧‧‧ thickness of the first terminal
D2‧‧‧第2端子之前端部之厚度 D2‧‧‧ Thickness of the front end of the 2nd terminal
D3‧‧‧自密封構件之底面至階差之高度(厚度) D3‧‧‧ Height from the bottom of the self-sealing member to the step (thickness)
R1‧‧‧第1端子之底背面 The bottom of the R1‧‧1 first terminal
R2‧‧‧第2端子之底背面 R2‧‧‧ bottom of the second terminal
T1‧‧‧第1端子之上表面 Top surface of T1‧‧‧1st terminal
T2‧‧‧第2端子之較低部位之上表面 T2‧‧‧ Upper surface of the lower part of the second terminal
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TW201438119A (en) | 2014-10-01 |
JP2014183142A (en) | 2014-09-29 |
CN104064553A (en) | 2014-09-24 |
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