CN207993847U - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
- Publication number
- CN207993847U CN207993847U CN201820433868.4U CN201820433868U CN207993847U CN 207993847 U CN207993847 U CN 207993847U CN 201820433868 U CN201820433868 U CN 201820433868U CN 207993847 U CN207993847 U CN 207993847U
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- CN
- China
- Prior art keywords
- line
- chip region
- pin
- glue
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A kind of semiconductor package, including forming glue-line, lead frame unit, semiconductor core blade unit, and encapsulation glue-line.The forming glue-line is made of insulating polymer material, the external zones with chip region described in chip region and collar.The lead frame unit has a plurality of independence electrical each other and is embedded at the pin of the chip region.The semiconductor core blade unit has the semiconductor chip for the top surface for being set to the chip region and a plurality of conducting wire for enabling the semiconductor chip be electrically connected with the pin.The encapsulation glue-line covers the side of the top surface of the chip region of the forming glue-line, the semiconductor core blade unit, the wiring face of the pin exposed and the pin exposed.
Description
Technical field
The utility model relates to a kind of package assembling using square flat outer-pin-free leaded package, especially
Refer to a kind of semiconductor package using square flat outer-pin-free leaded package and centreless tablet seat.
Background technology
The general semiconductor packages for utilizing square flat outer-pin-free (QFN, quad flat no-lead) leaded package
Component, because it is contemplated that after encapsulation therefore the semiconductor core can be arranged in the chip carrier equipped with metal in the heat dissipation of semiconductor chip
Piece, to assist the heat dissipation of the semiconductor chip.However, to minimize and without the package assembling of too high cooling requirements for,
The setting of the chip carrier has no too many benefit to the entirety of the package assembling.In addition, in order to which the chip carrier is arranged, also need
The space that partly pin can be set is sacrificed to be connect as the chip carrier with the frame of the lead frame, decreases pin
Can installation space.
Invention content
The purpose of this utility model is to provide a kind of semiconductor packages groups of the QFN leaded packages using centreless tablet seat
Part.
The utility model semiconductor package includes forming glue-line, lead frame unit, semiconductor core blade unit, and encapsulation
Glue-line.
The forming glue-line is made of insulating polymer material, the external zones with chip region described in chip region and collar,
The bottom surface of the external zones and the bottom surface of the chip region are coplanar, and collectively form the bottom surface of the forming glue-line, and described
External zones is less than the chip region from the upward vertical height in the bottom surface from the upward vertical height in the bottom surface.
There is the lead frame unit a plurality of independent pin electrical each other, each pin to be embedded at the chip region,
And with being exposed by the bottom surface of the chip region and the bottom surface coplanar with the bottom surface of the chip region, and from the chip
The top surface in area is exposed and the wiring face coplanar with the top surface of the chip region.
The semiconductor core blade unit has the semiconductor chip of the top surface for being set to the chip region and a plurality of for enabling
The conducting wire that the semiconductor chip is electrically connected with the pin.
It is described encapsulation glue-line cover the top surface of the chip region, the semiconductor core blade unit, the pin exposed institute
The top surface in the wiring face of stating, the side of the pin exposed and at least part of external zones.
Preferably, the semiconductor package, wherein the encapsulation glue-line not exclusively covers the top of the external zones
Face, and the lateral circle surface of the encapsulation glue-line and the lateral circle surface of the forming glue-line be not coplanar.
Preferably, the semiconductor package, wherein the top surface of the external zones is completely covered in the encapsulation glue-line,
And the lateral circle surface of the encapsulation glue-line and the lateral circle surface of the forming glue-line are coplanar.
Preferably, the semiconductor package, wherein the chip region has central part described in central part and collar
Periphery, the pin is set to the periphery, and the semiconductor chip is set to the central part, and is led by described
Line is electrically connected with the pin.
The beneficial effect of the utility model is：Using allow the semiconductor package the lead frame unit not
With the chip carrier, therefore, the installation space of pin will not be influenced because of chip carrier, can be more convenient for small-sized encapsulated component
It uses.
Description of the drawings
Fig. 1 is a schematic cross-sectional view, illustrates the embodiment of semiconductor package described in the utility model；
Fig. 2 is a schematic cross-sectional view, illustrates another state sample implementation of the encapsulation glue-line of embodiment；
Fig. 3 is a schematic top plan view, aids in illustrating the embodiment in manufacturing process, the aspect before not yet cutting；
Fig. 4 is a schematic cross-sectional view, illustrates the sectional structure of the IV-IV face lines along Fig. 3；And
Fig. 5 is a schematic cross-sectional view, aids in illustrating the semiconductor package of Fig. 2, in manufacturing process, cuing open before cutting
Depending on structure.
Specific implementation mode
The utility model is described in detail with reference to the accompanying drawings and embodiments.
Cooperation refering to fig. 1, Fig. 3 and Fig. 4, Fig. 1 be the utility model semiconductor package an embodiment sectional view.
The semiconductor package includes 3, a forming glue-line 2, lead frame unit semiconductor core blade units 4,
And one encapsulation glue-line 5.
The forming glue-line 2 is made of insulative potting materials such as such as epoxy resin, silane oxygen resins.With a chip region
22 and an external zones 25.
Specifically, the external zones 25 can chip region 22 described in collar, the chip region 22 have a central part 23 and
The periphery 24 of central part 23 described in one collar.The chip region 22 has a bottom surface 221 and a top surface 222 reversely with each other,
The bottom surface 221 of the chip region 22 and the bottom surface 251 of the external zones 25 are coplanar, and collectively form the forming glue-line
2 bottom surface.Wherein, the external zones 25 has first height from the bottom surface 251 of the external zones 25 vertically upward
H1, the chip region 22 have a second height H2 from the bottom surface 221 of the chip region 22 vertically upward, and described the
One height H1 is less than the second height H2.
The lead frame unit 3 is made of conductive materials such as copper, copper series alloy or iron-nickel alloys, is respectively arranged at the core
Section 22, and the lead frame unit 3 has the pin 31 of a plurality of periphery 24 for being embedded at the chip region 22.The pin
31 central part 23 that is positioned against each other each independently from the periphery 24 adjacent to the external zones 25 extends, and every
One pin 31 has an exposing of bottom surface 221 from the chip region 22 and the bottom surface 311 coplanar with the bottom surface 221, and
One expose from the top surface 222 of the chip region 22 and with 222 coplanar wiring face 312 of the top surface.
The semiconductor core blade unit 4 has the semiconductor chip 41 of a top surface for being set to the central part 23, and more
Item is to the conducting wire 42 that enables the semiconductor chip 41 be electrically connected with the pin 31.Wherein, the semiconductor chip 41 can be
General IC chip, luminescence chip etc., there is no particular restriction.
Encapsulation glue-line 5 lid covers the semiconductor core blade unit 4, the top surface 222 of the chip region 22, the pin 31
The side 313 and the wiring face 312 of the exposed chip region 22, and the top surface 253 of the external zones 25 is completely covered, and institute
Lateral circle surface 51 and the lateral circle surface 252 of the external zones 25 for stating encapsulation glue-line 5 are coplanar.
The material of the encapsulation glue-line 5 is mainly by the insulative potting materials institute such as such as epoxy resin, silane oxygen resin structure
At, and can be identical or different with the material of the forming glue-line 2.In addition, it is noted that the material of the encapsulation glue-line 5
Also the characteristic and demand of the visual semiconductor chip 41, and include further other functional added materials, to adjust
State the bulk property of semiconductor package.For example, when the semiconductor chip 41 is luminescence component, the encapsulation glue-line 5
Scattering particles or fluorescent material etc. can be added again, with change the luminescence component finally go out light characteristic.
It is noted that be that the top surface 253 of the external zones 25 is completely covered with the encapsulation glue-line 5 in Fig. 1, and it is described
For the lateral circle surface 51 of encapsulation glue-line 5 and the lateral circle surface 252 of the external zones 25 are coplanar.When right actual implementation, the encapsulation
Glue-line 5 can also as shown in Fig. 2, external zones 25 described in endless all standing top surface 253, at this point, it is described encapsulation glue-line 5 side week
Face 51 and the lateral circle surface 252 of the external zones 25 be not coplanar.
Specifically, cooperation refering to fig. 1, Fig. 3, the making of the semiconductor package shown in FIG. 1, is first to provide one
The substrate that the materials such as conductive material, such as copper, copper series alloy or iron-nickel alloy are constituted.A plurality of longitudinal direction is defined in the substrate
And division island that is transversely arranged and intersecting each other, and the division island that transverse direction and longitudinal direction that is adjacent two-by-two and intersecting each other arranges is common
Define multiple spaces that subsequently can be pre-formed after etched removal.Then, carry out first time etching, formed a lead frame half at
Product.
There is the lead frame semi-finished product a plurality of longitudinal and transverse direction to arrange and the connecting bracket that is spaced and a plurality of described
Pin 31.Wherein, the connecting bracket is located at position and thickness defined in the division island and is less than the substrate.It is described to draw
Foot 31 extends and corresponded to from the connecting bracket respectively is located at the space.Wherein, each space is corresponding as shown in Figure 1
The chip region 22, and the connecting bracket in each space of collar is the position of the corresponding external zones 25.
Then, the aforementioned lead frame semi-finished product clamper is set to a mold, pours into a forming glue material with the mode of being molded into, and enable
After the forming glue material solidification, you can form the forming glue-line 2.Then, it carries out second to etch, the forming glue will be formed
The connecting bracket etching of the lead frame semi-finished product of layer 2, which removes, extremely enables the corresponding forming glue-line 2 in lower section exposed, and
It allows the forming glue-line 2 corresponding to the connecting bracket position to form most Cutting Roads 21, and makes the pin 31 respectively electric
Property independent be not connected to each other.At this point, the position set by the pin 31 is the periphery 24 of each chip region 22, and by
31 collar of the pin are then the central part 23 of the chip region 22, and the Cutting Road 21 has bottom surface reversely with each other
211 and top surface 212.
Then, carry out chip package, by the semiconductor chip 41 be respectively arranged at each chip region 22 it is described in
Each semiconductor chip 41 is electrically connected with the corresponding pin 31 using conducting wire 42 by center portion 23 followed by routing processing procedure
It connects, finally recycling is molded into mode and pours into a packaging adhesive material, and the semiconductor core blade unit is completely covered in the packaging adhesive material
4, the exposed top surface 222 in the chip region 22, the pin 31 the wiring face 312, and the Cutting Road 21 is completely covered
Top surface 212, and the packaging adhesive material is formed by curing the encapsulation glue-line 5, you can obtain the lead frame as shown in Figure 3
Encapsulating structure.Fig. 3 is the schematic top plan view of the lead frame encapsulation structure, and Fig. 4 is then cuing open for the IV-IV face lines in Fig. 3
View.
Finally, then by the lead frame encapsulation structure via the Cutting Road 21 cutting (along cutting line X shown in Fig. 4 into
Row cutting), you can obtain single semiconductor package as shown in Figure 2.Wherein, the Cutting Road 21 is rear after cutting remains
Part i.e. be correspondingly formed the external zones 25.Since the encapsulation glue-line 5 of the lead frame encapsulation structure is to be completely covered
Therefore the top surface 212 of the Cutting Road 21 after cutting, is formed, chip region 22 described in collar after being cut by the Cutting Road 21
The lateral circle surface 51 of the external zones 25 can be coplanar with the lateral circle surface 252 of the forming glue-line 2.
Refering to Fig. 5, lead frame encapsulation structure shown in fig. 5 is that the aforementioned lead frame carries out semiconductor chip envelope for cooperation
After dress, routing when forming the process of the encapsulation glue-line 5, control enables the packaging adhesive material that the semiconductor chip is completely covered
The exposed top surface 222 in unit 4, the chip region 22, the pin 31 the wiring face 312, but enable the packaging adhesive material not
The top surface 212 of the Cutting Road 21 is completely covered, therefore, 5 meeting of encapsulation glue-line of formation is as shown in figure 5, in the cutting
The position in road 21 can have the region that do not fill out and cover the forming glue material.Therefore, when by the semiconductor packages knot as shown in Figure 5
Structure cuts (being cut along cutting line X shown in fig. 5) via the Cutting Road 21, you can obtains as shown in Figure 2 single
Semiconductor package.
Since the top surface 212 of the Cutting Road 21 is not completely covered for the encapsulation glue-line 5, after cutting, cut by described
Remained after cutting 21 cuttings and collar described in the external zones 25 of chip region 22 can protrude the encapsulation glue-line 5, and so that cutting
The lateral circle surface 51 of the lateral circle surface 252 of the forming glue-line 2 after cutting and the encapsulation glue-line 5 will not be coplanar.
Allow the lead frame unit 3 at the knot of centreless tablet seat in conclusion the utility model semiconductor package utilizes
Structure designs, and therefore, the package assembling in addition to that can be more suitable for miniaturization can also allow pin 31 to have more installation spaces, so
Really it can reach the purpose of this utility model.
Claims (4)
1. a kind of semiconductor package, it is characterised in that：Including：
Glue-line is shaped, is made of insulating polymer material, the external zones with chip region described in chip region and collar is described outer
The bottom surface for enclosing the bottom surface and the chip region in area is coplanar, and collectively forms the bottom surface of the forming glue-line, and the external zones
The vertical height upward from the bottom surface is less than the chip region from the upward vertical height in the bottom surface；
Lead frame unit, have it is a plurality of electrically independent pin, each pin are embedded at the chip region each other, and with by
The bottom surface of the chip region is exposed, and the bottom surface coplanar with the bottom surface of the chip region, and the top from the chip region
It shows out, and the wiring face coplanar with the top surface of the chip region, the pin also has the side of the exposed chip region
Face；
Semiconductor core blade unit has the semiconductor chip of the top surface for being set to the chip region and a plurality of for enabling described half
The conducting wire that conductor chip is electrically connected with the pin；And
Glue-line is encapsulated, the wiring of the top surface, the semiconductor core blade unit, the pin exposed of the chip region is covered
The top surface in face, the side of the pin exposed and at least part of external zones.
2. semiconductor package according to claim 1, it is characterised in that：Described in the encapsulation glue-line not exclusively covering
The top surface of external zones, and the lateral circle surface of the encapsulation glue-line and the lateral circle surface of the forming glue-line be not coplanar.
3. semiconductor package according to claim 1, it is characterised in that：The encapsulation glue-line is completely covered described outer
The top surface in area is enclosed, and the lateral circle surface of the encapsulation glue-line and the lateral circle surface of the forming glue-line are coplanar.
4. semiconductor package according to claim 1, it is characterised in that：The chip region has central part and ring
The periphery of the central part is enclosed, the pin is set to the periphery, and the semiconductor chip is set to the central part,
And it is electrically connected with the pin by the conducting wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820433868.4U CN207993847U (en) | 2018-03-29 | 2018-03-29 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820433868.4U CN207993847U (en) | 2018-03-29 | 2018-03-29 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207993847U true CN207993847U (en) | 2018-10-19 |
Family
ID=63830149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820433868.4U Active CN207993847U (en) | 2018-03-29 | 2018-03-29 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207993847U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115064511A (en) * | 2022-08-17 | 2022-09-16 | 广东长华科技有限公司 | Semiconductor packaging part with heat radiation structure |
-
2018
- 2018-03-29 CN CN201820433868.4U patent/CN207993847U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115064511A (en) * | 2022-08-17 | 2022-09-16 | 广东长华科技有限公司 | Semiconductor packaging part with heat radiation structure |
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| GR01 | Patent grant |