JP3381602B2 - Electronic component manufacturing method - Google Patents
Electronic component manufacturing methodInfo
- Publication number
- JP3381602B2 JP3381602B2 JP01372698A JP1372698A JP3381602B2 JP 3381602 B2 JP3381602 B2 JP 3381602B2 JP 01372698 A JP01372698 A JP 01372698A JP 1372698 A JP1372698 A JP 1372698A JP 3381602 B2 JP3381602 B2 JP 3381602B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- gold
- electrode
- bumps
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
Landscapes
- Wire Bonding (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は、バンプ付電子部品
を基板に実装してなる電子部品の製造方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electronic component having a bumped electronic component mounted on a substrate.
【0002】[0002]
【従来の技術】電子部品の組立構造として、BGA(B
all Grid Array)など基板にフリップチ
ップなどの電子部品を実装するとともに基板に形成され
た他の電極に半田バンプを形成したものが知られてい
る。以下従来の電子部品製造方法を図面を参照して説明
する。図12は従来の電子部品の断面図である。図12
において基板1の上面および下面にはそれぞれ回路電極
としての銅電極2A,2Bが形成されている。銅電極2
A,2B上にはバリア層としてのニッケル膜3A,3B
を介して金膜4A,4Bが形成されている。上面側の銅
電極2Aと下面側の銅電極2Bは内部配線5によって接
続されている。銅電極2Aの金膜4Aにはバンプ付電子
部品6の金バンプ7を導通させてバンプ付き電子部品6
と基板1の隙間を絶縁樹脂8によって封止し、他方の銅
電極2Bの金膜4B上には半田バンプ9を形成して電子
部品を組み立てている。2. Description of the Related Art BGA (B
It is known that an electronic component such as a flip chip is mounted on a substrate such as an all grid array and solder bumps are formed on other electrodes formed on the substrate. A conventional method of manufacturing an electronic component will be described below with reference to the drawings. FIG. 12 is a sectional view of a conventional electronic component. 12
In the above, copper electrodes 2A and 2B as circuit electrodes are formed on the upper surface and the lower surface of the substrate 1, respectively. Copper electrode 2
Nickel films 3A and 3B as barrier layers on A and 2B
The gold films 4A and 4B are formed through. The copper electrode 2A on the upper surface side and the copper electrode 2B on the lower surface side are connected by an internal wiring 5. The gold film 4A of the copper electrode 2A is electrically connected to the gold bumps 7 of the bumped electronic component 6 so that the bumped electronic component 6
The gap between the substrate 1 and the substrate 1 is sealed with the insulating resin 8, and the solder bumps 9 are formed on the gold film 4B of the other copper electrode 2B to assemble the electronic component.
【0003】ここで銅電極2A,2B上の金膜4A,4
Bについて説明する。金膜4A,4Bは一般にメッキ法
により形成され、バンプ付電子部品6の金バンプ7上と
の良好な導通を確保するために必要とされるものであ
る。ニッケル膜3A,3Bは銅電極2A,2Bの素材で
ある銅が金膜4A,4B中へ拡散するのを防止するバリ
ア層として機能する。Here, the gold films 4A, 4 on the copper electrodes 2A, 2B.
B will be described. The gold films 4A and 4B are generally formed by a plating method and are necessary for ensuring good electrical continuity with the gold bumps 7 of the electronic component 6 with bumps. The nickel films 3A and 3B function as a barrier layer that prevents copper, which is a material of the copper electrodes 2A and 2B, from diffusing into the gold films 4A and 4B.
【0004】[0004]
【発明が解決しようとする課題】金膜4A,4Bの表面
にはニッケル化合物などの金属化合物層が生成され易
い。これらの金属化合物は金バンプ7と金膜4A、4B
の導通や接合を阻害する導通阻害物であるため、極力こ
れらの層の生成を抑制する必要があり、この目的のため
には金膜4A,4Bの厚さをある程度以上に厚くする必
要があった。しかしながら、金膜4A,4Bを厚くする
と、半田バンプ9のボンディング性を低下させるという
悪影響がある。半田バンプ形成時に金膜4B中の金が溶
融半田中に溶け込み、半田のズズと化合して脆い化合物
を形成するからである。このように、金バンプ7との良
好な導通を確保するためには金膜4Aは厚い方(0.3
μm以上)がよく、他方半田バンプ9のボンディング性
を確保するためには金膜4Bは薄いことが望まれ、いわ
ば一方を満足すると他方が満足されない背反関係にある
という問題点があった。A metal compound layer such as a nickel compound is likely to be formed on the surfaces of the gold films 4A and 4B. These metal compounds are used for the gold bump 7 and the gold films 4A and 4B.
It is necessary to suppress the formation of these layers as much as possible because it is a conduction inhibitor that inhibits the conduction and bonding of the gold films. For this purpose, it is necessary to increase the thickness of the gold films 4A and 4B to a certain degree or more. It was However, thickening the gold films 4A and 4B has an adverse effect of deteriorating the bonding property of the solder bump 9. This is because the gold in the gold film 4B melts into the molten solder when the solder bumps are formed, and combines with the solder gap to form a brittle compound. As described above, in order to ensure good conduction with the gold bumps 7, the gold film 4A is thicker (0.3
It is desirable that the gold film 4B is thin in order to secure the bonding property of the solder bumps 9 on the other hand, and so to speak, if one of them is satisfied, there is a contradictory relationship that the other is not satisfied.
【0005】この問題を解決するために部分メッキ法を
適用して金膜4Aのメッキ工程と、金膜4Bのメッキ工
程を別々に行い、金膜4Aを厚く金膜4Bを必要最小限
度の厚さだけ形成することが考えられるが、部分メッキ
法は工程が多くなり大幅なコスト上昇を招いてしまうと
いう問題があった。In order to solve this problem, a partial plating method is applied to separately perform the gold film 4A plating step and the gold film 4B plating step, so that the gold film 4A is thick and the gold film 4B is at the minimum necessary thickness. However, the partial plating method has a problem that the number of steps is increased and the cost is significantly increased.
【0006】そこで本発明は、バンプ付電子部品の金バ
ンプとの良好な導通と、半田バンプのボンディング性を
ともに確保することができる電子部品の製造方法を提供
することを目的とする。[0006] Therefore, an object of the present invention is to provide a method of manufacturing an electronic component which can secure good electrical continuity with a gold bump of an electronic component with bumps and bondability of a solder bump.
【0007】[0007]
【課題を解決するための手段】請求項1記載の電子部品
製造方法は、基板にバンプ付電子部品のバンプと導通さ
せるための第1の電極と半田バンプを形成するための第
2の電極を形成する第1の工程と、これらの電極上に少
なくともニッケルを含むバリア層を形成する第2の工程
と、これらのバリア層の表面に金膜を形成する第3の工
程と、前記第1の電極上の金膜の表面に生成した導通阻
害物を除去する第4の工程と、バンプ付電子部品のバン
プを前記第1の電極に位置合せして導通させるとともに
このバンプ付電子部品を基板に固着させる第5の工程
と、前記第2の電極上に半田バンプを形成する第6の工
程とを含む。According to a first aspect of the present invention, there is provided a method of manufacturing an electronic component, wherein a substrate is provided with a first electrode for conducting the bump of the electronic component with bumps and a second electrode for forming a solder bump. A first step of forming, a second step of forming a barrier layer containing at least nickel on these electrodes, a third step of forming a gold film on the surface of these barrier layers, and the first step. A fourth step of removing a conduction blocker formed on the surface of the gold film on the electrode, and aligning the bump of the bumped electronic component with the first electrode to conduct electricity, and the bumped electronic component on the substrate. It includes a fifth step of fixing and a sixth step of forming solder bumps on the second electrodes.
【0008】請求項2記載の電子部品製造方法は、請求
項1記載の電子部品製造方法であって、前記第4の工程
において、プラズマ処理によるスパッタリングを利用し
て前記金膜の表面に生成した導通阻害物を除去するよう
にした。An electronic part manufacturing method according to a second aspect is the electronic part manufacturing method according to the first aspect, wherein in the fourth step, the gold film is formed on the surface of the gold film by utilizing sputtering by plasma treatment. The conduction inhibitor was removed.
【0009】請求項3記載の電子部品製造方法は、請求
項1記載の電子部品製造方法であって、前記第4の工程
に先立って、基板に加熱処理を施して前記第1の電極上
の金膜表面の導通阻害物の生成を促進した後にこの導通
阻害物を除去することにより、前記金膜中に含まれる金
属不純物をより多く除去するようにした。According to a third aspect of the present invention, there is provided an electronic component production method according to the first aspect, wherein the substrate is subjected to a heat treatment prior to the fourth step so that the electronic component is formed on the first electrode. By removing the conduction inhibitor after promoting the generation of the conduction inhibitor on the surface of the gold film, more metal impurities contained in the gold film were removed.
【0010】請求項4記載の電子部品製造方法は、請求
項1記載の電子部品製造方法であって、前記金膜の厚さ
の上限値は半田バンプに溶け込む金の重量%が0.1%
以下となる値であり、下限値は0.01μmであるよう
にした。The electronic component manufacturing method according to claim 4 is the electronic component manufacturing method according to claim 1, wherein the upper limit of the thickness of the gold film is 0.1% by weight of gold dissolved in the solder bump.
The value is as follows, and the lower limit value is set to 0.01 μm.
【0011】各請求項記載の発明によれば、金バンプが
導通する電極上の金膜表面に生成される導通阻害物を除
去することにより同一基板に形成された複数の電極の一
方に金バンプを良好に導通させるとともに、他方の電極
に半田バンプを接合性良く形成することができる。According to the invention described in each of the claims, the gold bump is formed on one of the plurality of electrodes formed on the same substrate by removing the conduction inhibitor generated on the surface of the gold film on the electrode through which the gold bump is conducted. Can be well conducted, and a solder bump can be formed on the other electrode with good bondability.
【0012】[0012]
【発明の実施の形態】(実施の形態1)図1は本発明の
実施の形態1の電子部品の側断面図、図2、図3、図
4、図5、図6、図7は同電子部品製造方法の工程説明
図である。まず図1を参照して電子部品の構造について
説明する。図1において、基板11の表面にはレジスト
11aが形成されており、基板11の上面にはバンプ付
電子部品16がボンディングされている。バンプ付電子
部品16は絶縁樹脂18によって基板11に固着されて
おり、バンプ付電子部品16は金バンプ17によって基
板11の上面に形成された電極12と導通している。電
極12は基板11の下面に形成された電極13と内部回
路14によって接続されており、電極13には半田バン
プ15が形成されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a side sectional view of an electronic component according to Embodiment 1 of the present invention, and FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. It is process explanatory drawing of an electronic component manufacturing method. First, the structure of the electronic component will be described with reference to FIG. In FIG. 1, a resist 11a is formed on the surface of the substrate 11, and a bumped electronic component 16 is bonded to the upper surface of the substrate 11. The electronic component 16 with bumps is fixed to the substrate 11 with an insulating resin 18, and the electronic component 16 with bumps is electrically connected to the electrodes 12 formed on the upper surface of the substrate 11 by the gold bumps 17. The electrode 12 is connected to an electrode 13 formed on the lower surface of the substrate 11 by an internal circuit 14, and a solder bump 15 is formed on the electrode 13.
【0013】次に図2〜図7を参照して電子部品製造方
法を説明する。図2〜図7は電子部品製造方法を工程順
に示すものである。図2において基板11の表面にはレ
ジスト11aが形成されている。基板11の上面の電極
12は、銅電極22A(第1の電極)上にバリア層とし
てニッケル膜23Aを形成し、更にニッケル膜23A上
に金膜24Aを極く薄くコーティングして形成されてい
る。金膜24Aは基板11にボンディングされるバンプ
付電子部品16の金バンプ17との導通を確保するため
に形成されるものである。また基板11の下面の電極1
3も同様に銅電極22B(第2の電極)上にニッケル膜
23Bを形成し、更に金膜24Bをコーティングして形
成されている。基板11の上面の電極12と下面の電極
13は同一メッキ工程にて形成される。従って、金膜2
4Bの厚さは金膜24A厚さと同一となる。Next, a method of manufacturing an electronic component will be described with reference to FIGS. 2 to 7 show an electronic component manufacturing method in the order of steps. In FIG. 2, a resist 11a is formed on the surface of the substrate 11. The electrode 12 on the upper surface of the substrate 11 is formed by forming a nickel film 23A as a barrier layer on the copper electrode 22A (first electrode) and further coating the nickel film 23A with a gold film 24A very thinly. . The gold film 24A is formed to ensure electrical continuity with the gold bumps 17 of the electronic component 16 with bumps bonded to the substrate 11. In addition, the electrode 1 on the lower surface of the substrate 11
Similarly, 3 is formed by forming a nickel film 23B on the copper electrode 22B (second electrode) and further coating a gold film 24B. The electrode 12 on the upper surface and the electrode 13 on the lower surface of the substrate 11 are formed by the same plating process. Therefore, the gold film 2
The thickness of 4B is the same as the thickness of the gold film 24A.
【0014】次に、これらの金膜24A,24Bの厚さ
の設定方法について説明する。図11は、最も一般的な
共晶半田を用いた場合の、半田バンプ15に溶け込む金
の割合(重量%)と半田バンプ15と電極13の接合強
度(半田バンプ形成後175℃、50時間放置後の接合
強度)との関係を示したグラフである。図11に示すよ
うに、電極13の金膜24B上に形成された半田バンプ
15に対して水平方向の荷重を加え、接合部が破断した
ときの荷重値を以て接合強度としたものである。Next, a method of setting the thickness of these gold films 24A and 24B will be described. FIG. 11 shows the proportion (% by weight) of gold that melts into the solder bumps 15 and the bonding strength between the solder bumps 15 and the electrodes 13 when the most common eutectic solder is used (the solder bumps are left at 175 ° C. for 50 hours It is a graph showing the relationship with the subsequent bonding strength). As shown in FIG. 11, a load in the horizontal direction is applied to the solder bumps 15 formed on the gold film 24B of the electrode 13, and the bonding strength is defined as the load value when the bonding portion is broken.
【0015】なお、実用上の判断基準として、接合強度
(F)は、半田バンプ形成直後の接合強度(F0)を1
00とし、60以上を実用上問題ない強度とした。実験
によれば金が0.10%を超えると半田バンプの接合強
度が60を下回ることがわかった。前述のように、半田
バンプ中に溶け込む金の割合が増加するに従って、半田
中のスズと金が化合して生じる金とスズの化合物の量が
増えるからである。As a practical criterion, the bonding strength (F) is 1 after the solder bump is formed.
The strength was set to 00, and 60 or more was determined to be a strength that causes no practical problem. According to the experiment, when the gold content exceeds 0.10%, the bonding strength of the solder bump is less than 60. This is because, as described above, as the proportion of gold that dissolves in the solder bumps increases, the amount of gold and tin compounds produced by the combination of tin and gold in the solder increases.
【0016】従って金膜24Bの厚さの上限値は半田バ
ンプに溶け込む金の重量%が0.10%を超えない値に
する必要がある。この要件を満たすための金膜24Bの
厚さの上限値は(数1)の式により求めることができ
る。Therefore, the upper limit of the thickness of the gold film 24B needs to be a value such that the weight% of gold dissolved in the solder bumps does not exceed 0.10%. The upper limit value of the thickness of the gold film 24B for satisfying this requirement can be obtained by the formula (Equation 1).
【0017】[0017]
【数1】 [Equation 1]
【0018】因みに、φ210μmの円形の電極13に
直径300μmの半田ボールを用いて半田バンプを形成
する場合、金膜24Bの厚さの上限値は0.20μmと
なる。なお金膜24Bの厚さの下限値は、ニッケル膜2
3Bの酸化を防止するために最低必要な0.01μmで
ある。金膜24Bの厚さはこのようにして定められた上
限値、下限値の間の範囲で設定される。従って金膜24
Aの厚さは金膜24Bと同一工程でめっきされる結果同
一の厚さとなる。なお、金膜24A、24Bのめっき方
法は、コスト面で有利な置換型無電解めっき法がよい。Incidentally, when a solder bump is formed on the circular electrode 13 having a diameter of 210 μm by using a solder ball having a diameter of 300 μm, the upper limit of the thickness of the gold film 24B is 0.20 μm. The lower limit of the thickness of the gold film 24B is the nickel film 2
It is 0.01 μm, which is the minimum required to prevent the oxidation of 3B. The thickness of the gold film 24B is set in the range between the upper limit value and the lower limit value thus determined. Therefore, the gold film 24
The thickness of A becomes the same as that of the gold film 24B as a result of plating in the same step. The gold electroplating method for the gold films 24A and 24B is preferably a substitution type electroless plating method which is advantageous in terms of cost.
【0019】このようにしてめっき法で形成された金膜
24A、金膜24Bの表面にはめっき工程中で混入した
ニッケルなどの不純物が空気に触れて表面で酸化される
ことにより生成する化合物層が生じている。このうち、
金膜24Aの表面に生じた化合物層は電極12と金バン
プ17との良好な導通を阻害する導通阻害物25であ
る。On the surfaces of the gold film 24A and the gold film 24B thus formed by the plating method, a compound layer formed by the impurities such as nickel mixed in during the plating process being exposed to air and being oxidized on the surfaces. Is occurring. this house,
The compound layer formed on the surface of the gold film 24A is a conduction inhibitor 25 that inhibits good conduction between the electrode 12 and the gold bump 17.
【0020】そこで、この導通阻害物25を除去するた
めに、基板11の表面のプラズマ処理が行われる。図3
に示すように、基板11を、電極12を上向きにして真
空チャンバ30内の電極31上に載置する。次いで真空
吸引手段32により真空チャンバ30内を真空吸引した
後、真空チャンバ30内にはプラズマガス供給部33に
よりアルゴンガスなどのプラズマ発生用ガスが供給され
る。この状態で高周波電源部34を駆動して電極31に
高周波電圧を印加することにより、真空チャンバ30内
にはプラズマが発生し、その結果発生するアルゴンイオ
ンや電子などのスパッタリング効果により電極12の金
膜24A表面の導通阻害物25が除去される。なお、プ
ラズマ処理に先立って基板11を加熱処理すれば、金膜
24A表面の導通阻害物25の生成を促進し、その結果
金膜24A中からより多くの金属不純物を除去して金膜
24Aの純度を高めることができる。Therefore, in order to remove the conduction block 25, plasma treatment of the surface of the substrate 11 is performed. Figure 3
The substrate 11 is placed on the electrode 31 in the vacuum chamber 30 with the electrode 12 facing upward, as shown in FIG. Then, after the vacuum suction means 32 suctions the inside of the vacuum chamber 30 by vacuum, a plasma generating gas such as argon gas is supplied into the vacuum chamber 30 by the plasma gas supply unit 33. By driving the high frequency power supply unit 34 in this state and applying a high frequency voltage to the electrode 31, plasma is generated in the vacuum chamber 30, and the resulting sputtering effect of argon ions and electrons causes the gold of the electrode 12 to grow. The conduction blocker 25 on the surface of the film 24A is removed. If the substrate 11 is heat-treated prior to the plasma treatment, generation of the conduction inhibitor 25 on the surface of the gold film 24A is promoted, and as a result, more metal impurities are removed from the gold film 24A to remove the gold film 24A. The purity can be increased.
【0021】次にこの基板11上にバンプ付電子部品1
6がボンディングされる。図4に示すように、バンプ付
電子部品16の金バンプ17の下端部には予め導電樹脂
40が塗布されている。このバンプ付電子部品16の金
バンプ17を基板11の電極12に位置合せし、次いで
基板11に対して下降させる。その後金バンプ17を電
極12に加圧した状態で加熱して導電樹脂40を硬化さ
せる。これにより金バンプ17は導電樹脂40を介して
電極12と導通する。このとき、電極12の金膜24A
上の導通阻害物は前工程で除去されているため良好な導
通(低電気抵抗)と十分な接着強度が確保される。Next, the electronic component 1 with bumps is provided on the substrate 11.
6 is bonded. As shown in FIG. 4, the conductive resin 40 is applied in advance to the lower end portion of the gold bump 17 of the bumped electronic component 16. The gold bumps 17 of the electronic component 16 with bumps are aligned with the electrodes 12 of the substrate 11 and then lowered with respect to the substrate 11. Then, the gold bumps 17 are heated while being pressed against the electrodes 12 to cure the conductive resin 40. As a result, the gold bump 17 is electrically connected to the electrode 12 via the conductive resin 40. At this time, the gold film 24A of the electrode 12
Since the above conduction inhibitor is removed in the previous step, good conduction (low electric resistance) and sufficient adhesive strength are secured.
【0022】次に図5に示すように、バンプ付電子部品
16と基板11との間の隙間には絶縁樹脂41が充填さ
れ、加熱処理によって絶縁樹脂41が硬化することによ
り、バンプ付電子部品16は基板11に固着される。こ
のとき、基板11のレジスト11aの表面はプラズマ処
理のスパッタリング効果により面粗度が大きくなってい
るため、絶縁樹脂41との密着性が向上し、良好な樹脂
封止を行うことができる。この後、図6に示すように基
板11の電極13上にはフラックス42が塗布され、次
いで半田ボール43が電極13上に搭載される。この
後、基板11を加熱することにより半田ボール43は溶
融し、その後固化することにより、図7に示すように電
極13上で半田バンプ15が形成される。Next, as shown in FIG. 5, the insulating resin 41 is filled in the gap between the electronic component with bumps 16 and the substrate 11, and the insulating resin 41 is cured by heat treatment, whereby the electronic component with bumps is cured. 16 is fixed to the substrate 11. At this time, since the surface roughness of the surface of the resist 11a of the substrate 11 is increased by the sputtering effect of the plasma treatment, the adhesion with the insulating resin 41 is improved, and good resin sealing can be performed. After this, as shown in FIG. 6, flux 42 is applied on the electrodes 13 of the substrate 11, and then solder balls 43 are mounted on the electrodes 13. Thereafter, the solder balls 43 are melted by heating the substrate 11 and then solidified to form the solder bumps 15 on the electrodes 13 as shown in FIG.
【0023】このとき、電極13の金膜24B上にも同
様にニッケル酸化物などの金属化合物が生成されている
が、これらはフラックス42によって還元されるので半
田バンプ15の接合性には影響を及ぼさない。また金膜
24Bの厚さは前述のように半田付け後に接合強度を阻
害しない範囲に設定されるため、半田バンプ15中に溶
融する金の量が過大になることはなく、したがってスズ
と金が化合することによって生ずる脆い化合物層の生成
を抑制して接合強度に優れた半田バンプを形成すること
ができる。At this time, a metal compound such as nickel oxide is also formed on the gold film 24B of the electrode 13, but since these are reduced by the flux 42, the bondability of the solder bump 15 is affected. Does not reach. Further, since the thickness of the gold film 24B is set in the range that does not hinder the bonding strength after soldering as described above, the amount of gold melted in the solder bumps 15 does not become excessive, so that tin and gold are It is possible to suppress the formation of a brittle compound layer caused by compounding and form a solder bump having excellent bonding strength.
【0024】(実施の形態2)図8、図9は本発明の実
施の形態2の電子部品製造方法の工程説明図である。図
8において示す基板11、電極12,13は実施の形態
1におけるものと同様である。本実施の形態2では、バ
ンプ付き電子部品16を基板に接着し、同時に金バンプ
17を電極12に導通させるための方法として異方性導
電材を用いるものである。まず、基板11上の電極12
の周囲には異方性導電材44が貼付される。異方性導電
材44は熱硬化性の絶縁樹脂45中に導電粒子46を含
有させたものである(図9参照)。(Second Embodiment) FIG. 8 and FIG. 9 are process explanatory views of an electronic component manufacturing method according to a second embodiment of the present invention. The substrate 11 and the electrodes 12 and 13 shown in FIG. 8 are the same as those in the first embodiment. In the second embodiment, an anisotropic conductive material is used as a method for adhering the electronic component 16 with bumps to the substrate and at the same time electrically connecting the gold bumps 17 to the electrodes 12. First, the electrode 12 on the substrate 11
Anisotropic conductive material 44 is attached to the periphery of. The anisotropic conductive material 44 is a thermosetting insulating resin 45 containing conductive particles 46 (see FIG. 9).
【0025】次にバンプ付電子部品16の金バンプ17
を電極12上に位置合せし、加熱ツール(図示せず)で
バンプ付電子部品16を下降させて金バンプ17を電極
12に対して押圧する。これにより図9に示すように金
バンプ17を導電粒子45を介して電極12の金膜24
Aと導通させると同時に絶縁樹脂45を熱硬化させる。
このとき、金膜24Aは前工程でプラズマ処理され、導
通阻害物25が除去されているので金バンプ17と電極
12の良好な導通を確保することができる。これ以降の
工程については実施の形態1と同様である。Next, the gold bump 17 of the bumped electronic component 16
Is aligned with the electrode 12, and the bumped electronic component 16 is lowered by a heating tool (not shown) to press the gold bump 17 against the electrode 12. As a result, as shown in FIG. 9, the gold bumps 17 are formed on the gold film 24 of the electrode 12 via the conductive particles 45.
At the same time as conducting with A, the insulating resin 45 is thermally cured.
At this time, the gold film 24A is plasma-treated in the previous step and the conduction block 25 is removed, so that good conduction between the gold bump 17 and the electrode 12 can be secured. The subsequent steps are the same as those in the first embodiment.
【0026】(実施の形態3)図10は本発明の実施の
形態3の電子部品製造方法の工程説明図である。図10
において示す基板11、電極12,13は実施の形態1
におけるものと同様である。本実施の形態3では、バン
プ付き電子部品16を絶縁樹脂により基板11に接着
し、金バンプ17を電極12に直接導通させるものであ
る。まず、基板11上の電極12の周囲には絶縁樹脂4
7が塗布される。(Third Embodiment) FIG. 10 is a process explanatory diagram of an electronic component manufacturing method according to a third embodiment of the present invention. Figure 10
The substrate 11 and the electrodes 12 and 13 shown in FIG.
The same as in. In the third embodiment, the electronic component 16 with bumps is bonded to the substrate 11 with an insulating resin so that the gold bumps 17 are directly connected to the electrodes 12. First, the insulating resin 4 is formed around the electrode 12 on the substrate 11.
7 is applied.
【0027】次にバンプ付電子部品16の金バンプ17
を電極12に位置合せし、バンプ付電子部品16を下降
させて金バンプ17を電極12に対して押圧する。これ
により図10に示すように金バンプ17は電極12の金
膜24Aに直接接触して導通する。このとき金膜24A
は前工程でプラズマ処理され、導通阻害物が除去されて
いるので金バンプ17と電極12の良好な導通を確保す
ることができる。Next, the gold bump 17 of the bumped electronic component 16
Is aligned with the electrode 12, the electronic component 16 with bump is lowered, and the gold bump 17 is pressed against the electrode 12. As a result, as shown in FIG. 10, the gold bump 17 is brought into direct contact with the gold film 24A of the electrode 12 to be electrically connected. At this time, the gold film 24A
Since the plasma treatment was performed in the previous step to remove the conduction inhibitor, good conduction between the gold bump 17 and the electrode 12 can be ensured.
【0028】この後バンプ付き電子部品16を所定時間
基板11に押圧しながら保持することにより絶縁樹脂4
7が硬化し、バンプ付き電子部品16は基板11に固着
される。これ以降の工程については実施の形態1と同様
である。Thereafter, the bumped electronic component 16 is pressed against the substrate 11 for a predetermined period of time and held, whereby the insulating resin 4 is formed.
7 is cured and the bumped electronic component 16 is fixed to the substrate 11. The subsequent steps are the same as those in the first embodiment.
【0029】以上各実施の形態で説明したように、バン
プ付電子部品16のボンディングに先立って基板11の
上面をプラズマ処理することにより、部分めっき法など
の複雑な工程を必要とすることなく、同一基板に形成さ
れた複数の電極の一方の電極12に金バンプ17を良好
に導通させ、かつ他方の電極13に半田バンプ15を良
好に形成することができる。また、バンプ付電子部品1
6の搭載に先立って基板11のプラズマ処理を行うよう
にしているため、バンプ付電子部品16へのプラズマに
よるダメージが発生しない。さらに、電極12、13上
に形成される金膜は極めて薄いものであるため、高価な
材料である金の消費量を減少させてコストの低減をはか
ることができる。As described in each of the above embodiments, by plasma-treating the upper surface of the substrate 11 prior to bonding the electronic component 16 with bumps, a complicated process such as a partial plating method is not required, The gold bump 17 can be satisfactorily conducted to one electrode 12 of the plurality of electrodes formed on the same substrate, and the solder bump 15 can be satisfactorily formed on the other electrode 13. Also, electronic component with bump 1
Since the plasma treatment of the substrate 11 is performed prior to the mounting of 6, the electronic component 16 with bumps is not damaged by the plasma. Furthermore, since the gold film formed on the electrodes 12 and 13 is extremely thin, it is possible to reduce the amount of gold, which is an expensive material, to reduce the cost.
【0030】なお、バンプ付き電子部品16と電極の接
続方法の代表的な例を、実施の形態1、2および3で説
明したが、本発明はこれに限定されるものではない。Although a typical example of the method of connecting the electronic component 16 with bumps to the electrodes has been described in the first, second and third embodiments, the present invention is not limited to this.
【0031】[0031]
【発明の効果】本発明によれば、金バンプが導通する電
極上の金膜表面の導通阻害物を除去することにより、部
分メッキ法などの複雑な工程を必要とせずに同一基板に
形成された複数の電極の一方に金バンプを良好に導通さ
せるとともに、他方の電極に半田バンプを接合性良く形
成することができる。さらに、電極上に形成される金膜
は極めて薄いものであるため、高価な材料である金の消
費量を減少させてコストの低減をはかることができる。According to the present invention, by removing the conduction inhibitor on the surface of the gold film on the electrode through which the gold bump conducts, the gold bump is formed on the same substrate without requiring a complicated process such as a partial plating method. In addition, the gold bump can be satisfactorily conducted to one of the plurality of electrodes, and the solder bump can be formed on the other electrode with good bondability. Furthermore, since the gold film formed on the electrode is extremely thin, it is possible to reduce the amount of gold, which is an expensive material, to reduce the cost.
【図1】本発明の実施の形態1の電子部品の側断面図FIG. 1 is a side sectional view of an electronic component according to a first embodiment of the present invention.
【図2】本発明の実施の形態1の電子部品製造方法の工
程説明図FIG. 2 is a process explanatory view of the electronic component manufacturing method according to the first embodiment of the present invention.
【図3】本発明の実施の形態1の電子部品製造方法の工
程説明図FIG. 3 is a process explanatory diagram of the electronic component manufacturing method according to the first embodiment of the present invention.
【図4】本発明の実施の形態1の電子部品製造方法の工
程説明図FIG. 4 is a process explanatory view of the electronic component manufacturing method according to the first embodiment of the present invention.
【図5】本発明の実施の形態1の電子部品製造方法の工
程説明図FIG. 5 is a process explanatory diagram of the electronic component manufacturing method according to the first embodiment of the present invention.
【図6】本発明の実施の形態1の電子部品製造方法の工
程説明図FIG. 6 is a process explanatory view of the electronic component manufacturing method according to the first embodiment of the present invention.
【図7】本発明の実施の形態1の電子部品製造方法の工
程説明図FIG. 7 is a process explanatory view of the electronic component manufacturing method according to the first embodiment of the present invention.
【図8】本発明の実施の形態2の電子部品製造方法の工
程説明図FIG. 8 is a process explanatory diagram of an electronic component manufacturing method according to a second embodiment of the present invention.
【図9】本発明の実施の形態2の電子部品製造方法の工
程説明図FIG. 9 is a process explanatory diagram of the electronic component manufacturing method according to the second embodiment of the present invention.
【図10】本発明の実施の形態3の電子部品製造方法の
工程説明図FIG. 10 is a process explanatory diagram of an electronic component manufacturing method according to a third embodiment of the present invention.
【図11】半田バンプに溶け込む金の割合と半田バンプ
の接合強度との関係を示すグラフFIG. 11 is a graph showing the relationship between the proportion of gold that dissolves in the solder bumps and the bonding strength of the solder bumps.
【図12】従来の電子部品の断面図FIG. 12 is a sectional view of a conventional electronic component.
11 基板 12、13 電極 15 半田バンプ 16 バンプ付き電子部品 17 金バンプ 22A、22B 銅電極 23A、23B ニッケル膜 24A、24B 金膜 25 導通阻害物 41、45、47 絶縁樹脂 43 半田ボール 44 異方性導電材 46 導電粒子 11 board 12, 13 electrodes 15 Solder bump 16 Electronic components with bumps 17 gold bumps 22A, 22B Copper electrode 23A, 23B Nickel film 24A, 24B Gold film 25 conduction blocker 41, 45, 47 Insulating resin 43 Solder ball 44 anisotropic conductive material 46 Conductive particles
フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 23/12 H01L 21/60 Continuation of front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 23/12 H01L 21/60
Claims (4)
せるための第1の電極と半田バンプを形成するための第
2の電極を形成する第1の工程と、これらの電極上に少
なくともニッケルを含むバリア層を形成する第2の工程
と、これらのバリア層の表面に金膜を形成する第3の工
程と、前記第1の電極上の金膜の表面に生成した導通阻
害物を除去する第4の工程と、バンプ付電子部品のバン
プを前記第1の電極に位置合せして導通させるとともに
このバンプ付電子部品を基板に固着させる第5の工程
と、前記第2の電極上に半田バンプを形成する第6の工
程とを含むことを特徴とする電子部品製造方法。1. A first step of forming a first electrode for electrically connecting to a bump of an electronic component with bumps and a second electrode for forming a solder bump on a substrate, and at least nickel on these electrodes. A second step of forming a barrier layer containing Al, a third step of forming a gold film on the surface of these barrier layers, and removal of a conduction inhibitor generated on the surface of the gold film on the first electrode. And a fifth step of aligning the bumps of the electronic component with bumps with the first electrode to make them conductive and fixing the electronic component with bumps to the substrate, and the second electrode on the second electrode. And a sixth step of forming solder bumps.
よるスパッタリングを利用して前記金膜の表面に生成し
た導通阻害物を除去することを特徴とする請求項1記載
の電子部品製造方法。2. The method of manufacturing an electronic component according to claim 1, wherein in the fourth step, the conduction inhibitor generated on the surface of the gold film is removed by utilizing sputtering by plasma treatment.
理を施して前記第1の電極上の金膜表面の導通阻害物の
生成を促進した後にこの導通阻害物を除去することによ
り、前記金膜中に含まれる金属不純物をより多く除去す
ることを特徴とする請求項1記載の電子部品製造方法。3. Prior to the fourth step, by subjecting the substrate to a heat treatment to promote generation of a conduction inhibitor on the surface of the gold film on the first electrode, the conduction inhibitor is removed. 2. The method of manufacturing an electronic component according to claim 1, further comprising removing more metal impurities contained in the gold film.
け込む金の重量%が0.1%以下となる値であり、下限
値は0.01μmであることを特徴とする請求項1記載
の電子部品の製造方法。4. The upper limit of the thickness of the gold film is such that the weight% of gold dissolved in the solder bump is 0.1% or less, and the lower limit thereof is 0.01 μm. 1. A method for manufacturing an electronic component according to 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP01372698A JP3381602B2 (en) | 1998-01-27 | 1998-01-27 | Electronic component manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP01372698A JP3381602B2 (en) | 1998-01-27 | 1998-01-27 | Electronic component manufacturing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH11214446A JPH11214446A (en) | 1999-08-06 |
JP3381602B2 true JP3381602B2 (en) | 2003-03-04 |
Family
ID=11841258
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP01372698A Expired - Fee Related JP3381602B2 (en) | 1998-01-27 | 1998-01-27 | Electronic component manufacturing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3381602B2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4575839B2 (en) * | 2004-05-28 | 2010-11-04 | パナソニック株式会社 | Joining apparatus and joining method |
US8240539B2 (en) | 2004-05-28 | 2012-08-14 | Panasonic Corporation | Joining apparatus with UV cleaning |
CN1943029A (en) * | 2005-03-23 | 2007-04-04 | 松下电器产业株式会社 | Semiconductor device and method for manufacturing same |
-
1998
- 1998-01-27 JP JP01372698A patent/JP3381602B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH11214446A (en) | 1999-08-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2751912B2 (en) | Semiconductor device and manufacturing method thereof | |
JP5141076B2 (en) | Semiconductor device | |
US6576539B1 (en) | Semiconductor chip assembly with interlocked conductive trace | |
JPH0936186A (en) | Power semiconductor module and its mounting method | |
JP2000349194A (en) | Semiconductor device and its manufacture | |
JP3381602B2 (en) | Electronic component manufacturing method | |
US6699780B1 (en) | Method of connecting a conductive trace to a semiconductor chip using plasma undercut etching | |
JP3116926B2 (en) | Package structure and semiconductor device, package manufacturing method, and semiconductor device manufacturing method | |
JP3279470B2 (en) | Semiconductor device and manufacturing method thereof | |
JPH05235102A (en) | Semiconductor device | |
CN211792251U (en) | Embedded copper structure for microelectronic package | |
JP3438583B2 (en) | Anisotropic conductive film connection method | |
JP3389853B2 (en) | Electronic component and solder bump forming method | |
JP3078781B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
JP3279844B2 (en) | Semiconductor device and manufacturing method thereof | |
JP3257953B2 (en) | Method for manufacturing substrate for hybrid integrated circuit | |
JP2676107B2 (en) | Substrate for mounting electronic components | |
JP2757594B2 (en) | Film carrier equipment | |
JP3454097B2 (en) | Electronic component and method of manufacturing electronic component | |
EP2782124A1 (en) | Power semiconductor mounting | |
US20100148364A1 (en) | Semiconductor device and method for producing semiconductor device | |
JPH10163241A (en) | Manufacture of electronic component | |
JPH04356935A (en) | Bump-electrode formation and mounting structure of semiconductor device | |
JP3934739B2 (en) | Plug-in type electronic control unit and connection structure between wiring board and plug member | |
JPH1079570A (en) | Method of electrically jointing electronic element chip to wiring circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071220 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081220 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091220 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091220 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101220 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101220 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111220 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111220 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121220 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121220 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131220 Year of fee payment: 11 |
|
LAPS | Cancellation because of no payment of annual fees |