TW201101458A - Stackable package and method for making the same and semiconductor package - Google Patents

Stackable package and method for making the same and semiconductor package Download PDF

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Publication number
TW201101458A
TW201101458A TW98121299A TW98121299A TW201101458A TW 201101458 A TW201101458 A TW 201101458A TW 98121299 A TW98121299 A TW 98121299A TW 98121299 A TW98121299 A TW 98121299A TW 201101458 A TW201101458 A TW 201101458A
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Taiwan
Prior art keywords
electrical connection
package structure
substrate
wafer
connection point
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TW98121299A
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Chinese (zh)
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TWI389296B (en
Inventor
Chi-Chih Chu
Cheng-Yi Weng
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Advanced Semiconductor Eng
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Priority to TW98121299A priority Critical patent/TWI389296B/en
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Publication of TWI389296B publication Critical patent/TWI389296B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The present invention relates to a stackable package and a method for making the same and a semiconductor package. The stackable package includes a substrate, a chip, a leadframe and a molding compound. The chip is disposed on the substrate, and is electrically connected to the substrate. The leadframe is attached to the substrate, and includes a plurality of leads and a plurality of electrical connecting pads. The leads electrically connect the electrical connecting pads to the substrate, and define an accommodating space for accommodating the chip. The molding compound encapsulates the chip and the leadframe, and exposes the electrical connecting pads. Therefore, the leadframe enables a standard memory to be stacked on the stackable package, and reduces the thickness of the package. Moreover, the leadframe provides a connecting surface having high density circuit on the upper surface of the molding compound, so that an upper package of any types can be stacked on the stackable package.

Description

201101458 六、發明說明： 【發明所屬之技術領域】 本發明係關於-種封裝結構及其製造方法，詳言之，係 關於種具有導線架之可堆疊式封裝結構及其製造方法及 堆疊後之半導體封裝結構。 【先前技術】 參考圖1 ’顯不習知第一種可堆疊式封裝結構之剖面示 Ο Ο 意，。該習知第一種可堆疊式封裝結構1包括-基板Η、 日曰片12、複數條導線13、—封膠體及複數個銲球 該基板11包括-第一表面lu、一第二表面⑴、複數個穿 導孔13及複數個電性連接點〗丨4。該等穿導孔113係貫穿 該基板11，該等電性連接點114係位於該基板11之第一表 之外圍顯路於該第一表面i i 1。該晶片12位於該201101458 VI. Description of the Invention: [Technical Field] The present invention relates to a package structure and a method of fabricating the same, and more particularly to a stackable package structure having a lead frame, a method of manufacturing the same, and a stacked Semiconductor package structure. [Prior Art] Referring to Fig. 1', a cross-sectional view of the first stackable package structure is not known. The first stackable package structure 1 includes a substrate Η, a corrugated sheet 12, a plurality of wires 13, a sealant, and a plurality of solder balls. The substrate 11 includes a first surface lu and a second surface (1). , a plurality of through holes 13 and a plurality of electrical connection points 丨 。 4. The through holes 113 extend through the substrate 11. The electrical connection points 114 are located on the first surface i i 1 at the periphery of the first surface of the substrate 11. The wafer 12 is located at the

板之第表面111。該等導線】3係電性連接該基板U 及該晶片12。該封膠體14係包覆部分該基板u、該晶片12 及該等導線13。該等銲球15係位於該基板n之第二表面 112 ° 該習知第一種可堆疊式封裝結構1之缺點如下。,等電 性連接點114係㈣該基板11之第—表面m之外圍，使得 該等電性連接點114之分佈不符合―標準記憶體 —之鲜球之分佈，而無法堆疊該標準記憶體 (Standard M_ry)於該習知第—種可堆疊式封裝結構】之 頂端。 參考圖2’顯Μ知第：種可堆#式封裝結構之剖面示 139983.doc 201101458 意圖。該習知第二種可堆疊式封裝結構2包括一第一基板 • 21、一第—晶片22、一底膠23、一介電層24、一第二基板 25、複數條導線26、一封膠體27及複數個銲球28。該第一 基板21具有一第一表面211及一第二表面212。該第一晶片 22位於該第—基板21上，且包括複數個第一凸塊221。該 底膠23係包覆該第一晶片22之該等第一凸塊22ι。該介電 層24係位於該第一晶片22上。該第二基板25係位於該介電 ❹ 層24上，且包括第一表面251、一第二表面252及複數個電 性連接點253，該第一表面251係接觸該介電層24，該等電 性連接點253係位於該第二表面252。該等導線26係電性連 接該第二基板25及該第一基板21。該封膠體27係包覆該第 一基板21之第一表面211、該第一晶片U、該介電層24、 該第二基板25之第一表面251及該等導線26，且顯露該第 二基板25之電性連接點253。該等銲球28係位於該第一基 板21之第二表面212。 Q 該習知第二種可堆疊式封裝結構2之缺點如下。該可堆 疊式封裝結構2雖然可供一標準記憶體（standard Memory) 堆疊’但需額外使用一介電層24置於該第一晶片22及該第 二基板25之間，而使該可堆疊式封裝結構2之厚度增加， 並提高成本。 因此’有必要提供一種可堆疊式封裝結構及其製造方法 及半導體封裝結構，以解決上述問題。 【發明内容】 本發明提供一種可堆疊式封裝結構，其包括一基板、一 139983.doc • 6 · 201101458 晶片 一導線架及一封膠體。該基板具有一上表面、一下 表面及至少一第一銲墊，該第一銲墊係位於該上表面。該 晶片位於該基板之上表面，且電性連接至該基板。該導線 架附著於該基板之上表面，該導線架包括複數個引腳及複 數個電性連接點，該等引腳連接該等電性連接點，每一引 腳包括-第一部分、一第二部分及一中間部分，該第一部 分係電性連接該第-銲塾，該第二部分係連接該電性連接 Ο 點，該中間部分連接該第一部分及該第二部分，該第二部 分及該中間部分定義出一容置空間以容置該晶片。該封膠 體包覆該基板之上表面、該晶片及該導線架’且顯露該等 電性連接點。 本發=提供—種可堆疊式封裝結構，其包括一封膠 體、一導線架、一晶μ 一 s片及一基板。該封膠體具有一接合表 表面顯露複數個電性連接點，該等電性連接點 嗲蓉當带 連接點及複數個第二電性連接點，且 該等第一電性連接點位於該等第二電性 導線架位於該封膠體内， '' 。〇 電性連接點— °導線表包括複數個引腳及該等 電/·生連接點，每一5,腳包括一第 、 中間部分’該第二部分係連接該電性:分及-連接該第-部分及該第：部^^點，該中間部分 定義出一容置由 ^第—口 及該中間部分 數個第二_:;等腳包括複數個第一引腳及複 該等第二引腳連接該等第二==第:電:連接點， 穿過二個相鄰之第—電帛點’母-第二引腳係 連接點之間隙。該晶片位於該容 I39983.doc 201101458 置空間内。該基板具有一第一表面、The first surface 111 of the board. The wires 3 are electrically connected to the substrate U and the wafer 12. The encapsulant 14 covers a portion of the substrate u, the wafer 12, and the wires 13. The solder balls 15 are located on the second surface 112 of the substrate n. The disadvantages of the first stackable package structure 1 are as follows. The isoelectric connection point 114 is (4) the periphery of the first surface m of the substrate 11, such that the distribution of the electrical connection points 114 does not conform to the distribution of the "standard memory" fresh balls, and the standard memory cannot be stacked. (Standard M_ry) is at the top of the conventional stackable package structure. Referring to Fig. 2', it is apparent that the cross section of the type of package can be 139983.doc 201101458. The second stackable package structure 2 includes a first substrate 21, a first wafer 22, a primer 23, a dielectric layer 24, a second substrate 25, a plurality of wires 26, and a Colloid 27 and a plurality of solder balls 28. The first substrate 21 has a first surface 211 and a second surface 212. The first wafer 22 is located on the first substrate 21 and includes a plurality of first bumps 221 . The primer 23 covers the first bumps 22 of the first wafer 22. The dielectric layer 24 is on the first wafer 22. The second substrate 25 is disposed on the dielectric layer 24 and includes a first surface 251, a second surface 252, and a plurality of electrical connection points 253. The first surface 251 contacts the dielectric layer 24. An isoelectric connection point 253 is located on the second surface 252. The wires 26 are electrically connected to the second substrate 25 and the first substrate 21. The encapsulant 27 covers the first surface 211 of the first substrate 21, the first wafer U, the dielectric layer 24, the first surface 251 of the second substrate 25, and the wires 26, and the first surface is exposed. The electrical connection point 253 of the two substrates 25 is obtained. The solder balls 28 are located on the second surface 212 of the first substrate 21. Q The disadvantages of the second stackable package structure 2 are as follows. The stackable package structure 2 can be stacked as a standard memory but requires an additional dielectric layer 24 to be placed between the first wafer 22 and the second substrate 25 to make the stackable The thickness of the package structure 2 is increased and the cost is increased. Therefore, it is necessary to provide a stackable package structure, a method of manufacturing the same, and a semiconductor package structure to solve the above problems. SUMMARY OF THE INVENTION The present invention provides a stackable package structure including a substrate, a 139983.doc • 6 · 201101458 wafer, a lead frame, and a gel. The substrate has an upper surface, a lower surface and at least one first bonding pad, the first bonding pad being located on the upper surface. The wafer is located on an upper surface of the substrate and is electrically connected to the substrate. The lead frame is attached to the upper surface of the substrate, the lead frame includes a plurality of pins and a plurality of electrical connection points, and the pins are connected to the electrical connection points, and each of the pins includes a first part, a first a second portion and an intermediate portion, the first portion is electrically connected to the first bead, the second portion is connected to the electrical connection point, the intermediate portion is connected to the first portion and the second portion, the second portion And the middle portion defines an accommodating space for accommodating the wafer. The encapsulant encapsulates the upper surface of the substrate, the wafer and the lead frame' and exposes the electrical connection points. The present invention provides a stackable package structure comprising a glue body, a lead frame, a crystal chip and a substrate. The encapsulant has a plurality of electrical connection points on a surface of the bonding surface, the electrical connection point is a connection point of the cicada and a plurality of second electrical connection points, and the first electrical connection points are located at the same The second electrical lead frame is located in the sealant body, ''. 〇 Electrical connection point — ° The wire list includes a plurality of pins and the electrical connection points, and each of the 5 feet includes a first and middle portion. The second portion is connected to the electrical: minute and - connected The first part and the part: the ^^ point, the middle part defines a plurality of second _:; and the middle part includes a plurality of first pins and the plurality of first pins The second pin is connected to the second ==: electrical: connection point, through the gap between the two adjacent first-electrode point 'mother-second pin system connection point. The wafer is located in the space of the I39983.doc 201101458 space. The substrate has a first surface,

一部分電性連接至該等電性連接點。A portion is electrically connected to the electrical connection points.

之製造方法，其包 該基板具有·一上表面、一下 一銲墊係位於該上表面；（b) ’該晶片係電性連接至該基 板；⑷提供-導線架，該導線架包括複數個引腳及複數個 電性連接點mi料接料雜連接點，每—引腳包 中間部分，該第二部分係 括一第一部分、一第二部分及一 連接該電性連接點，該中間部分連接該第一部分及該第二 部分，該第二部分及該中間部分定義出一容置空間以容置 該晶片；（d)附著該導線架於該基板之上表面，使每一引腳 〇 之第一部分電性連接該第一銲墊，且該晶片位於該容置空 間内；及（e)形成一封膠體，以覆蓋該基板之上表面、該 片及該導線架’且顯露該等電性連接點。 本發明再提供一種半導體封裝結構，其包括一可堆疊式 封裝結構及至少一上封裝結構。該可堆疊式封裝結構包括 一基板、一晶片、一導線架及一封膠體。該基板具有一上 表面、一下表面及至少一第一銲墊，該第一銲墊係位於該 上表面。該晶片位於該基板之上表面，且電性連接至該基 板。該導線架附著於該基板之上表面，該導線架包括複數 139983.doc -8 - 201101458 個引腳及複數個電性連接點， ” 該專引腳連接該等電性連接 點，每一引腳包括一第一部 |刀 一第二部分及一中簡邱 分，該第一部分係電性連接 ° 吊鮮墊，該第二部分係遠 接該電性連接點，該中間部分 、 八社@ ^ \ 連接該第一部分及該第二部 刀，該第一口 ρ分及該中間部分 一— 疋義出一谷置空間以容置該a manufacturing method comprising: the substrate having an upper surface, a lower pad being located on the upper surface; (b) 'the wafer is electrically connected to the substrate; (4) providing a lead frame, the lead frame comprising a plurality of a pin and a plurality of electrical connection points, wherein the second portion of the first portion, a second portion and a connection portion of the electrical connection point, the middle portion Partially connecting the first portion and the second portion, the second portion and the intermediate portion defining an accommodating space for accommodating the wafer; (d) attaching the lead frame to the upper surface of the substrate to make each pin The first portion of the crucible is electrically connected to the first pad, and the wafer is located in the accommodating space; and (e) forming a gel to cover the upper surface of the substrate, the sheet and the lead frame' and revealing the Isoelectric connection point. The present invention further provides a semiconductor package structure including a stackable package structure and at least one upper package structure. The stackable package structure includes a substrate, a wafer, a lead frame and a gel. The substrate has an upper surface, a lower surface and at least one first bonding pad, the first bonding pad being located on the upper surface. The wafer is located on the upper surface of the substrate and is electrically connected to the substrate. The lead frame is attached to the upper surface of the substrate, and the lead frame includes a plurality of 139983.doc -8 - 201101458 pins and a plurality of electrical connection points, wherein the dedicated pin connects the electrical connection points, each lead The foot includes a first part, a second part of the knife, and a middle part, the first part is electrically connected to the hanging pad, and the second part is connected to the electrical connection point, the middle part, the eighth part @ ^ \ connects the first part and the second part of the knife, the first port ρ points and the middle part one - a meaning of a valley space to accommodate the

:片。該封穋體包覆該基板之上表面、該晶片及該導線 架，且顯露該等電性連接點。該上封裝結構係位於該可堆 叠式封裝結構上，且電㈣接至該可堆疊式封裝結構。 藉此，該導線架使該等電性連接點之分佈符合—標準記 憶體(Standard Memory)之銲球之分佈，而得以堆疊續栌準 記憶體於本發明可堆疊式封裝結構之頂端。再/該㈣ 架可避免使用額外之介電層，而減少本發明可堆疊式封裝 結構之總厚度。並且，該導線架於該封膠體之上表面提供 一南線路密集度之接合表面，以供堆疊任一種態樣之上封 裝結構。此外，使用-標準四方形之模具以形成該封勝 體’即可顯露該等電性連接點，而不需研發特殊形狀之模 具，故可降低製造成本。 【實施方式】 參考圖3至圖11，顯示本發明可堆疊式封裝結構之第一 實施例之製造方法之示意圖。參考圖3，提供一基板31， 該基板31具有一上表面311(即第一表面）、一下表面312(即 第二表面）、至少一第一銲墊313及複數個第二銲墊314, 該第一銲墊313及該等第二銲墊314係位於該上表面311(即 第一表面）。參考圖4，設置至少一銲料（s〇lder paste)32於 139983.doc -9- 201101458 該基板3 1之第一銲墊3 13上。較佳地，該銲料32係利用沾 • 錫（DlPPing solder Paste)或印刷製程設置於該基板31之第 一銲墊313上。 參考圖5’設置一晶片於該基板31之上表面311(即第一 表面），該晶片係電性連接至該基板31。在本實施例中， 該晶片係為一打線晶片33，該打線晶片33係透過複數條導 線331電性連接至該基板31之第二銲墊314，且利用一黏著 層332附著於該基板31。然而，在其他應用中，參考圖6, 該b曰片係可為一覆晶晶片34，其包括一上表面341(即背 面）、一下表面342(即主動面）及複數個凸塊343，該等凸塊 343係位於該下表面342(即主動面），且該覆晶晶片34係透 過該等凸塊343電性連接至該基板31之第二銲墊314。 參考圖7至圖9,提供一導線架35,該導線架35包括複數 個引腳351、複數個電性連接點352及一邊框354。在本實 施例中，該等電性連接點352包括複數個第一電性連接點 ❹ 352A及複數個第二電性連接點352B，然而，在其他實施 例中’該等電性連接點352更包括至少一第三電性連接點 352C(圖15) ’其中該等第一電性連接點352A及該等第二電 性連接點352B係位於該打線晶片33之正上方，該至少一第 二電性連接點352C係位於該打線晶片33外之相對位置。 該等引腳351連接該等電性連接點352(第一電性連接點 352A、第二電性連接點352B及第三電性連接點352C)。每 一引腳351包括一第一部分3511、一第二部分3512及一中 間部分3513 ’該第二部分3512係連接該電性連接點352(第 139983.doc -10- 201101458 • —電性連接點352A、第二電性連接點352B及第三電性連 ‘ 接點352C)，該中間部分⑸3連接該第一部们川及該第 二部分3512。較佳地，該導線架35之材f係為銅。在本實 施例中，該第一部分35Π與該第二部分3512平行，且具有 一高度差，而該中間部分3513分別與該第一部分3511^該 第二部分3512間具有一夾角，使每一引腳351具有二個彎 折處，該第二部分3512及該中間部分3513定義出一容置空 〇 Pal 353 °在本實施例中’每二個相鄰之電性連接點352(第 一電性連接點352A、第二電性連接點352β及第三電性連 接點352C)之間具有一間距，且每一電性連接點352(第一 電性連接點352A、第二電性連接點352B及第三電性連接 點352C)包括一本體3521及一電鍍層3522，該本體”以連 接該引腳351之第二部分3512，該電鍍層3522位於該本體 3521上，且該電鑛層3522之材質係可為但不限定於鎳金。 在本實施例中，該邊框354係用以連接並固定該等引腳 〇 351 ° 接著，較佳地’利用一膠帶（圖中未示）黏著該等電性連 接點352(第一電性連接點352A、第二電性連接點352B及第 二電性連接點352C)及該等引腳351之第二部分35 12，以固 定該等引腳351，直到形成一封膠體36(圖ι〇)後再予以除 移。接著，附著該導線架35於該基板31之上表面311(即第 一表面），使每一引腳351之第一部分3511電性連接該第一 銲塾313 ’且該打線晶片33位於該容置空間353内。在本實 施例中’該導線架35係利用表面黏著技術（Surface Mount 139983.doc -11- 201101458:sheet. The package covers the upper surface of the substrate, the wafer and the lead frame, and exposes the electrical connection points. The upper package structure is located on the stackable package structure and electrically connected to the stackable package structure. Thereby, the lead frame allows the distribution of the electrical connection points to conform to the distribution of the solder balls of the standard memory, and the stacked memory is stacked on top of the stackable package structure of the present invention. The /four shelf avoids the use of additional dielectric layers and reduces the overall thickness of the stackable package structure of the present invention. Moreover, the lead frame provides a south line-dense bonding surface on the upper surface of the encapsulant for mounting the structure on any of the stacked layers. In addition, the use of a standard square mold to form the seal body can reveal the electrical connection points without the need to develop a mold of a special shape, thereby reducing manufacturing costs. [Embodiment] Referring to Figs. 3 to 11, there are shown schematic views of a manufacturing method of a first embodiment of the stackable package structure of the present invention. Referring to FIG. 3, a substrate 31 is provided. The substrate 31 has an upper surface 311 (ie, a first surface), a lower surface 312 (ie, a second surface), at least one first bonding pad 313, and a plurality of second bonding pads 314. The first pad 313 and the second pads 314 are located on the upper surface 311 (ie, the first surface). Referring to FIG. 4, at least one solder paste 32 is disposed on the first pad 3 13 of the substrate 31 on 139983.doc -9- 201101458. Preferably, the solder 32 is disposed on the first pad 313 of the substrate 31 by using a soldering process or a printing process. A wafer is disposed on the upper surface 311 (i.e., the first surface) of the substrate 31 with reference to FIG. 5', and the wafer is electrically connected to the substrate 31. In this embodiment, the wafer is a wire wafer 33 that is electrically connected to the second pad 314 of the substrate 31 through a plurality of wires 331 and is attached to the substrate 31 by an adhesive layer 332. . However, in other applications, referring to FIG. 6, the b-plate can be a flip chip 34 including an upper surface 341 (ie, a back surface), a lower surface 342 (ie, an active surface), and a plurality of bumps 343. The bumps 343 are located on the lower surface 342 (ie, the active surface), and the flip chip 34 is electrically connected to the second pads 314 of the substrate 31 through the bumps 343. Referring to Figures 7 through 9, a lead frame 35 is provided. The lead frame 35 includes a plurality of pins 351, a plurality of electrical connection points 352, and a bezel 354. In this embodiment, the electrical connection point 352 includes a plurality of first electrical connection points 352 352A and a plurality of second electrical connection points 352B. However, in other embodiments, the electrical connection points 352 The first electrical connection point 352A and the second electrical connection point 352B are located directly above the wire bonding die 33, and the at least one first The two electrical connection points 352C are located at opposite positions outside the wire bonding die 33. The pins 351 are connected to the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C). Each of the leads 351 includes a first portion 3511, a second portion 3512, and a middle portion 3513. The second portion 3512 is connected to the electrical connection point 352 (No. 139983.doc -10- 201101458 • Electrical connection point 352A, a second electrical connection point 352B, and a third electrical connection 'contact 352C'. The intermediate portion (5) 3 connects the first portion and the second portion 3512. Preferably, the material f of the lead frame 35 is copper. In this embodiment, the first portion 35 is parallel to the second portion 3512 and has a height difference, and the intermediate portion 3513 has an angle with the first portion 3511 and the second portion 3512, respectively. The foot 351 has two bends, and the second portion 3512 and the intermediate portion 3513 define an accommodation space Pal 353 ° in the present embodiment 'every two adjacent electrical connection points 352 (first electric There is a spacing between the sexual connection point 352A, the second electrical connection point 352β and the third electrical connection point 352C), and each electrical connection point 352 (the first electrical connection point 352A, the second electrical connection point) 352B and the third electrical connection point 352C) include a body 3521 and a plating layer 3522, the body is connected to the second portion 3512 of the pin 351, the plating layer 3522 is located on the body 3521, and the electric ore layer The material of 3522 can be, but is not limited to, nickel gold. In this embodiment, the frame 354 is used to connect and fix the pins 〇 351 °, and then preferably 'use a tape (not shown) Adhering to the electrical connection point 352 (first electrical connection point 352A, second electrical connection Point 352B and second electrical connection point 352C) and second portion 35 12 of the pins 351 are used to fix the pins 351 until a glue 36 (Fig. 1) is formed and then removed. The lead frame 35 is attached to the upper surface 311 of the substrate 31 (ie, the first surface), so that the first portion 3511 of each pin 351 is electrically connected to the first pad 313 ′ and the wire wafer 33 is located therein. In the space 353. In the present embodiment, the lead frame 35 utilizes surface adhesion technology (Surface Mount 139983.doc -11-201101458

Technology，SMT)透過該銲料32附著於該基板31之上表面 ‘ 311(即第一表面）。 然而，在其他實施例中，係可先於該打線晶片33上放置 一分隔晶片38(圖16)，再附著該導線架35於該基板31之上 表面311(即第一表面），以使該分隔晶片38支撐該等引腳 351或者，係可先利用噴流（Dispensing)或印刷（Printing) 方式形成一低模流薄膜（Low Modules Film)39(圖17)以包覆 ❹ 該打線晶片33及該等導線331，再附著該導線架35於該基 板31之上表面311(即第一表面），以使該低模流薄膜39支撐 該等引腳351。參考圖1〇,形成一封膠體36，以覆蓋該基 板31之上表面311(即第一表面）、該銲料32、該打線晶片33 及該導線架35，且顯露該等電性連接點352(第一電性連接 點3S2A、第二電性連接點3S2B及第三電性連接點352〇之 電鍍層3522。較佳地，該等電性連接點352(第一電性連接 點352A、第二電性連接點352B及第三電性連接點352c)與 〇 該封膠體36之一上表面361(即接合表面）齊平。較佳地，接 著進行單體化（Singulati〇n)製程，以形成複數個可堆疊式 封裝結構3A。該單體化製程係為切割或衝壓製程，以移除 該邊框354，而使該封膠體36之側邊362、該等引腳351之 側邊3514及該基板31之侧邊315切齊（圖u)。參考圖u，形 成複數個第一銲球37於該基板31之下表面312(即第二表 面）’同時形成本發明可堆疊式封裝結構3。 參考圖12，顯示該可堆疊式封裝結構3堆疊一上封裝尹 構4之示意圖。在本實施例中，該上封裝結構4係為一球柵 139983.doc • 12- 201101458 ρ列封裝結構（Ball Grid Array Paekage)，其包括複數個第 一鲜球41 ’每n球41係對應且電性連接並直接接觸 該導線架35之每-電性連接點352(第—電性連接點352八、 第二電性連接點352B及第三電性連接點352〇。然:而，在 其他應用巾，該上封褒結構4係不限^為—球栅陣列封襄 結構，且該封裝結構3亦可堆疊：個以上之上封裝結構7, 該等上封裝結構7係為並排，如圖13所示。 Ο 再參考圖11，顯示本發明可堆叠式封褒結構之第一實施 例之剖面示意圖。該可堆疊式封裝結構3包括一基板Η、 至少-輝料_der Paste)32、—晶片、—導線架^、—封 膠體36及複數個第一銲球37。該基板31具有一上表面 3U、-下表面312、至少一第一鮮墊313及複數個第二鲜 墊314,該第一銲墊313及該等第二銲墊314係位於該上表 面 3 11 〇 該銲料32位於該基板31之第一銲墊313上。該晶片位於 〇 該基板31之上表面3U，且電性連接至該基板31。在本實 施例中，該晶片係為一打線晶片33，該打線晶片33係透過 複數條導線331電性連接至該基板31之第二銲墊314，且利 用一黏著層332附著於該基板31。 該導線架35附著於該基板31之上表面311，該導線架％ 包括複數個引腳351及複數個電性連接點352。在本實施例 中，該等電性連接點352包括複數個第一電性連接點352A 及複數個第二電性連接點352B，然而，在其他實施例中， 該等電性連接點352更包括至少一第三電性連接點352C(圖 139983.doc •13- 201101458 15)，其中該等第一電性連接點352A及該等第二電性連接 •點352B係位於該打線晶片33之正上方，該至少一第三電性 連接點352C係位於該打線晶片33外之相對位置。 該等引腳351連接該等電性連接點352(第一電性連接點 352A、第二電性連接點352B及第三電性連接點352c)，每 一引腳351包括一第一部分3511、一第二部分3512及一中 間部分3513，該第一部分3511係透過該銲料32電性連接該 ❹ 第一銲墊313，該第二部分3512係連接該電性連接點 352(第一電性連接點352A、第二電性連接點352B及第三電 性連接點352〇，該中間部分3513連接該第一部分3511及 該第二部分3512。較佳地，該導線架35之材質係為銅。在 本實施例中，該第一部分3511與該第二部分3512平行，且 具有一高度差，而該中間部分3513分別與該第一部分3511 及該第二部分3512間具有一夾角，使每一引腳351具有二 個彎折處，該第二部分3512及該中間部分3513定義出一容 〇 置空間353以容置該打線晶片33。在本實施例中，每二個 相鄰之電性連接點352(第一電性連接點352A、第二電性連 接點352B及第三電性連接點352(：)之間具有一間距，且每 一電性連接點352(第一電性連接點352A、第二電性連接點 352B及第三電性連接點352C)包括一本體3521及一電鍵層 3522’該本體3 521連接該引腳351之第二部分3512，該電 鍍層3522位於該本體3521上，且該電鍍層3522之材質係可 為但不限定於錄金。 該封膠體36包覆該基板31之上表面311、該銲料32、該 139983.doc 201101458 打線晶片33及該導線架35 ’且顯露該等電性連接點352(第 . 一電性連接點352A、第二電性連接點352B及第三電性連 接點352C)。較佳地，該等電性連接點352(第一電性連接 點352A、第二電性連接點352B及第三電性連接點352C)與 該封膠體36之一上表面361齊平，且該封膠體36之側邊 362、該等引腳351之側邊3514及該基板31之側邊315切 齊。該等第一銲球37位於該基板31之下表面312。 ❹ 又參考圖11，顯示本發明可堆疊式封裝結構之第一實施 例之剖面示意圖。該可堆疊式封裝結構3包括一封膠體 36、一導線架35、一晶片、一基板31、至少一銲料（s〇lder Paste)32及複數個第一銲球37。 該封膠體36具有一上表面361 (即接合表面），該上表面 361(即接合表面）顯露複數個電性連接點352，該等電性連 接點352包括複數個第一電性連接點352A及複數個第二電 性連接點352B，且該等第一電性連接點352八位於該等第 Ο 二電性連接點352B之外圍（如圖8及圖9所示）。亦即該等第 一電性連接點352A包圍該等第二電性連接點352B。在本 實施例中，該等第一電性連接點352A及該等第二電性連接 點352B係位於該打線晶片33之正上方。然而，在其他實施 例中’該等電性連接點352更包括至少一第三電性連接點 352C(圖15) ’該至少一第三電性連接點352c係位於該打線 晶片3 3外之相對位置。 在本實⑯例中’每二個相鄰之電性連接點说（第一電性 連接點3 5 2 A、第-雷μ译址 一電f連接點352B及第三電性連接點 139983.doc -15- 201101458 352C)之間具有一間距，且每一電性連接點352(第一電性 . 連接點352A、第二電性連接點352B及第三電性連接點 352C)包括一本體3521及一電鍍層3522，該電鍍層^^位 於該本體3521上，且該電鍍層3522之材質係可為但不限定 於鎳金。較佳地，該等第一電性連接點352八及該等第二電 性連接點352B係位於該上表面361(即接合表面）之中央區 域且該等電性連接點352(第一電性連接點352A、第二電 ❹ 性連接點352B及第三電性連接點352C)與該封膠體36之一 上表面361(即接合表面）齊平。 該導線架35位於該封膠體36内，配合參考圖8及圖9,該 導線架35包括複數個引腳351、該等第—電性連接點352A 及該等第二電性連接點352B，每一引腳35i包括一第一部 分35H、一第二部分3S12及一中間部分35n，該第二部分 3512係連接該電性連接點说（第—電性連接點352a、第二 電性連接點352B及第三電性連接點352〇,該中間部分 〇 3513連接該第一部分35n及該第二部分3512，該第二部分 3512及該中間部分3513定義出一容置空間⑸，且該等引 腳351包括複數個第一引腳351A及複數個第二引腳35iB， u等第引腳351A連接該等第一電性連接點352a，該等 第二引腳351B連接該等第二電性連接點352b。 較佳地，該導線架35之材質係為銅。在本實施例中，該 帛-部分3511與該第二部分3512平行，且具有—高度差， 而該中間部分3513分別與該[部分3511及該第二部分 3512間具有H使每—引腳351具有二個彎折處，該 139983.doc -16 - 201101458 第二部分3512及該中間部分3513定義出一容置空間353。 在本實施例中，該等引腳351之第二部分3512連接該等電 性連接點352(第一電性連接點352A、第二電性連接點352b 及第二電性連接點352C)之本體3521。此外，每一第二引 腳35 1B係穿過二個相鄰之第一電性連接點352A之間隙。 該晶片位於該容置空間353内。在本實施例中，該晶片 係為一打線晶片33，且利用一黏著層332附著於該基板 ❹ 31。該基板31具有一上表面311(即第一表面）、一下表面 312(即第二表面）、至少一第一銲墊313及複數個第二銲墊 314，該第一銲墊313及該等第二銲墊314係位於該上表面 311(即第一表面）。該基板31之上表面311(即第一表面）承 載該晶片、該導線架35及該封膠體36〇該基板31之第一銲 墊313透過該銲料32及該等引腳351之第一部分35ιι電性連 接至該等電性連接點352(第一電性連接點352A、第二電性 連接點352B及第三電性連接點352c)。該基板31之第二銲 Ο 塾3 14透過複數條導線33 1電性連接至該打線晶片33。較佳 地，該封膠體36之側邊362、該等引腳351之側邊3514及該 基板31之側邊315切齊。該等第一銲球”位於該基板31之 下表面312(即第二表面）。 再參考圖12,較佳地，該可堆疊式封裝結構3更包括至 少一上封裝結構4，其配置於該封膠體％之一上表面 361(即接a表面）’且電性連接該等電性連接點Μ%第一電 ⑯連接點352A、第二電性連接點352B及第三電性連接點 352C)。該上封裝結構4係為一球柵陣列封裝結構⑺… 139983.doc -17· 201101458Technology (SMT) is attached to the upper surface 311 (i.e., the first surface) of the substrate 31 through the solder 32. However, in other embodiments, a spacer wafer 38 (FIG. 16) may be placed on the wire wafer 33, and the lead frame 35 may be attached to the upper surface 311 (ie, the first surface) of the substrate 31 so that The spacer chip 38 supports the pins 351 or a low mold film 39 (FIG. 17) to cover the wire wafer 33 by means of a Dispensing or Printing method. And the wires 331 are attached to the upper surface 311 (ie, the first surface) of the substrate 31 such that the low-mold film 39 supports the pins 351. Referring to FIG. 1A, a glue 36 is formed to cover the upper surface 311 (ie, the first surface) of the substrate 31, the solder 32, the wire wafer 33, and the lead frame 35, and the electrical connection points 352 are exposed. (The first electrical connection point 3S2A, the second electrical connection point 3S2B and the third electrical connection point 352 电镀 of the plating layer 3522. Preferably, the electrical connection point 352 (the first electrical connection point 352A, The second electrical connection point 352B and the third electrical connection point 352c) are flush with the upper surface 361 (ie, the bonding surface) of the encapsulant 36. Preferably, the singulating process is followed by a singulating process. To form a plurality of stackable package structures 3A. The singulation process is a cutting or stamping process to remove the bezel 354, and the side edges 362 of the encapsulant 36, the sides of the pins 351 3514 and the side edge 315 of the substrate 31 are aligned (FIG. u). Referring to FIG. u, a plurality of first solder balls 37 are formed on the lower surface 312 (ie, the second surface) of the substrate 31 while forming the stackable type of the present invention. Package Structure 3. Referring to Figure 12, there is shown a schematic diagram of the stackable package structure 3 stacked on the upper package. In an embodiment, the upper package structure 4 is a ball grid 139983.doc • 12-201101458 ρ column package structure (Ball Grid Array Paekage), which includes a plurality of first fresh balls 41 'each n ball 41 series corresponding and electric Sexually connected and directly contact each of the electrical connection points 352 of the lead frame 35 (the first electrical connection point 352, the second electrical connection point 352B and the third electrical connection point 352 〇. However: in other The upper package structure 4 is not limited to a ball grid array package structure, and the package structure 3 can also be stacked: more than one package structure 7, the upper package structure 7 is side by side, such as Figure 13 is a cross-sectional view showing a first embodiment of the stackable package structure of the present invention. The stackable package structure 3 includes a substrate Η, at least - _ der Paste 32 a wafer, a lead frame, a sealant 36, and a plurality of first solder balls 37. The substrate 31 has an upper surface 3U, a lower surface 312, at least one first fresh pad 313, and a plurality of second fresh pads. 314, the first pad 313 and the second pads 314 are located on the upper surface 3 11 〇 the solder 32 is located The first pad 313 of the substrate 31 is disposed on the upper surface 3U of the substrate 31 and electrically connected to the substrate 31. In this embodiment, the wafer is a wire wafer 33, and the wire wafer is The 33 series is electrically connected to the second pad 314 of the substrate 31 through a plurality of wires 331 and is attached to the substrate 31 by an adhesive layer 332. The lead frame 35 is attached to the upper surface 311 of the substrate 31. % includes a plurality of pins 351 and a plurality of electrical connection points 352. In this embodiment, the electrical connection point 352 includes a plurality of first electrical connection points 352A and a plurality of second electrical connection points 352B. However, in other embodiments, the electrical connection points 352 are further The at least one third electrical connection point 352C (FIG. 139983.doc • 13-201101458 15) is included, wherein the first electrical connection points 352A and the second electrical connection points 352B are located on the wire bonding die 33. Directly above, the at least one third electrical connection point 352C is located at a relative position outside the wire bonding die 33. The pins 351 are connected to the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352c), and each pin 351 includes a first portion 3511. a second portion 3512 and a middle portion 3513, the first portion 3511 is electrically connected to the first pad 313 through the solder 32, and the second portion 3512 is connected to the electrical connection point 352 (first electrical connection The portion 352A, the second electrical connection point 352B, and the third electrical connection point 352A are connected to the first portion 3511 and the second portion 3512. Preferably, the lead frame 35 is made of copper. In this embodiment, the first portion 3511 is parallel to the second portion 3512 and has a height difference, and the intermediate portion 3513 has an angle with the first portion 3511 and the second portion 3512, respectively. The foot 351 has two bends, and the second portion 3512 and the middle portion 3513 define a receiving space 353 for accommodating the wire wafer 33. In this embodiment, each two adjacent electrical connections Point 352 (first electrical connection point 352A, second electrical connection point 35 2B and the third electrical connection point 352 (:) have a spacing between each, and each electrical connection point 352 (first electrical connection point 352A, second electrical connection point 352B and third electrical connection point 352C The body 3521 is connected to the second portion 3512 of the pin 351. The plating layer 3522 is located on the body 3521, and the material of the plating layer 3522 can be, but is not limited to, The sealant 36 covers the upper surface 311 of the substrate 31, the solder 32, the 139983.doc 201101458 wire wafer 33 and the lead frame 35' and exposes the electrical connection points 352 (the first electrical property) The connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C). Preferably, the electrical connection point 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the The three electrical connection points 352C) are flush with the upper surface 361 of the encapsulant 36, and the side edges 362 of the encapsulant 36, the side edges 3514 of the pins 351, and the side edges 315 of the substrate 31 are aligned. The first solder balls 37 are located on the lower surface 312 of the substrate 31. Referring again to Figure 11, the stackable package structure of the present invention is shown. A cross-sectional view of an embodiment. The stackable package structure 3 includes a glue body 36, a lead frame 35, a wafer, a substrate 31, at least one solder paste 32, and a plurality of first solder balls 37. The encapsulant 36 has an upper surface 361 (ie, an engagement surface) that exposes a plurality of electrical connection points 352 that include a plurality of first electrical connection points 352A and a plurality of second electrical connection points 352B, and the first electrical connection points 352 are located at the periphery of the second electrical connection points 352B (as shown in FIGS. 8 and 9). That is, the first electrical connection points 352A surround the second electrical connection points 352B. In this embodiment, the first electrical connection points 352A and the second electrical connection points 352B are located directly above the wire bonding die 33. However, in other embodiments, the electrical connection points 352 further include at least one third electrical connection point 352C (FIG. 15). The at least one third electrical connection point 352c is located outside the wire bonding die 3 3 . relative position. In the 16 cases of the real case, 'Every two adjacent electrical connection points are said (the first electrical connection point 3 5 2 A, the first-Ray-μ translation address, the electric-f connection point 352B, and the third electrical connection point 139983 Doc -15- 201101458 352C) has a spacing between each, and each electrical connection point 352 (first electrical connection point 352A, second electrical connection point 352B and third electrical connection point 352C) includes a The body 3521 and a plating layer 3522 are disposed on the body 3521, and the material of the plating layer 3522 can be, but not limited to, nickel gold. Preferably, the first electrical connection points 352 and the second electrical connection points 352B are located in a central region of the upper surface 361 (ie, the bonding surface) and the electrical connection points 352 (first electrical The sexual connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C) are flush with the upper surface 361 (i.e., the bonding surface) of the encapsulant 36. The lead frame 35 is located in the seal body 36. Referring to FIG. 8 and FIG. 9 , the lead frame 35 includes a plurality of pins 351 , the first electrical connection points 352A and the second electrical connection points 352B. Each of the leads 35i includes a first portion 35H, a second portion 3S12, and a middle portion 35n. The second portion 3512 is connected to the electrical connection point (the first electrical connection point 352a and the second electrical connection point). 352B and a third electrical connection point 352, the intermediate portion 3513 is connected to the first portion 35n and the second portion 3512, the second portion 3512 and the intermediate portion 3513 define an accommodation space (5), and the reference The leg 351 includes a plurality of first pins 351A and a plurality of second pins 35iB. The u pins 351A are connected to the first electrical connection points 352a, and the second pins 351B are connected to the second electrical terminals. Preferably, the lead frame 35 is made of copper. In the present embodiment, the meandering portion 3511 is parallel to the second portion 3512 and has a height difference, and the intermediate portion 3513 is respectively The [part 3511 and the second portion 3512 have H such that each - pin 351 has two bends The 139983.doc -16 - 201101458 second portion 3512 and the intermediate portion 3513 define an accommodating space 353. In this embodiment, the second portion 3512 of the pins 351 is connected to the electrical connection. The body 3521. of the point 352 (the first electrical connection point 352A, the second electrical connection point 352b and the second electrical connection point 352C). In addition, each second pin 35 1B passes through two adjacent first The gap between the electrical connection points 352A is located in the accommodating space 353. In the embodiment, the wafer is a wire wafer 33 and is adhered to the substrate ❹ 31 by an adhesive layer 332. The substrate 31 Having an upper surface 311 (ie, a first surface), a lower surface 312 (ie, a second surface), at least one first bonding pad 313, and a plurality of second bonding pads 314, the first bonding pad 313 and the second bonding pads The pad 314 is located on the upper surface 311 (ie, the first surface). The upper surface 311 of the substrate 31 (ie, the first surface) carries the wafer, the lead frame 35, and the first sealing pad of the sealing body 36 and the substrate 31. 313 is electrically connected to the electrical connection points 352 through the solder 32 and the first portion 35 of the pins 351 ( An electrical connection point 352A, a second electrical connection point 352B, and a third electrical connection point 352c). The second bonding pad 314 of the substrate 31 is electrically connected to the wire bonding die 33 through a plurality of wires 33 1 . Preferably, the side 362 of the encapsulant 36, the side 3514 of the pins 351 and the side 315 of the substrate 31 are aligned. The first solder balls are located on the lower surface 312 of the substrate 31 (ie Second surface). Referring to FIG. 12, the stackable package structure 3 further includes at least one upper package structure 4 disposed on an upper surface 361 of the encapsulant (ie, a surface) and electrically connected. Electrical connection point Μ% first electrical 16 connection point 352A, second electrical connection point 352B and third electrical connection point 352C). The upper package structure 4 is a ball grid array package structure (7)... 139983.doc -17· 201101458

Grid Array Package)，其包括複數個外接點（例如：第 球41)，每一外接點(例如：第二銲球41)係對應且電性： 並直接接觸該導線架35之每—電性連接點352(第—電 接點352A、第二電性連接點侧及第三電性連接點 352〇。“ ’在其他應用中’該上封裝結構4係不限定為 -球柵陣列封裝結肖，且該封裝結構3亦可堆疊二個以上 ^上封裝結構7’料上封裝結構7係為並排，如圖^所 示0 ❹Grid Array Package), which includes a plurality of external contacts (eg, the first ball 41), each external contact (eg, the second solder ball 41) is corresponding and electrically: and directly contacts each of the lead frames 35 - electrical The connection point 352 (the first electrical contact 352A, the second electrical connection point side, and the third electrical connection point 352 〇. " 'In other applications' the upper package structure 4 is not limited to - ball grid array package junction Xiao, and the package structure 3 can also be stacked more than two upper package structure 7' material on the package structure 7 is side by side, as shown in FIG.

又參考圖12，顯示本發明半導體封裝結構之剖面示意 圖。該半導體封裝結構6包括—可堆疊式封裝結構及至少 -上封裝結構4。該可堆叠式封裝結構係與本發明可堆疊 式封裝結構3之第-實施例相同。該上封裝結_係位於二 可堆疊式封裝結構3上’且電性連接至該可堆疊式封裝結 構3。 參考圖14，顯示本發明可堆疊式封裝結構之第二實施例 之剖面示意圖。本實施例之可堆疊式封裝結構#第一實 施例之可堆疊式封裝結構3(圖u)大致相同，其中相同之元 件賦予相同之編號。本實施例與第—實施例之不同處在於 該晶片之結構不同。在本實施財1晶片係為-覆晶晶 片34’其包括-上表面341(即背面）、_τ表面342(即主動 面）及複數個凸塊343 ’該等凸塊⑷係位於該下表面⑷（即 主動面），且該覆晶晶>{ 34係透過該等凸塊⑷電性連接至 該基板31之第二銲墊314。 參考圖15 ’顯示本發明可堆疊式封裝結構之第三實施例 139983.doc -18- 201101458 之剖面示意圖。本實施例之可堆疊式封裝結構8與第一實 -施例之可堆疊式封裝結構3(圖11}大致相同，其中相同之元 件賦予相同之編號。本實施例與第一實施例之不同處在於 該封裝結構8之電性連接點352更包括至少一第三電性連接 點352C ,該至少一第三電性連接點352C係位於該打線晶 片33外之相對位置。 參考圖16，顯示本發明可堆疊式封裝結構之第四實施例 ❹ 之剖面示意圖。本實施例之可堆疊式封裝結構9與第一實 施例之可堆疊式封裝結構3(圖11}大致相同，其中相同之元 件賦予相同之編號。本實施例與第一實施例之不同處在於 該封裝結構9更包括一分隔晶片38，其係位於該打線晶片 33上用以支撐該等引腳351。 參考圖1 7，顯示本發明可堆疊式封裝結構之第五實施例 之剖面示意圖。本實施例之可堆疊式封裝結構1〇與第一實 施例之可堆疊式封裝結構3(圖11)大致相同，其中相同之元 〇 件賦予相同之編號。本實施例與第一實施例之不同處在於 該封裝結構10更包括一低模流薄膜（L〇w M〇dules Film)39 ’其係包覆該打線晶片33用以支標該等引腳351。 藉此，該導線架35使該等電性連接點352之分佈符合一 標準記憶體（Standard Memory)之銲球之分佈，而得以堆疊 該標準記憶體於本發明可堆疊式封裝結構3,5之頂端。再 者’該導線架35可避免使用額外之介電層24(圖2)，而減少 本發明可堆疊式封裝結構3,5之總厚度。並且，該導線架 _ 35於該封膠體36之上表面361提供一高線路密集度之接合 139983.doc •19- 201101458 表面’以供堆疊任—種態樣之上封裝結構4。此外，使用 -標準四方形之模具以形成該封膠體36，即可顯露該等電 性連接點352’而不需研發特殊形狀之模具，故可降 造成本。 - 准上述實施例僅為說明本發明之原理及其功效 :::本發明。因此’習於此技術之人士對上述實施例進 Ο 不脫本發明之精神。本發明之權利範圍應 如後述之申請專利範圍所列。 【圖式簡單說明】 之剖面示意 圖1顯示顯示習知第一種可堆疊式封裝結構 圖， 之剖面示意 圖2顯示顯示習知第二種可堆疊式封裝結構 圖， Ο ㈣11顯示本發明可堆疊式封襄結構 之製造方法之示意圖； 圖12顯示本發明可堆疊式封袭結構 上封裝結構之示意圖； 圖13顯示本發明可堆叠式封裝結構 個上封裝結構之示意圖； 圖14顯示本發明可堆疊式封裝社槿 示意圖； 、0再 圖15顯示本發明可堆疊 示意圖； 、裝構之第三實施例之剖面 圖丨6顯示本發明可堆疊 裝”，。構之第四實施例之剖面 之第一實施例 之第一實施例堆疊一 之第一實施例堆疊 二 之第二實施例之剖面 139983.doc •20· 201101458 示意圖；及 圖17顯示本發明可堆疊式封裝結構之第五實施例之剖面 不意圖。 【主要元件符號說明】Referring again to Figure 12, there is shown a cross-sectional schematic view of a semiconductor package structure of the present invention. The semiconductor package structure 6 includes a stackable package structure and at least an upper package structure 4. The stackable package structure is the same as the first embodiment of the stackable package structure 3 of the present invention. The upper package is disposed on the second stackable package structure 3 and electrically connected to the stackable package structure 3. Referring to Figure 14, there is shown a cross-sectional view of a second embodiment of the stackable package structure of the present invention. The stackable package structure 3 of the first embodiment (Fig. u) of the first embodiment is substantially the same, wherein the same elements are given the same reference numerals. The difference between this embodiment and the first embodiment is that the structure of the wafer is different. In the present embodiment, the wafer 1 is a flip chip 34' which includes an upper surface 341 (ie, a back surface), a _τ surface 342 (ie, an active surface), and a plurality of bumps 343 'the bumps (4) are located on the lower surface. (4) (ie, the active surface), and the flip chip > {34 is electrically connected to the second pad 314 of the substrate 31 through the bumps (4). Referring to Figure 15', there is shown a cross-sectional view of a third embodiment of the stackable package structure of the present invention 139983.doc -18- 201101458. The stackable package structure 8 of the present embodiment is substantially the same as the stackable package structure 3 (FIG. 11) of the first embodiment, wherein the same components are given the same numbers. This embodiment is different from the first embodiment. The electrical connection point 352 of the package structure 8 further includes at least a third electrical connection point 352C, and the at least one third electrical connection point 352C is located at a position outside the wire bonding die 33. Referring to FIG. A cross-sectional view of a fourth embodiment of the stackable package structure of the present invention. The stackable package structure 9 of the present embodiment is substantially the same as the stackable package structure 3 of the first embodiment (Fig. 11), wherein the same components The same number is assigned to the first embodiment. The package structure 9 further includes a spacer wafer 38 on the wire bonding die 33 for supporting the pins 351. A cross-sectional view showing a fifth embodiment of the stackable package structure of the present invention. The stackable package structure 1 of the present embodiment is substantially the same as the stackable package structure 3 (FIG. 11) of the first embodiment, wherein the phase The same components are given the same number. The difference between this embodiment and the first embodiment is that the package structure 10 further includes a low-mold film (L〇w M〇杜les Film) 39' which covers the wire wafer. 33 is used to support the pins 351. Thereby, the lead frame 35 allows the distribution of the electrical connection points 352 to conform to the distribution of solder balls of a standard memory, and the standard memory is stacked. At the top of the stackable package structure 3, 5 of the present invention, the lead frame 35 can avoid the use of an additional dielectric layer 24 (Fig. 2), and reduce the total thickness of the stackable package structure 3, 5 of the present invention. Moreover, the lead frame _35 provides a high line density bonding on the upper surface 361 of the encapsulant 36. 139983.doc • 19- 201101458 surface 'for stacking the above-described package structure 4. Further, By using a standard square mold to form the seal body 36, the electrical connection points 352' can be exposed without the need to develop a mold of a special shape, which can be reduced. - The above embodiments are merely illustrative of the present invention. Principles and effects::: The invention. Therefore ' The above embodiments are not inconsistent with the spirit of the present invention. The scope of the present invention should be as described in the following patent application. [Simplified Schematic] FIG. A stackable package structure diagram, a cross-sectional view 2 showing a conventional second stackable package structure diagram, and a fourth diagram showing a manufacturing method of the stackable package structure of the present invention; FIG. 12 shows a stackable type of the present invention. FIG. 13 is a schematic view showing a package structure of a stackable package structure of the present invention; FIG. 14 is a schematic view showing a stackable package structure of the present invention; FIG. 6 is a cross-sectional view of the third embodiment of the apparatus showing the stackable package of the present invention. A first embodiment of a first embodiment of a cross section of a fourth embodiment is stacked with a first embodiment of a second embodiment of a second embodiment of a cross section 139983.doc • 20· 201101458; and FIG. 17 shows the present invention. The cross section of the fifth embodiment of the stacked package structure is not intended. [Main component symbol description]

1 習知第一種可堆疊式封裝結構 2 習知第二種可堆疊式封裝結構 3 本發明可堆疊式封裝結構之第一 實施例 3A 可堆疊式封裝結構 4 上封裝結構 5 本發明可堆疊式封裝結構之第二 實施例 6 本發明半導體封裝結構 7 上封裝結構 8 〇 本發明可堆疊式封裝結構之第三實施例 本發明可堆疊式封裝結構之第四 實施例 10 本發明可堆疊式封裝結構之第五實施例 ll 基板 12 晶片 13 導線 14 封膠體 15 銲球 21 第一基板 22 第一晶片 23 底膠 24 介電層 139983.doc •21 - 2011014581 Conventional First Stackable Package Structure 2 Conventional Second Stackable Package Structure 3 First Embodiment of Stackable Package Structure of the Invention 3A Stackable Package Structure 4 Upper Package Structure 5 The present invention can be stacked Second Embodiment 6 of the present invention The semiconductor package structure 7 The package structure 8 of the present invention The third embodiment of the stackable package structure of the present invention The fourth embodiment of the stackable package structure of the present invention 10 Fifth Embodiment of Package Structure 11 Substrate 12 Wafer 13 Conductor 14 Sealant 15 Solder Ball 21 First Substrate 22 First Wafer 23 Primer 24 Dielectric Layer 139983.doc • 21 - 201101458

25 第二基板 26 導線 27 封膠體 28 鲜球 31 基板 32 銲料 33 打線晶片 34 覆晶晶片 35 導線架 36 封膠體 37 第一銲球 38 分隔晶片 39 低模流薄膜 41 第二銲球 111 第一表面 112 第二表面 113 穿導孔 114 電性連接點 211 第一表面 212 第二表面 221 第一凸塊 251 第一表面 252 第二表面 253 電性連接點 139983.doc -22 20110145825 second substrate 26 wire 27 encapsulant 28 fresh ball 31 substrate 32 solder 33 wire wafer 34 flip chip 35 lead frame 36 sealant 37 first solder ball 38 separation wafer 39 low-mold film 41 second solder ball 111 first Surface 112 second surface 113 through hole 114 electrical connection point 211 first surface 212 second surface 221 first bump 251 first surface 252 second surface 253 electrical connection point 139983.doc -22 201101458

311 上表面 312 下表面 313 第一銲墊 314 第二銲墊 315 側邊 331 導線 332 黏著層 341 上表面 342 下表面 343 凸塊 351 引腳 351A 第一引腳 351B 第二引腳 352 電性連接點 352A 第一電性連接點 352B 第二電性連接點 352C 第三電性連接點 353 容置空間 354 邊框 361 上表面 362 側邊 3511 第一部分 3512 第二部分 3513 中間部分 139983.doc -23- 201101458 3514 側邊 3521 本體 3522 電鍍層 〇311 upper surface 312 lower surface 313 first pad 314 second pad 315 side 331 wire 332 adhesive layer 341 upper surface 342 lower surface 343 bump 351 pin 351A first pin 351B second pin 352 electrical connection Point 352A first electrical connection point 352B second electrical connection point 352C third electrical connection point 353 accommodation space 354 frame 361 upper surface 362 side 3511 first part 3512 second part 3513 middle part 139983.doc -23- 201101458 3514 Side 3521 Body 3522 Plating 〇

139983.doc139983.doc

Claims (1)

201101458 七、申請專利範圍： 1. 一種可堆疊式封裝結構，包括： 基板，具有一上表面、一下表面及至少一第一銲 塾’ δ亥第一鮮墊係位於該上表面； 曰曰片，位於該基板之上表面，且電性連接至該基 -導線架，附著於該基板之上表面，該導線架包括複 〇201101458 VII. Patent application scope: 1. A stackable package structure, comprising: a substrate having an upper surface, a lower surface and at least one first soldering pad; Δ海 first fresh pad is located on the upper surface; Located on the upper surface of the substrate, and electrically connected to the base-conductor, attached to the upper surface of the substrate, the lead frame including the retanning 數個引腳及複數個f性連接點，料51腳連接該等電性 連，點’每一引腳包括一第一部分、一第二部分及一中 間。p分，該第一部分係電性連接該第一銲墊，該第二部 :刀係連接該電性連接點，該中間部分連接該第—部分及 該第二部分’該第二部分及該中間部分^義出一容置处 間以容置該晶片；及 二 -封膠體，包覆該基板之上表面、該晶片及該導線 架，且顯露該等電性連接點。 2.=清求項1之封裝結構，《中該基板更包括複數個第二 銲墊，該等第二銲墊位於該上表面。 3· ^求項2之封裝結構，其中該晶片包括-主動面、_ 背面及複數個凸塊，該等凸塊係位於該主動面，且該晶 4 2透過該等凸塊電性連接至該基板之該等第二銲塾。 月求項2之封裝結構，其中該晶片係透過複數條導線 =性連接至該基板之該等第二録塾，且該 著層附著於該基板。 黏 5 ·如請求項1 > at 士袭結構，其中每二個相鄰之電性連接點 139983.doc 201101458 之間具有一間距。 6.如請求項1之封裝結構，其 體及-雷铲层 '、 電性連接點包括一本 Χ ，該本體連接該引腳之第二部分，且节電 鍍層位於該本體上。 该電 7. 如請求項6之封裝結構，立 金。 ，、Τ该電鍍層之材質係為鎳 8. 如請求項1之封裝結構，其中矽篝f ^ 徊筮一# 再〒該等電性連接點包括複數 Ο Ο 電性連接點及複數個第― 電性遠*㈣第-電性連接點，該等第一 方。··㈣第二電性連接點係位於該晶片之正上 9. 如請求項8之封装 少再-中該等電性連接點更包括至 ^ a u . ^第二電性連接點係位於 該曰曰片外之相對位置。1〇.如請求項 中該等電性i車垃扑也# 訂褒、.·〇構其 、 連接點與該封膠體之一上表面齊平。 月长項1之封裝結構，其中該封 敎側邊及該基板之側邊切齊。 Μ該等引 月长項1之封裝結構，更包括 — Paste)，位於兮*上 鲜枓（Solder 間。）位於該基板之第-銲塾與該引腳之第一部份之 13.如請求们之封袭 該基板之下表面。 更匕括複數個第-銲球，位於 14·如請求们之封裝 访曰H L 尺巴枯刀Ν晶片，其係位於 該日日片上用以支撐該等引腳。 15.如清求項1之封社 、…構，更包括一低模流薄膜（L〇w 139983.doc 201101458 Modules Film) ’其係包覆該晶片用以支撐該等引腳。 16. —種可堆疊式封裝結構之製造方法，包括： ⑷提供一基板’該基板具有-上表面、-下表面及至 少一第一銲墊，該第一銲墊係位於該上表面； ㈨設置-晶片於該基板之上表面，該晶片係電性連接 至該基板；A plurality of pins and a plurality of f-connection points are connected to the electrical connection, and the point 'each pin includes a first portion, a second portion and a middle portion. The first portion is electrically connected to the first pad, the second portion is: the knife is connected to the electrical connection point, the intermediate portion is connected to the first portion and the second portion 'the second portion and the The middle portion defines a receiving space for accommodating the wafer; and a second sealing body covering the upper surface of the substrate, the wafer and the lead frame, and exposing the electrical connection points. 2. = The package structure of claim 1, wherein the substrate further comprises a plurality of second pads, the second pads being located on the upper surface. 3. The package structure of claim 2, wherein the wafer comprises an active surface, a back surface, and a plurality of bumps, wherein the bumps are located on the active surface, and the crystals 4 are electrically connected to the bumps through the bumps The second solder fillets of the substrate. The package structure of claim 2, wherein the wafer is connected to the second recording of the substrate through a plurality of wires, and the layer is attached to the substrate. Sticky 5 · As requested in Item 1 > at the striking structure, where there is a spacing between each two adjacent electrical connection points 139983.doc 201101458. 6. The package structure of claim 1, wherein the body and the shovel layer, the electrical connection point comprises a body, the body is connected to the second portion of the pin, and the energy-saving plating layer is located on the body. The electricity 7. As claimed in item 6, the package structure, the gold. The material of the plating layer is nickel 8. The package structure of claim 1 wherein 矽篝f ^ 徊筮一# and the electrical connection point comprises a plurality of electrical connections and a plurality of ― Electrical far* (4) The first electrical connection point, the first party. (4) The second electrical connection point is located directly above the wafer. 9. If the package of claim 8 is less, the electrical connection point further includes to ^ au. ^ The second electrical connection point is located at the The relative position outside the cymbal. 1〇. In the request item, the electric i car is also 褒 褒, 〇 其 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The package structure of the moon length item 1, wherein the side edges of the seal and the sides of the substrate are aligned.封装 The encapsulation structure of the long term 1 includes - Paste), located on the 兮* 枓 枓 Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol Sol The requester sealed the lower surface of the substrate. In addition, a plurality of first-solder balls are located at the package of the requester. The H L-bar blade is located on the Japanese film to support the pins. 15. The sealing device of claim 1 further comprises a low-mold film (L〇w 139983.doc 201101458 Modules Film) which is coated with the wafer to support the pins. 16. A method of fabricating a stackable package structure, comprising: (4) providing a substrate having: an upper surface, a lower surface, and at least one first bonding pad, the first bonding pad being located on the upper surface; Providing a wafer on an upper surface of the substrate, the wafer being electrically connected to the substrate; ()提供If線架’該導線架包括複數個引腳及複數個 電性連接點，該等引腳連接該等電性連接點，每一 引腳包括一第一部分、一第二部分及一中間部分， 該第二部分係連接該電性連接點，該十間部分連接 該第-部分及該第二部分，該第二部分及該中間部 分定義出一容置空間以容置該晶片； ⑷附著該導線架於該基板之上表面，使每—引腳之第 一部分電性連接該[銲塾，且該晶片位於該容置 空間内；及 該晶片及 〇 ⑷形成一封膝體’以覆蓋該基板之上表面 該導線架，且顯露該等電性連接點。 17·Ϊ =項16之方法’其中該步驟⑷中，該基板更包括複 數個第二銲墊，位於該上表面。 請求項17之方法’其中該步驟(b)中該晶片包括一主 2面、—背面及複數個凸塊’該等凸塊係值於該主動 =該晶片錢過料凸塊電性連接至該基板之該等 ^ 塾。 19.如請求項17之方法 其中該步驟（b)中 該晶片係透過複 139983.doc 201101458 數條導線電性連接至該基板之該等第二銲墊，且該晶片 利用一黏著層附著於該基板。 2〇·如請求項16之方法，其中該步驟（…後，更包括一設置一 分隔晶片於該晶片上之步驟。 Ο() providing an If-Rack] The lead frame includes a plurality of pins and a plurality of electrical connection points, the pins connecting the electrical connection points, each of the pins including a first portion, a second portion, and a a middle portion, the second portion is connected to the electrical connection point, the ten portions are connected to the first portion and the second portion, and the second portion and the intermediate portion define an accommodating space for accommodating the wafer; (4) attaching the lead frame to the upper surface of the substrate, so that the first portion of each pin is electrically connected to the [welding pad, and the wafer is located in the accommodating space; and the wafer and the cymbal (4) form a knee body] The lead frame is covered on the upper surface of the substrate, and the electrical connection points are exposed. 17. The method of item 16 wherein, in the step (4), the substrate further comprises a plurality of second pads on the upper surface. The method of claim 17, wherein the wafer in the step (b) comprises a main surface, a back surface, and a plurality of bumps, wherein the bump values are electrically connected to the active = the wafer money over bump These are the substrates. 19. The method of claim 17, wherein the wafer in the step (b) is electrically connected to the second pads of the substrate through a plurality of wires 139983.doc 201101458, and the wafer is attached to the substrate by an adhesive layer The substrate. 2. The method of claim 16, wherein the step (... further comprises the step of providing a separate wafer on the wafer. 21.如請求項16之方法，其中該步驟（1?)後，更包括一形成一 低模流薄膜（Low Modules Film)以包覆該晶片之步驟， 該低模流薄膜係利用喷流（Dispensing)或印刷（printing) 方式形成。 22·如凊求項16之方法’其中該步驟⑷後，更包括—提供一 膠帶以黏著該等電性連接點及該等引腳之第二部分之步 驟，該步驟⑷後，更包括一移除該膠帶之步驟。 23.如凊求項16之方法，其中該步驟⑷中，每二個相鄰之電 性連接點之間具有一間距。 24.如請求項16之方法，苴中 /、甲这步驟（C)中，母一電性連接點 包括一本體及一電鍵層，兮太# ^ 这本體連接該引腳之第二部 分’且該電鍍層位於該本體上。 A如請求項24之方法，其中該步驟⑷中，該電錄層之材質 係為鎳金。 ^求項16之錢，其巾該㈣⑷巾，料電性連接點 數個第一電性連接點及複數個第二電性連接點， ^第-電性連接點及該等第二電性連接點係位 片之正上方。 27_如請求項26之方法，豆中 笛一^ 〃中料電性連接點更包括至少一 第二電性連接點，該至少一第二 電性連接點係位於該晶 139983.doc 201101458 片外之相對位置。 該等電性連接點 28.如請求項16之方法，其中該步驟（c)中， 與該封膠體之一上表面齊平。 29·如請求項16之方法，其中該步驟⑷後，更包括一設置至 少一銲料（Solder Paste)於該基板之第—鲜塾上之步驟， 該步驟⑷中，料線㈣制表面黏著技術⑽咖 M_ Teehn°lGgy，SMT)透過該銲料附著於該基板之上 表面。 ❹ 3 0.如請求項29之方法，装φ兮經M总心丨m 具T該銲枓係利用沾錫（Dipping Solder Paste)或印刷製程設置於該基板之第一銲墊上。 31.如請求項16之方法，其中該步驟⑷後，更包括一進行單 體化（Singulation)製程，以形成複數個可堆疊式封裝結 構之步驟。 口 32.如請求項31之方法’其中該單體化製程係為切割或衝壓 製程。 〇 33.如4求項32之方法，其中該封膠體之侧邊該等引腳之 側邊及該基板之側邊切齊。 34.如請求項16之方法，其中該步驟⑷後，更包括一形成複 數個第一銲球於該基板之下表面之步驟。 35·如凊求項16之方法，其中該步驟⑷後，更包括—堆疊至 少一上封裝結構之步驟。 • 36.如凊求項35之方法，其中係堆疊至少二個上封裝結構， 該等上封裝結構係為並排。 37.如請求項35之方法，其中該上封裝結構係為—球拇陣列 139983.doc 201101458 封裝結構（Ball Grid Array Package)。 月求項35之方法，其中該上封裝結構包括複數個第二 辉求母一第二銲球係對應且電性連接該導線架之每一 電性連接點。 39‘如請求項38之方法’其中每一第二銲球係直接接觸該導 線架之每一電性連接點。 40.種半導體封裝結構，包括： 0 一可堆疊式封裝結構，包括： 一基板’具有一上表面、一下表面及至少一第一銲 塾’該第一銲墊係位於該上表面； 曰曰片，位於該基板之上表面，且電性連接至該美 板； & 一導線架，附著於該基板之上表面，該導線架包括 複數個引腳及複數個電性連接點，該等引腳連接該等 電性連接點，每一引腳包括一第一部分、一第二部分 〇 及一中間部分，該第一部分係電性連接該第一銲墊， 該第二部分係連接該電性連接點，該中間部分連接該 第一部分及該第二部分，該第二部分及該中間部分定 義出一容置空間以容置該晶片；及 一封膠體，包覆該基板之上表面、該晶片及該導線 架’且顯露該等電性連接點；及 至少一上封裝結構，位於該可堆疊式封裝結構上，且 電性連接至該可堆疊式封裝結構。 41.如請求項40之封裝結構，其中該基板更包括複數個第二 139983.doc -6 - 201101458 銲墊，該等第二銲墊位於該上表面。 .42.如請求項41之封裝結構，其中該晶片包括—主動面、一 背面及複數個凸塊，該等凸塊係位於該主動面，且該晶 片係透過該等凸塊電性連接至該基板之該等第二鲜塾。a 43·如請求項41之封裝結構，其中該晶片係透過複數條導線 ，性連接至該基板之該等第：鲜墊，且該晶片利用一黏 著層附著於該基板。 44·如請求項4〇之封農結構，其中每二個相鄰之電性連接點 之間具有一間距。 45·如請求項4G之封裝結構，其中每—電性連接點包括一本 體及一電鍍層，該本體連接該引腳之第二部分，且該電 鑛層位於該本體上。 46.如請求項45之封裝結構’其中該電鑛層之材質係為鎮 金。 47·如請求項40之封裝結構，其中該等電性連接點包括複數 〇 個第一電性連接點及複數個第二電性連接點，該等第一 電性連接點及該等第二電性連接點係位於該晶片之正上 方。 48·如請求項47之封裝結構，其中該等電性連接點更包括至 少一第三電性連接點，該至少一第三電性連接點係位於 該晶片外之相對位置。 49.如請求項40之封裝結構，其中該等電性連接點與該封膠 體之一上表面齊平。 5〇·如請求項40之封裝結構，其中該封膠體之側邊、該等引 139983.doc 201101458 腳之側邊及該基板之側邊切齊。 51. 如請求項4〇之封裝結構，其中該可堆疊式封裝結構更包 括至少一銲料（Solder Paste)，位於該基板之第一銲墊與 該引腳之第一部分之間。 52. 如請求項4〇之封裝結構，其中該可堆疊式封裴結構更包 括複數個第一銲球，位於該基板之下表面。21. The method of claim 16, wherein after the step (1?), further comprising the step of forming a low mold film to coat the wafer, the low mold film utilizing a jet stream ( Dispensing) or printing (printing). 22) The method of claim 16, wherein after the step (4), further comprising: providing a tape to adhere the electrical connection point and the second portion of the pins, after the step (4), further comprising a The step of removing the tape. 23. The method of claim 16, wherein in the step (4), there is a spacing between each of the two adjacent electrical connection points. 24. The method of claim 16, wherein in the step (C), the mother-electrical connection point comprises a body and a key layer, and the body is connected to the second part of the pin. And the plating layer is on the body. A. The method of claim 24, wherein in the step (4), the material of the electrographic layer is nickel gold. ^ Claim 16 money, the towel (4) (4) towel, the electrical connection point number of the first electrical connection point and the plurality of second electrical connection points, ^ the first electrical connection point and the second electrical The connection point is directly above the slice. 27_ The method of claim 26, wherein the electrical connection point of the hopper is further comprising at least one second electrical connection point, wherein the at least one second electrical connection point is located at the 139983.doc 201101458 piece Relative position outside. The method of claim 16, wherein the step (c) is flush with the upper surface of one of the encapsulants. The method of claim 16, wherein after the step (4), the method further comprises the step of: setting at least one solder (Solder Paste) on the first layer of the substrate, wherein the step (4), the surface line (4) surface adhesion technology (10) Coffee M_Teehn°lGgy, SMT) is attached to the upper surface of the substrate through the solder. ❹ 3 0. According to the method of claim 29, the φ 兮 M M M M 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 31. The method of claim 16, wherein the step (4) further comprises the step of performing a singulation process to form a plurality of stackable package structures. Port 32. The method of claim 31 wherein the singulation process is a cutting or stamping process. The method of claim 32, wherein the side edges of the pins of the encapsulant are aligned with the sides of the substrate. 34. The method of claim 16, wherein the step (4) further comprises the step of forming a plurality of first solder balls on a lower surface of the substrate. 35. The method of claim 16, wherein the step (4) further comprises the step of stacking at least one of the package structures. 36. The method of claim 35, wherein at least two upper package structures are stacked, the upper package structures being side by side. 37. The method of claim 35, wherein the upper package structure is a ball Array 139 983.doc 201101458 Package Array Package. The method of claim 35, wherein the upper package structure comprises a plurality of second and second solder balls corresponding to each other and electrically connected to each of the electrical connection points of the lead frame. 39 'A method of claim 38, wherein each of the second solder balls is in direct contact with each electrical connection point of the lead frame. 40. A semiconductor package structure, comprising: a stackable package structure, comprising: a substrate having an upper surface, a lower surface, and at least one first soldering pad; the first bonding pad is located on the upper surface; a sheet on the upper surface of the substrate and electrically connected to the sheet; & a lead frame attached to the upper surface of the substrate, the lead frame comprising a plurality of pins and a plurality of electrical connection points, Pins are connected to the electrical connection points, each of the pins includes a first portion, a second portion, and a middle portion, the first portion is electrically connected to the first pad, and the second portion is connected to the electricity a connecting portion, the intermediate portion connecting the first portion and the second portion, the second portion and the intermediate portion defining an accommodating space for accommodating the wafer; and a gel covering the upper surface of the substrate, And the at least one upper package structure is disposed on the stackable package structure and electrically connected to the stackable package structure. 41. The package of claim 40, wherein the substrate further comprises a plurality of second 139983.doc -6 - 201101458 pads, the second pads being located on the upper surface. The package structure of claim 41, wherein the wafer comprises an active surface, a back surface and a plurality of bumps, the bumps are located on the active surface, and the wafer is electrically connected to the bumps through the bumps The second fresh mash of the substrate. The package structure of claim 41, wherein the wafer is connected to the first: fresh pads of the substrate through a plurality of wires, and the wafer is attached to the substrate by an adhesive layer. 44. The enclosure structure of claim 4, wherein each of the two adjacent electrical connection points has a spacing therebetween. 45. The package structure of claim 4, wherein each of the electrical connection points comprises a body and a plating layer, the body is coupled to the second portion of the pin, and the layer of the ore is located on the body. 46. The package structure of claim 45 wherein the material of the electroderaline layer is a gold alloy. 47. The package structure of claim 40, wherein the electrical connection points comprise a plurality of first electrical connection points and a plurality of second electrical connection points, the first electrical connection points and the The two electrical connection points are located directly above the wafer. The package structure of claim 47, wherein the electrical connection points further comprise at least one third electrical connection point, the at least one third electrical connection point being located at a relative position outside the wafer. 49. The package of claim 40, wherein the electrical connection points are flush with an upper surface of the encapsulant. 5. The package structure of claim 40, wherein the sides of the encapsulant, the sides of the legs 139 983.doc 201101458, and the sides of the substrate are aligned. 51. The package structure of claim 4, wherein the stackable package structure further comprises at least one solder (Solder Paste) between the first pad of the substrate and the first portion of the pin. 52. The package structure of claim 4, wherein the stackable package further comprises a plurality of first solder balls on a lower surface of the substrate. 53·如請求項40之封裝結構，其中該可堆疊式封裝結構更包 括一分隔晶片，其係位於該晶片上用以支撐該等引腳。 54. 如請求項40之封裝結構，其中該可堆疊式封裝結構更包 括低模流薄膜（Low Modules Film)，其係包覆兮曰片 用以支撐該等引腳。 55. 如請求項40之封裝結構，係包括至少二個上封裝結構， 該等上封裝結構係為並排。 56. 如請求項4G之封裝結構，其中該上封裝結構係為-球栅 陣列封裝結構（Ball Grid Array Package)。 57_如請求項4G之封裝結構，其中該上封I結構包括複數個 第二銲球，每一第二銲球係對應且電性連接該導線架之 每一電性連接點。 第二銲球係直接接觸 58·如請求項57之封裝結構，其中每一 該導線架之每一電性連接點。 59. —種可堆疊式封裝結構’包括： -封膠體，具有一接合表面，該接合表面顯露複數個 電性連接點，料電性連接點包括複數個第—電性 點及複數個第二電性連接點，且該等第— 电性連接點位 139983.doc 201101458 於該等第二電性連接點之外圍； • —導線架’位於該封膠體内’該導線架包括複數個引 腳及該等電性連接點，每一引腳包括一第一部分、一第 -部分及-中間部分’該第二部分係連接該電性連接 點，該中間部分連接該第-部分及該第二部分，該第二 部分及該中間部分定義出—容置空間，且該等引腳包括 複數個第-㈣及複數個第H該等第—引腳連接 該等[電性連接點，該等第二㈣連接該等第二電性 連接點； 一晶片，位於該容置空間内；及 一基板，具有一第一表面、一帛三表面及至少一第一 銲墊，該第一銲墊係位於該第一表面，該基板之第一表 面係用以承載該晶片、該導線架及該封膠體，該晶片電 性連接至該基板，且該基板之第一銲墊透過該等引腳之 第一部分電性連接至該等電性連接點。 〇 60·如請求項59之封裝結構，其中該基板更包括複數個第二 銲塾’該等第二銲墊位於該第一表面。 61. 如請求項60之封裝結構’其中該晶片包括一主動面、一 背面及複數個凸塊，該等凸塊係位於該主動面，且該晶 片係透過該等凸塊電性連接至該基板之該等第二銲墊。 62. 如請求項60之封裝結構，其中該晶片係透過複數條導線 電性連接至該基板之該等第二銲墊，且該晶片利用一黏 著層附著於該基板。 63. 如請求項59之封裝結構，其中每二個相鄰之電性連接點 139983.doc 201101458 之間具有一間距。 電性連接點包括一本 之第二部分，且該電 64.如請求項59之封裝結構，其中每一 體及一電鍍層，該本體連接該引腳 鑛層位於該本體上。 65.如晴求項64之封裝結構 金。 其中該電鍍層之材質係為鎳 〇 〇 6=請求項59之封裝結構，其中該等第—電性連接點及該 等第二電性連接點係位於該晶片之正上方。 67.如請求項66之封裝結構’其中該等電性連接點更包括至 少一第三電性連接點，該至少—第三電性連接點係位於 該晶片外之相對位置。 如明求項59之封裝結構，其中該等電性連接點與該封膠 體之接合表面齊平。 69·如請求項59之封裝結構，其中該封膠體之側邊、該等引 腳之側邊及該基板之侧邊切齊。 7〇.如請求項59之封裝結構，更包括至少-輝料(S〇lder ’位於該基板之第一銲墊與該引腳之第一部分之 間0 71_如請求物之封裝結構，更包括複數㈣—銲球，位於 該基板之第二表面。 、 2求項59之封裝結構’其中該等電性連接點係位於該 接口表面之中央區域。 73.^求項59之封襄結構，其中每―第二引腳係穿過二個 相鄰之第-電性連接點之間隙。 139983.doc 201101458 74. 如請求項59之封裝結 j曰Ημ+ 更包括一分隔晶片，其係位於 該日日片上用以支撐該等5丨腳。 75. 如請求項59之封裝結 M〇dUles FiIm)，其 更匕括一低模流薄膜(L- …、覆該阳片用以支撐該等引腳。 76. 如睛求項59之封裝結 f料姑“ 更包括至少—上封裝結構，配 置於該接&表面’且電性連㈣等·連接點。 77. 如請求項76之封裝結 Ο 再/、中係堆疊至少二個上封裝結 構，該等上封裝結構係為並排。 78. 如請求項76之封裝結構，其中該上封裝結構包括複數個 外接點’每一外接點係對應且電性連接每一電性連接 點0 79.如明求項76之封裝結構，其中該上封裝結構係為 一球栅 陣列封裝結構（Bau Grid Array Package)。 8〇.如請^項76之封裝結構，其中該上封裝結構包括複數個 ，二銲球，每—第：銲球係對應且電性連接該導線架之 〇 每一電性連接點。 月求項80之肖裝結構，纟中每一第二鲜球係直接接觸 該導線架之每一電性連接點。 139983.doc53. The package structure of claim 40, wherein the stackable package structure further comprises a spacer wafer on the wafer for supporting the pins. 54. The package structure of claim 40, wherein the stackable package structure further comprises a low mold film (Low Modules Film) that is coated with a die to support the pins. 55. The package structure of claim 40, comprising at least two upper package structures, the upper package structures being side by side. 56. The package structure of claim 4, wherein the upper package structure is a Ball Grid Array Package. 57. The package structure of claim 4, wherein the upper I structure comprises a plurality of second solder balls, each of the second solder balls corresponding to and electrically connected to each electrical connection point of the lead frame. The second solder ball is in direct contact with the package structure of claim 57, wherein each electrical connection point of each of the lead frames. 59. A stackable package structure comprising: a sealant having a joint surface exposing a plurality of electrical connection points, the electrical connection point comprising a plurality of first electrical points and a plurality of second Electrical connection points, and the first electrical connection points 139983.doc 201101458 are on the periphery of the second electrical connection points; • the lead frame 'is located in the sealant body'. The lead frame includes a plurality of pins And the electrical connection points, each of the pins includes a first portion, a first portion, and an intermediate portion. The second portion is connected to the electrical connection point, and the intermediate portion is connected to the first portion and the second portion a portion, the second portion and the intermediate portion define an accommodating space, and the pins include a plurality of - (4) and a plurality of Hths - the pin-connecting the [electrical connection points, etc. The second (four) is connected to the second electrical connection points; a wafer is located in the accommodating space; and a substrate having a first surface, a third surface, and at least one first bonding pad, the first bonding pad Located on the first surface, the substrate a surface is used to carry the wafer, the lead frame and the encapsulant, the wafer is electrically connected to the substrate, and the first pad of the substrate is electrically connected to the first portion through the first portion of the pins Junction. The package structure of claim 59, wherein the substrate further comprises a plurality of second solder pads' such second pads are located on the first surface. 61. The package structure of claim 60, wherein the wafer includes an active surface, a back surface, and a plurality of bumps, the bumps are located on the active surface, and the wafer is electrically connected to the wafer through the bumps The second pads of the substrate. 62. The package structure of claim 60, wherein the wafer is electrically connected to the second pads of the substrate through a plurality of wires, and the wafer is attached to the substrate by an adhesive layer. 63. The package structure of claim 59, wherein there is a spacing between each two adjacent electrical connection points 139983.doc 201101458. The electrical connection point includes a second portion of the package, and the electrical package is the package structure of claim 59, wherein each body and a plating layer, the body connecting the pin ore layer is located on the body. 65. The package structure of the claim 64 is gold. The material of the plating layer is a package structure of nickel 〇 = 6 = claim 59, wherein the first electrical connection points and the second electrical connection points are directly above the wafer. 67. The package structure of claim 66 wherein the electrical connection points further comprise at least a third electrical connection point, the at least - third electrical connection point being located at a relative location outside the wafer. The package structure of claim 59, wherein the electrical connection points are flush with the bonding surface of the encapsulant. 69. The package structure of claim 59, wherein the sides of the encapsulant, the sides of the pins, and the sides of the substrate are aligned. 7. The package structure of claim 59, further comprising at least - a phosphor (S〇lder ' between the first pad of the substrate and the first portion of the pin 0 71_ as claimed in the package structure, Including a plurality (four)—a solder ball, located on a second surface of the substrate. 2, a package structure of the item 59, wherein the electrical connection points are located in a central region of the interface surface. 73. Each of the "second" leads passes through the gap between two adjacent electrical-electrical connection points. 139983.doc 201101458 74. The package junction j曰Ημ+ of claim 59 further includes a separate wafer, It is located on the Japanese film to support the 5 feet. 75. The package of the item 59, M〇dUles FiIm), further comprises a low-mold film (L- ..., covering the film for supporting These pins are 76. If the package of the item 59 is required to include at least the upper package structure, the surface is connected to the surface, and the electrical connection (four), etc. is connected. 77. The package structure of 76 is further stacked in at least two upper package structures, and the upper package structure is 78. The package structure of claim 76, wherein the upper package structure comprises a plurality of external contacts 'each external contact point corresponding to each other and electrically connected to each electrical connection point 0. 79. The upper package structure is a ball grid array package (Bau Grid Array Package). The package structure of the item 76, wherein the upper package structure comprises a plurality of, two solder balls, each - the first: The ball system corresponds to and is electrically connected to each electrical connection point of the lead frame. In the schematic structure of the moon item 80, each of the second fresh balls in the cymbal directly contacts each electrical connection point of the lead frame. 139983.doc
TW98121299A 2009-06-25 2009-06-25 Stackable package and method for making the same and semiconductor package TWI389296B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120241935A1 (en) * 2011-03-24 2012-09-27 Chipmos Technologies Inc. Package-on-package structure
CN102751267A (en) * 2012-05-28 2012-10-24 日月光半导体制造股份有限公司 Semiconductor packaging structure for stacking and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120241935A1 (en) * 2011-03-24 2012-09-27 Chipmos Technologies Inc. Package-on-package structure
CN102751267A (en) * 2012-05-28 2012-10-24 日月光半导体制造股份有限公司 Semiconductor packaging structure for stacking and manufacturing method thereof

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