TW201216416A - Semiconductor package with reinforced base - Google Patents

Semiconductor package with reinforced base Download PDF

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Publication number
TW201216416A
TW201216416A TW099134806A TW99134806A TW201216416A TW 201216416 A TW201216416 A TW 201216416A TW 099134806 A TW099134806 A TW 099134806A TW 99134806 A TW99134806 A TW 99134806A TW 201216416 A TW201216416 A TW 201216416A
Authority
TW
Taiwan
Prior art keywords
wafer
base
semiconductor package
package structure
reinforced
Prior art date
Application number
TW099134806A
Other languages
Chinese (zh)
Other versions
TWI431728B (en
Inventor
Hui-Chang Chen
Original Assignee
Powertech Technology Inc
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Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW099134806A priority Critical patent/TWI431728B/en
Publication of TW201216416A publication Critical patent/TW201216416A/en
Application granted granted Critical
Publication of TWI431728B publication Critical patent/TWI431728B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

Disclosed is a semiconductor package with reinforced base comprising a leadframe, a chip and an encapsulant. A chip tabling fillister is formed within a chip base of the leadfiame and a positioning grille is formed within the bottom of the chip tabling fillister. A concave-convex slot is formed within a backside of the chip with a shape complementing the positioning grille. The chip is lodged and fixed in the chip tabling fillister without adhesive. The encapsulant encapsulates the chip and combines with the chip base as a whole. Accordingly, there can be had stronger bonding force between the chip and the chip base of the leadframe to save die bonding process, and to reduce whole package height.

Description

201216416 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置’特別係有關於一種具強 化式基座之半導體封裝構造。 【先前技術】 現今半導體產業中’在晶圓之積體電路製作完成之 後’由晶圓切割而成的若干晶片係可結合至—晶片承載 器（carrier)上’其可為一導線架或一印刷電路板，並且利 •用打線（wire bonding)或覆晶接合（fiip chip b〇nding)之方 式電性連接晶片與晶片承載器’再進行封膠步驟以構成 一半導體封裝構造。其中，以導線架作為晶片承載器之 半導體封裝構造之型態與種類繁多，例如：QFp封裝 (quad flat package)、QFN 封裝（qUad flat non_leaded package)、SOP 封裝（small outline package)或 DIP 封裝 (dual in-line package)等。 如第1圖所示’一種習知為QFN型態之半導體封裝 鲁 構造1〇〇係於一導線架110之中央位置設有一金屬材質 且面積大於晶片之晶片基座111，以作為該導線架u 〇 用以承載一晶片120之部位。在設置該晶片120至該導 線架110時，通常係採用傳統的黏晶（die bonding)製程 預先塗佈一黏著膠170於該晶片基座111上，再將該晶 片1 20之背面1 2 1貼附至該晶片基座111上，之後再以 烘烤固化該黏著膠1 70之方式結合該晶片1 20與該導線 架110之該晶片基座111β 一般而言，該黏著膠17〇係 201216416 選用熱固性的環氧樹脂（epoxy)，在晶片剛放置之時，該 黏者膠170尚未完全固化而呈現膠稍態。應在該晶片基 座111之周邊須先設置一擋膠環槽115，其係為環狀凹 槽型態且環繞設置於該晶片基座111上之該晶片12〇與 該黏著膠170，當該黏著膠170受到該晶片120擠壓後 朝向四周溢流而出時，藉由該擋膠環槽11 5阻絕溢出的 黏著膠繼續向外擴散而汙染至該導線架丨丨〇，甚至影響 後續打線製程之進行。此外’該半導體封裝構造丨〇〇係 春 以打線方式形成複數個銲線14〇，以電性連接該晶片】2〇 與該導線架110之引腳112。之後，形成一封膠體13〇 並與該導線架11 0結合，以密封該晶片丨2〇、該些銲線 140與部分之該些引腳112。201216416 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device', and particularly relates to a semiconductor package structure having an enhanced susceptor. [Prior Art] In the semiconductor industry today, 'after wafer fabrication of integrated circuits is completed, 'a number of wafers cut from wafers can be bonded to a wafer carrier' which can be a lead frame or a The printed circuit board is electrically connected to the wafer carrier by wire bonding or flip chip bonding to perform a sealing step to form a semiconductor package structure. Among them, there are many types of semiconductor package structures using lead frames as wafer carriers, such as QFp package, qFad flat non-leaded package, small outline package or DIP package ( Dual in-line package). As shown in FIG. 1 , a semiconductor package of the QFN type is provided with a metal material and a wafer base 111 having a larger area than the wafer at the center of a lead frame 110 as the lead frame. u is used to carry a portion of a wafer 120. When the wafer 120 is disposed on the lead frame 110, a conventional adhesive bonding process is used to pre-coat an adhesive 170 on the wafer base 111, and then the back surface of the wafer 1 20 is 1 2 1 Attached to the wafer base 111, and then bonded to the wafer 110 and the wafer base 111 of the lead frame 110 by baking and curing the adhesive 110. Generally, the adhesive 17 is 201216416. A thermosetting epoxy resin is used, and when the wafer is just placed, the adhesive 170 is not fully cured and is in a gel state. A gap ring 115 should be disposed at the periphery of the wafer base 111, which is an annular groove type and surrounds the wafer 12 and the adhesive 170 disposed on the wafer base 111. When the adhesive tape 170 is squeezed out of the wafer 120 and overflows toward the periphery, the adhesive ring groove 11 prevents the overflow adhesive from continuing to spread out to contaminate the lead frame, and even affects the subsequent The line process is carried out. In addition, the semiconductor package structure is formed by a plurality of bonding wires 14 打 in a wire bonding manner to electrically connect the chip to the pin 112 of the lead frame 110. Thereafter, a colloid 13 形成 is formed and bonded to the lead frame 110 to seal the wafer 丨 2 , the bonding wires 140 and a portion of the leads 112 .

Si 由上可知，傳統的半導體封裝構造在黏晶製程時須使 用黏者膠1 7 0 ’以期能將該晶片1 2 0黏著固定至該導線 架110之該晶片基座m，其中除了難以避免上述溢膠 φ 之情況發生外，亦必須考量到使用該黏著膠1 70之材料 成本問題。並且，由於該晶片120本身已具有一定厚度， 加上該黏著膠170之厚度，故整體的封裝高度有一最低 要求，同時該些銲線14〇必須要有一克服晶片高度差之 打線距離，導致金線用量增加。此外，該封膠體丨3 〇係 完全包覆該晶片120,並且該黏著膠17〇會造成在該晶 片120與該晶片基座丨丨丨之間的熱阻，降低了熱量由該 晶片120傳遞至該晶片基座lu之傳導速度，故當該晶 片120運作時於該封膠體13〇内部所產生之熱量無法有 4 201216416 效地發散至外界’因而無法提供良好的散熱特性 【發明内容】 有赛於此，本發明之主要目的係在於提供—種 式基座之半導體封裝構造， 社人七、，、 乃興导踝系之間有較強的 、’〇 〇 ，以省略黏晶製程之黏著膠塗施與烘烤固化等作 業0 之It can be seen from the above that the conventional semiconductor package structure must use the adhesive to be fixed to the wafer base m of the lead frame 110 in the die bonding process, in addition to being difficult to avoid. In addition to the above-mentioned overflow φ, the material cost of using the adhesive 703 must also be considered. Moreover, since the wafer 120 itself has a certain thickness, and the thickness of the adhesive 170 is added, the overall package height has a minimum requirement, and the bonding wires 14 must have a wire bonding distance that overcomes the height difference of the wafer, resulting in gold. Line usage increases. In addition, the encapsulant 丨3 完全 completely covers the wafer 120, and the adhesive 17 〇 causes thermal resistance between the wafer 120 and the wafer pedestal, and heat is transferred from the wafer 120 The conduction speed to the wafer base lu, so that the heat generated inside the sealant 13 when the wafer 120 is in operation cannot be effectively radiated to the outside world, thus failing to provide good heat dissipation characteristics. In this regard, the main object of the present invention is to provide a semiconductor package structure of a type of pedestal, and there is a strong "〇〇" between the members of the company, and the 兴 〇〇 〇〇 省略 省略 省略 省略 省略Adhesive application and baking curing work

本發明之次一目的係在於提供一種具強化式基座 半導體封裴構造’其晶片背面呈現被支撐之裸空狀態 以具有較佳的散熱特性與結合力。 本發明之再一 半導體封裝構造， 向度與封膠體用量 量。 目的係在於提供一種具強化式基座之 可省略黏著膠，進而降低整體的封裝 ’更可縮短打線距離，以減少金線用 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示—種具強化式基座之半導體封 裝構造，主要包含-導線架、-晶片與-封膠體。該導 線架係具有一晶片基座與複數個引腳，該晶片基座係形 成有一晶片嵌合槽以及一形成於該晶片嵌合槽底部之定 位格柵。該晶片係設於該晶片基座上，該晶片之一背面 係形成有複數個與該定位格栅形狀互補之凹凸溝槽，以 使該晶片之至少一部位以無黏著膠方式卡合固定於該晶 1基座之該晶片嵌合槽内。該封膠體係包覆該晶片與部 分之該些引腳並結合該晶片基座為一體。 本發月的目的及解決其技術問題還可採用以下技術[s] 5 201216416 措施進一步實現。 在前述之具強化式基座之半導體封裝構造中，該定位 格柵係可包含複數個呈平行排列且貫穿至該晶片基座之 一下表面之槽孔。 在引述之具強化式基座之半導體封裝構造中，該些槽 孔係可為雷射切割孔。 在前述之具強化式基座之半導體封裝構造中，該晶片 基座之該下表面與該晶片之該凹凸溝槽之凸起表面係可 籲外露於該封膠體之外。 在前述之具強化式基座之半導體封裝構造中，該凹凸 溝槽係可為在晶圓階段以切割方式形成之立體圖案。 在前述之具強化式基座之半導體封裝構造中，其係為 無外弓丨腳式封装，其中該些引腳之下表面亦外露於該封 膠體之外。 在前述之具強化式基座之半導體封裝構造中，可另包 φ 含複數個第一銲線，係電性連接該晶片在其主動面之複 數個銲墊至該導線架之該些引腳。 在前述之具強化式基座之半導體封裝構造中，可另包 含至少一第二銲線，係電性連接該晶片在其主動面之— 輝塾至該導線架之該晶片基座。 在前述之具強化式基座之半導體封裝構造中，可另包 含—金屬接合層，係至少形成於該晶片嵌合槽内之該定 位格柵之表面。 在前述之具強化式基座之半導體封裝構造中，該金屬 201216416 接合層係可更延伸至該晶片基座在該晶片嵌合槽之外之 周邊表面，以供該第二銲線之接合。 由以上技術方案可以看出’本發明之具強化式基座之 半導體封裝構造，具有以下優點與功效： 一、 可藉由晶片至少局部嵌埋於導線架之晶片基座以及 曰曰片基座之定位格栅與晶片背面之凹凸溝槽兩者形 狀互補之特定組合關係作為其中之一技術手段，由 於晶片嵌埋於晶片基座時同時凹凸溝槽亦卡入晶片 基座之定位格柵，故使晶片能以無黏著膠方式卡固 於晶片基座之晶片嵌合槽内。因此，晶片與導線架 之間有較強的結合力，以省略黏晶製程之黏著膠塗 施與烘烤固化等作業。 二、 可藉由晶片基座之^位格柵與晶片f面之凹凸溝槽 兩者形狀互補以及定位格柵由多㈤貫穿晶片基座之 槽孔所組成之特定組合關係作為其中之一技術手 由於晶片者面之凹凸溝槽係可嵌入至晶片基座 之定位格柵之槽孔内，而使晶片之凹凸溝槽之巧起 表面能夠外露於封膠體之外，故使得晶片背面呈現 被支撐之裸空狀離，以且古私 L以具有較佳的散熱特性與結合 力。 可藉由晶片至少局部後埋於道 丨敢埋於導線架之晶片基座以及 :片基座之定位格栅與晶片背面之凹凸溝槽兩者形 狀互補之之特定組合關係作為其中之一技術手段， 晶片係^㈣膠方式^^至晶片基座之晶 7 201216416 嵌口槽内可省略以往黏著膠之厚度並降低晶片突 出於曰曰片基座之呵度。因此，可降低整體的封裝高 度與封膠體用量’更縮短打線距離’以減少金線用 量。 【實施方式】 以下將配合所附圖不詳細說明本發明之實施例，然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計’詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種具強化式基座之 半導體封裝構造舉例說明於第2圖之截面示意圖。該具 • 強化式基座之半導體封褒構造200係包含一導線架 210、一晶片220以及—封膠體23〇。 清參閱第2圖所示’並配合參酌第3A與3B圖，該 ^線架21(>係具有—晶片基座211與複數個引腳212。 詳細而吕’該導線架21〇係作為傳輸積體電路（integrated circim，1C)内之電子元件功能至外部之金屬載板，通常 是利用化予钱刻或機械沖壓方式由一金屬片製出該晶片 基座211與該些弓1聊212。其中，該晶片基座211係形 成有一晶片嵌合槽213以及一形成於該晶片嵌合槽213[s] 8 201216416A second object of the present invention is to provide a reinforced susceptor semiconductor package structure in which the back side of the wafer exhibits a supported bare state for better heat dissipation characteristics and bonding. Still another semiconductor package construction of the present invention, the degree of orientation and the amount of sealant used. The object of the present invention is to provide an reinforced base which can omit the adhesive, thereby reducing the overall package, and the wire length can be shortened to reduce the gold wire. The purpose of the present invention and solving the technical problem are achieved by the following technical solutions. . The present invention discloses a semiconductor package structure having a reinforced base, which mainly comprises a lead frame, a wafer and a sealant. The wire frame has a wafer base and a plurality of pins, and the wafer base is formed with a wafer fitting groove and a positioning grid formed at the bottom of the wafer fitting groove. The chip is disposed on the wafer base, and a back surface of the wafer is formed with a plurality of concave and convex grooves complementary to the shape of the positioning grid, so that at least one portion of the wafer is locked and fixed by adhesive-free bonding. The wafer 1 is in the wafer fitting groove of the susceptor. The encapsulation system encapsulates the wafer and portions of the pins and is integrated with the wafer pedestal. The purpose of this month and the resolution of its technical problems can be further achieved by the following techniques [s] 5 201216416. In the semiconductor package construction of the reinforced base described above, the positioning grid may include a plurality of slots arranged in parallel and extending through the lower surface of the wafer pedestal. In the semiconductor package construction with the reinforced pedestal cited, the slots may be laser cut holes. In the semiconductor package structure of the reinforced base described above, the lower surface of the wafer pedestal and the convex surface of the embossed groove of the wafer are exposed to the outside of the encapsulant. In the above-described semiconductor package structure having a reinforced pedestal, the embossed trench may be a three-dimensional pattern formed by cutting in a wafer stage. In the semiconductor package structure of the reinforced base described above, it is an outer bowless package, wherein the lower surfaces of the pins are also exposed outside the sealant. In the semiconductor package structure of the reinforced pedestal, the φ includes a plurality of first bonding wires electrically connected to the plurality of pads of the active surface of the wafer to the pins of the lead frame. . In the semiconductor package structure with the reinforced base described above, at least one second bonding wire may be further included to electrically connect the wafer to the active surface of the wafer to the wafer base of the lead frame. In the semiconductor package structure having the reinforced base described above, a metal bonding layer may be further included, which is formed at least on the surface of the positioning grating in the wafer fitting groove. In the semiconductor package structure of the reinforced base described above, the metal 201216416 bonding layer may extend further to the peripheral surface of the wafer pedestal outside the wafer fitting groove for bonding the second bonding wire. It can be seen from the above technical solution that the semiconductor package structure with the reinforced base of the present invention has the following advantages and effects: 1. The wafer base and the cymbal base which can be at least partially embedded in the lead frame by the wafer As a technical means, a specific combination relationship between the positioning grid and the concave and convex grooves on the back surface of the wafer is used as a technical means. Since the concave and convex grooves are also inserted into the positioning grid of the wafer base when the wafer is embedded in the wafer base, Therefore, the wafer can be stuck in the wafer fitting groove of the wafer base without adhesive. Therefore, there is a strong bonding force between the wafer and the lead frame to omit the adhesive application and baking curing of the die bonding process. Second, the specific combination of the shape of the groove of the wafer base and the concave and convex grooves of the f-plane of the wafer and the positioning of the plurality of (five) through the slot of the wafer base can be used as one of the technologies. Since the concave and convex grooves of the wafer face can be embedded in the slots of the positioning grid of the wafer base, the delicate surface of the concave and convex grooves of the wafer can be exposed outside the sealing body, so that the back surface of the wafer is presented The support is bare and free, and the ancient private L has better heat dissipation characteristics and bonding force. As a technique, the wafer can be at least partially buried in the wafer base of the lead frame and the specific combination of the positioning grid of the chip base and the concave and convex grooves on the back surface of the wafer. Means, the wafer system ^ (four) glue method ^ ^ to the wafer base crystal 7 201216416 in the groove can be omitted from the thickness of the past adhesive and reduce the wafer protruding from the base of the cymbal. Therefore, the overall package height and the amount of the sealant can be reduced to shorten the wire-traveling distance to reduce the amount of gold wire used. The embodiments of the present invention are not described in detail below with reference to the accompanying drawings. Therefore, only the components and combinations related to the case are shown. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some ratios of dimensions and other related dimensions are either exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design. Detailed component layout may be more complicated. According to a first embodiment of the present invention, a semiconductor package structure having a reinforced base is illustrated in a cross-sectional view of Fig. 2. The semiconductor package structure 200 with the reinforced base includes a lead frame 210, a wafer 220, and a sealant 23". Referring to Fig. 2, and in conjunction with Figures 3A and 3B, the wire frame 21 (> has a wafer base 211 and a plurality of pins 212. The details of the wire frame 21 are Transmitting the electronic component function in the integrated circuit (1C) to the external metal carrier board, usually by using a metal sheet to form the wafer base 211 and chatting with the bows by means of chemical or mechanical stamping. 212. The wafer base 211 is formed with a wafer fitting groove 213 and a wafer fitting groove 213 [s] 8 201216416

底部之定位格柵214〇該晶片嵌合槽in係由半蝕刻方 法製作。該疋位袼柵214係為一體成型於該晶片嵌合槽 213之結構，作為在該晶片嵌合槽213内用以支撐晶片 之底邛。也就是說，在該晶片22〇放入至該晶片嵌合槽 213之後，位於該晶片嵌合槽213底部之該定位格柵 除了用以定位該晶片220之外，更可用以支撐該晶片22〇 於該晶片嵌合槽213内。此外，該.晶片嵌合槽213之開 口係不小於該晶片220之尺寸，以確保該晶片22〇能夠 ㈣容置於該晶片嵌合槽213内。在一較佳實施例中， 該定偉格栅214係包含複數個呈平行排列且貫穿至該晶 片基座211之—下表面2ua之槽孔214八，故使得該晶 片基座211之底部係為局部鏤空型態。其中，該些槽孔 2 14A係可為雷射切割孔，以雷射切割方式使該些槽孔 21 4A之形狀呈現為長方形，或者亦可切割為其它形狀， 例如：正方形等等、在本實施例中，該具強化式基座之 半導體封裝構造200係可為無外引腳式封裝，例如四方 扁平無外引腳（quad Hat Non-leaded，QFN)封裝，其中該 些引腳212之下表面係外露於該封膠體23〇之外，以作 為對外電性連接之銲點。而該些引腳212之下表面可單 排或多排排列在該封膠體23〇之底面周邊，而分佈在該 封膠體230底面之四側邊或兩侧邊。因此，在該具強化 式基座之半導體封裝構造2〇〇中，該導線架21〇之該些 弓丨腳212係可不需要具有從該封膠體23〇兩側延伸而出 且呈現彎折狀態之外腳部。 201216416 請參閱第2圖所示，該晶片22〇係設於該晶片基座 211上，該晶片220之一背面221係形成有一與該定位 格栅214形狀互補之凹凸溝槽222 ’以使該晶片22〇之 至少一部位以無黏著膠方式卡合固定於該晶片基座2ιι 之該晶片嵌合槽213内。具體而言，該晶片22〇係為以 半導體為基層之積體電路元件，例如：記憶體、邏輯元 件、特殊應用積體電路（ASIC)等。更具體地，該晶片22〇 鲁之主動面223上係設有複數個銲墊224，以作為連接 積體電路之對外端點，並且該些銲墊224係可位於該主 動面223之周邊，通常該些銲墊224之材質係可選用鋁、 銅等。此外，所稱之「形狀互補」係指該凹凸溝槽222 之凸起部位係恰可嵌入至該定位格栅214之槽孔214A， 並且該凹凸溝槽222之凹陷部位係可平貼於該定位格柵 214之表面，使得該凹凸溝槽222與該定位格栅214之 間形成猶如拼圖積木般的嵌合關係，故毋須使用黏著膠 % 即可將該晶片220固定於該晶片基座2 11之該晶片嵌合 槽2 1 3之内。在本實施例中，可利用晶圓圖案化薄化技 術，使該凹凸溝槽222係為在晶圓階段以切割方式形成 之立體圖案，其位於該晶片22〇之該背面221且不貫穿 至該主動面223。並且，可藉由打線方式形成複數個第 一鲜線240 ’以電性連接該晶片22〇之該些銲墊224至 該導線架210之該些引腳212。此外，該具強化式基座 之半導體封裝構造2〇〇係可另包含至少一第二銲線 250係電性連接該晶片220之其中至少一銲塾224至該 10 201216416 導線架210之該晶片基座211之周邊，達到接地連接之 作用。在一較佳型態中，該晶片22〇可完全嵌入至該晶 片嵌合槽213内，即該晶片22〇之該主動面223與該晶 片基座2 11之上表面係可位於同—水平高度，以縮短了 該些第一銲線240與該第二銲線25〇之打線距離與弧 尚，除了可以減少金線用量之外，更降低了整體的封裝 南度與減少封膠體用量，更可完全消除對晶片之模流沖 擊力道，使模封時該晶片220不會由該晶片基座211脫 •出。 請參閱第2圖所示，該封膠體23〇係包覆該晶片22〇 與部分之該些引腳212並結合該晶片基座211為一體。 詳細而言，該封膠體230係可選用具有熱固性之環氧樹 脂（epoxy molding compound，EMC)，在該“膠體 23〇 固 化之後，可保護位於内部之該晶片220、該些第一銲線 240與該第二銲線25〇不受外界環境的干擾。在本實施 • 例中，該封膠體230係未完全包覆該導線架21〇 ’其中 該晶片基座211之該下表面211A與該晶片220之該凹凸 溝槽222之凸起表面係可外露於該封膠體23〇之外故 使得該晶片220之該背面22 1呈現被支撐之裸空狀態， 以具有較佳.的散熱特性與結合力。 綜上可知，本發明該晶片220至少局部嵌埋於該導線 架210之該晶片基座211以及該晶片基座211之該定位 格柵213與該晶片220之該背面221之該凹凸溝槽222 兩者形狀互補之特定組合關係作為其中一技術手段，由 11 201216416 於該晶片220能夠直接嵌入固定於該晶片基座之該 晶片嵌合槽213與該定位格柵214，並且該曰 曰日月 2 2 0之 該凹凸溝槽222與該定位格柵214之間形成為一 ♦入關 係，使得該晶片220與該導線架210之結合能在毋須使 用黏著膠之情況下完成。因此，本發明係利用該晶片基 座211之該晶片嵌合槽213與該定位格栅214共同機械 式固疋住該晶片220而不易鬆脫，使該晶片220與該導 線架210之間具有較強的結合力，並且毋須使用黏著膠 鲁以節省材料成本’也省略了以往的黏晶（die bonding)製 程。此外，亦可降低整體的封裝高度與封膠體用量，並 縮短打線距離，以減少金線用量。 請參閱第4A至4C圖所示，其揭示該晶片22〇在晶 圓階段形成該凹凸溝槽222於該背面221時之元件截面 示意圖。如第4A圖所示，提供一晶圓1〇，該晶圓10在 未分割之前係包含有若干個晶片220。接著，藉由一第 φ 一刀輪21對該晶圓1 〇之背面進行第一次切割動作，以 形成該凹凸溝槽222於該晶圓1 〇之背面，而所指之「晶 圓之背面」係為在晶圓切割之後該晶片2 2 0之背面2 2 1。 之後’如第4B圖所示，再藉由一第二刀輪22沿著該晶 圓1 0之切割道（如虛線所示）進行第二次切割動作’以將 該晶圓1 〇切離成若干晶片220。最後，如第4C圖所示， 在切離該晶圓1 〇後，即可得到已切出該凹凸溝槽2 2 2 於背面22 1之該晶片220。細部來說，上述第一次切割 動作中’該第一刀輪2 1係未切穿該晶圓1 0 ’僅是用以[s】 12 201216416 在該晶圓10之背面切出對應每一晶片之該凹凸溝槽 222,而上述第二次切割動作中，該第二刀輪22則是直 接切穿該晶圓1〇’用以分離該晶圓1〇成若干晶片22〇。 在一較佳實施例中，該第一刀㉟21之切割深度係不大於 該晶圓10厚唐之二分之一，IV Vt try 坪艮 以確保該晶圓1 0分離成若 干晶片220後的結構強度。 依據本發明之第二具體實施例，另一種具強化式基座 之半導體封裝構造舉例說明於第5圖之截面示意圖，其 主要元件與第一實施例相同’故以相同符號標示並不再 詳予贅述。該具強化式基座之半導體封裝構造係包 含該導線架2U)、該晶片22〇與該封膠體23〇。其中該 晶片220之該凹凸溝槽222之形狀與該導線架21〇之該 晶片基座211之該定位格柵214互補，使得該晶片22〇 至少-部位能_無黏著膠方式卡合固定於該晶片基座 211之該晶片後合槽213内。 在本實施例中，該具強仆I — . 丹难化式基座之半導體封裝構造 300係可另包含—金屬接合層36〇，係至少形成於該晶片 嵌合槽213内之該定位格柵2M之表面。更進一步地， 該金屬接合層360係可以電鐘方式形成於該導線架21〇 之表面’通常該金屬接合層36〇之材質係可選自於金、 鎳金、銀或其它適當材質之其中之一。在該…2〇嵌 入至該晶片嵌合槽213内之後’❺了該晶片22〇之該凹 凸溝槽222卡固至該定位格栅214，利用該金屬接合層 360能夠使該晶片22〇與該定位格柵214進行共晶溶合⑸ 13 201216416 反應以產生接合關係，更緊密地結合該晶片2 2 0至該晶 片基座211’以避免該晶片220由該晶片嵌合槽213脫 出於該晶片基座211之外，並且該晶片220至少局部嵌 陷於該晶片嵌合槽213内，可減少對晶片之模流沖擊力 道’故不需要習知黏著膠之設置。此外，該金屬接合層 360亦可更延伸至該晶片基座211在該晶片嵌合槽213 之外之周邊表面，有利於該第二銲線25〇之接合。在本 實施例中，該具強化式基座之半導體封裝構造3〇〇可具 體為四方扁平無外引腳式（quad flat Non_ieaded，qFN)封 裝，該導線架2 1 0在切割製程之後，該些引腳2丨2會顯 露出未被該金屬接合層360所包覆之部分於該封膠體 2 3 0之側面。 以上所述，僅是本發明的較佳實施例而已並非對本 發明作任何形式上的 揭 限制，雖然本發明已以較佳實施例The bottom positioning grid 214 and the wafer fitting groove in are made by a half etching method. The gate grid 214 is integrally formed in the wafer fitting groove 213 as a bottom plate for supporting the wafer in the wafer fitting groove 213. That is, after the wafer 22 is placed in the wafer fitting groove 213, the positioning grid located at the bottom of the wafer fitting groove 213 can be used to support the wafer 22 in addition to the wafer 220. The wafer is fitted into the wafer fitting groove 213. In addition, the opening of the wafer fitting groove 213 is not smaller than the size of the wafer 220 to ensure that the wafer 22 can be accommodated in the wafer fitting groove 213. In a preferred embodiment, the stator grid 214 includes a plurality of slots 214 in parallel and extending through the lower surface 2ua of the wafer base 211, so that the bottom of the wafer base 211 is It is a partial hollow type. The slots 2 14A may be laser cutting holes, and the shapes of the slots 21 4A may be rectangular in a laser cutting manner, or may be cut into other shapes, such as a square, etc. In an embodiment, the reinforced base semiconductor package structure 200 can be an external leadless package, such as a quad flat Non-leaded (QFN) package, wherein the pins 212 The lower surface is exposed outside the sealant 23〇 as a solder joint for external electrical connection. The lower surfaces of the pins 212 may be arranged in a single row or a plurality of rows around the bottom surface of the sealing body 23, and distributed on the four sides or both sides of the bottom surface of the sealing body 230. Therefore, in the semiconductor package structure 2 of the reinforced base, the plurality of the arch legs 212 of the lead frame 21 need not have a shape extending from the sides of the sealant 23 and exhibit a bent state. Outside the foot. 201216416, as shown in FIG. 2, the wafer 22 is mounted on the wafer base 211, and a back surface 221 of the wafer 220 is formed with a concave-convex groove 222' complementary to the shape of the positioning grid 214. At least one portion of the wafer 22 is snap-fitted to the wafer fitting groove 213 of the wafer base 2 by adhesive-free bonding. Specifically, the wafer 22 is an integrated circuit element based on a semiconductor, such as a memory, a logic element, an application specific integrated circuit (ASIC), or the like. More specifically, the active surface 223 of the wafer 22 is provided with a plurality of pads 224 as external terminals of the integrated circuit, and the pads 224 are located around the active surface 223. Usually, the pads 224 are made of aluminum, copper or the like. In addition, the term "complementary shape" means that the convex portion of the concave-convex groove 222 is exactly embedded in the slot 214A of the positioning grid 214, and the recessed portion of the concave-convex groove 222 can be flattened thereto. The surface of the grating 214 is positioned such that the concave-convex groove 222 and the positioning grating 214 form a fitting relationship like a puzzle piece, so that the wafer 220 can be fixed to the wafer base 2 without using an adhesive. 11 of the wafer is fitted into the groove 2 1 3 . In this embodiment, the concave and convex trenches 222 can be formed into a three-dimensional pattern formed by cutting in the wafer stage by using a wafer pattern thinning technique, which is located on the back surface 221 of the wafer 22 and does not penetrate to The active surface 223. Moreover, a plurality of first fresh lines 240' can be formed by wire bonding to electrically connect the pads 224 of the wafer 22 to the pins 212 of the lead frame 210. In addition, the semiconductor package structure 2 having the reinforced base may further include at least one second bonding wire 250 electrically connecting at least one of the solder pads 224 of the wafer 220 to the wafer of the 10 201216416 lead frame 210. The periphery of the pedestal 211 functions as a ground connection. In a preferred embodiment, the wafer 22 can be completely embedded in the wafer fitting groove 213, that is, the active surface 223 of the wafer 22 and the upper surface of the wafer substrate 2 11 can be in the same level. The height is shortened to shorten the wire distance and arc of the first bonding wire 240 and the second bonding wire 25, in addition to reducing the amount of the gold wire, the overall package southness and the amount of the sealing body are reduced. The mold flow impact force on the wafer can be completely eliminated, so that the wafer 220 is not removed from the wafer base 211 during molding. Referring to FIG. 2, the encapsulant 23 is coated with the wafer 22 and a portion of the leads 212 and integrated with the wafer base 211. In detail, the encapsulant 230 may be provided with an epoxy molding compound (EMC), and after the "colloid 23" is cured, the wafer 220 located inside, the first bonding wires 240 may be protected. And the second bonding wire 25 is not interfered by the external environment. In the embodiment, the sealing body 230 does not completely cover the lead frame 21', wherein the lower surface 211A of the wafer base 211 and the The convex surface of the concave and convex groove 222 of the wafer 220 can be exposed outside the sealing body 23, so that the back surface 22 1 of the wafer 220 is in a supported bare state to have better heat dissipation characteristics. In summary, the wafer 220 of the present invention is at least partially embedded in the wafer pedestal 211 of the lead frame 210 and the positioning grid 213 of the wafer base 211 and the ridge of the back surface 221 of the wafer 220. The specific combination of the shapes of the trenches 222 is used as one of the technical means. The wafer 220 can be directly embedded in the wafer mating groove 213 and the positioning grid 214 fixed to the wafer base by the 11 201216416, and the crucible 222 Sun and moon The embossed trench 222 of the 260 and the positioning grid 214 are formed in a singular relationship, so that the bonding of the wafer 220 and the lead frame 210 can be completed without using an adhesive. Therefore, the present invention The wafer mating groove 213 of the wafer base 211 and the positioning grid 214 are mechanically fixed to the wafer 220 without being loosened, so that the wafer 220 has a strong bond with the lead frame 210. Force, and no need to use adhesive to save material cost' also omitted the previous die bonding process. In addition, it can also reduce the overall package height and the amount of sealant, and shorten the wire distance to reduce the amount of gold wire. Referring to FIGS. 4A-4C, the cross-sectional view of the device in which the bump 22 is formed on the back surface 221 at the wafer stage is disclosed. As shown in FIG. 4A, a wafer is provided. The wafer 10 includes a plurality of wafers 220 before being undivided. Then, a first cutting operation is performed on the back surface of the wafer 1 by a φ first cutter wheel 21 to form the concave and convex trenches 222. The wafer 1 , While the "back surface of the round grain" as referred to in line after dicing the back surface 20 of the wafer 2 2 2 1. Then, as shown in FIG. 4B, a second cutting operation is performed along a scribe line of the wafer 10 (shown by a broken line) by a second cutter wheel 22 to cut the wafer 1 away. A plurality of wafers 220 are formed. Finally, as shown in FIG. 4C, after the wafer 1 is cut away, the wafer 220 from which the concave and convex trenches 2 2 2 have been cut out is obtained. In detail, in the first cutting operation, 'the first cutter wheel 2 1 is not cut through the wafer 10 ' is only used for [s] 12 201216416 on the back side of the wafer 10, corresponding to each The bump groove 222 of the wafer, and in the second cutting operation, the second cutter wheel 22 directly cuts through the wafer 1' to separate the wafer 1 into a plurality of wafers 22A. In a preferred embodiment, the cutting depth of the first blade 3521 is not more than one-half of the thickness of the wafer 10, and the IV Vt try is used to ensure that the wafer 10 is separated into a plurality of wafers 220. Structural strength. According to a second embodiment of the present invention, another semiconductor package structure having a reinforced base is illustrated in a cross-sectional view of FIG. 5, the main components of which are the same as those of the first embodiment. Give a brief description. The semiconductor package structure with the reinforced base includes the lead frame 2U), the wafer 22 and the encapsulant 23A. The shape of the concave-convex groove 222 of the wafer 220 is complementary to the positioning grid 214 of the wafer base 211 of the lead frame 21, so that the wafer 22 can be at least partially adhered to the adhesive-free manner. The wafer base 211 is in the wafer rear groove 213. In this embodiment, the semiconductor package structure 300 having a strong susceptor can further include a metal bonding layer 36, which is formed at least in the wafer matching groove 213. The surface of the gate 2M. Further, the metal bonding layer 360 can be formed on the surface of the lead frame 21 by an electric clock. Generally, the material of the metal bonding layer 36 can be selected from gold, nickel gold, silver or other suitable materials. one. After the 2 〇 is embedded in the wafer fitting groove 213, the embossed groove 222 of the wafer 22 is clamped to the positioning grid 214, and the metal bonding layer 360 can be used to make the wafer 22 The positioning grid 214 undergoes eutectic fused (5) 13 201216416 reaction to create a bonding relationship, more closely bonding the wafer 220 to the wafer pedestal 211 ′ to prevent the wafer 220 from being detached from the wafer fitting groove 213 The wafer base 211 is external to the wafer base 211, and the wafer 220 is at least partially embedded in the wafer fitting groove 213, so that the mold impact force on the wafer can be reduced, so that the conventional adhesive is not required. In addition, the metal bonding layer 360 may further extend to the peripheral surface of the wafer base 211 outside the wafer fitting groove 213 to facilitate the bonding of the second bonding wire 25 . In this embodiment, the semiconductor package structure 3 of the reinforced base may be specifically a quad flat non-ieaded (qFN) package, after the lead frame 210 is cut, These pins 2丨2 will reveal the portion not covered by the metal bonding layer 360 on the side of the encapsulant 230. The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention, although the present invention has been described in its preferred embodiments.

• 術者，在不脫離 修改、等效性變化 内。• The surgeon does not deviate from modifications or equivalence changes.

14 20121641614 201216416

式基座之半導體封裝構造繪示其導線架之立體 示意圖。 第4A至4C圖：依據本發明之一具體實施例的具強化式 基座之半導體封裝構造繪示在晶圓階段形成凹 凸溝槽於晶片背面時之元件截面示意圖。 第5圖.依據本發明之第二具體實施例的一種具強化式 基座之半導體封裝構造之截面示意圖。 【主要元件符號說明】 10晶圓 21第一刀輪 22第二刀輪 100四方扁平無外引腳式半導體封裝構造 1 1 〇導線架 11 5擋膠環槽 170黏著膠 111晶片基座 120晶片 130封膠體 112 引腳 121背面 140銲線 200具強化式基座之半導體封裝構造 210導線架The semiconductor package structure of the pedestal shows a perspective view of the lead frame. 4A to 4C are diagrams showing a cross-sectional view of an element having a reinforced pedestal according to an embodiment of the present invention, showing a recessed groove formed on the back surface of the wafer at the wafer stage. Figure 5 is a cross-sectional view showing a semiconductor package structure having a reinforced base in accordance with a second embodiment of the present invention. [Main component symbol description] 10 wafer 21 first cutter wheel 22 second cutter wheel 100 square flat no-lead type semiconductor package structure 1 1 〇 lead frame 11 5 rubber ring groove 170 adhesive 111 wafer base 120 wafer 130 sealant 112 pin 121 back 140 wire 200 with reinforced base semiconductor package structure 210 lead frame

2 1 1晶片基座 213晶片敌合槽 2 2 0晶片 221背面 224銲墊 211A下表面 2 14定位格柵 222凹凸溝槽 230封膠體 240第一銲線 300具強化式基座之半導體封裝構造 360金屬接合層 212 引腳 214A槽孔 223 主動面 250第二銲線 [S] 152 1 1 wafer base 213 wafer enemy slot 2 2 0 wafer 221 back 224 solder pad 211A lower surface 2 14 positioning grid 222 concave and convex groove 230 encapsulant 240 first bonding wire 300 with reinforced base semiconductor package structure 360 metal bonding layer 212 pin 214A slot 223 active surface 250 second bonding wire [S] 15

Claims (1)

201216416 七、申請專利範圍： 1、一種具強化式基座之半導體封裝構造，包含： 一導線架，係具有一晶片基座與複數個引聊，該曰 片基座係形成有一晶片嵌合槽以及一形成於 八々、琢晶 片嵌合槽底部之定位格柵；201216416 VII. Patent application scope: 1. A semiconductor package structure with a reinforced base, comprising: a lead frame having a wafer base and a plurality of chats, wherein the die base is formed with a wafer fitting groove And a positioning grid formed on the bottom of the eight-inch, 琢 wafer mating groove; 一晶片’係設於該晶片基座上’該晶片之_背面係 形成有一與該定位格柵形狀互補之凹凸溝槽，以 使該晶片之至少一部位以無黏著膠方式卡合固定 於該晶片基座之該晶片嵌合槽内；以及 一封膠體，係包覆該晶片與部分之該些引腳並結合 該晶片基座為一體。 2、根據申請專利範圍第丨項之具強化式基座之半導體 封裝構造，其中該定位格栅係包含複數個呈平行排 列且貫穿至該晶片基座之一下表面之槽孔。 3、 根據申請專利範圍第2項之具強化式基座之半導體 封裝構造，其中該些槽孔係為雷射切割孔。 4、 根據申請專利範圍第2項之具強化式基座之半導體 封裝構造，其中該晶片基座之該下表面與該晶片之 該凹凸溝槽之凸起纟面係外露於該封膠體之外。 5、 根據"專利範圍帛4項《具強化式基座之半導體 封裝構造，其係為無外引腳式封裝，其t該些引腳 之外。 3、4或5項之具強化 其中該凹凸溝槽係為在 LSI ' 之下表面亦外露於該封膠體 6、根據申.請專利範圍第1、2 式基座之半導體封裝構造， 16 201216416 晶圓階段以切割方式形成之立體圖案。 7、 根據申請專利範圍第1、2 4 . . ε ^ 2 3、4或5項之具強化 式基座之I導體封裝構&，另包含I數個第一銲 線’係電性連接該晶片在其主動面之複數個鲜塾至 該導線架之該些引腳。 8、 根據申請專利範圍第7項之具強化式基座之半導體 封裝構造，另包含至少一第二銲線，係電性連接該a wafer is disposed on the base of the wafer. The back surface of the wafer is formed with a concave-convex groove complementary to the shape of the positioning grid, so that at least a portion of the wafer is snap-fitted to the portion in a non-adhesive manner. The wafer pedestal of the wafer pedestal; and a gel that encapsulates the wafer and a portion of the pins and is integrated with the wafer pedestal. 2. The semiconductor package structure of the reinforced base according to the scope of the patent application, wherein the positioning grid comprises a plurality of slots arranged in parallel and extending through a lower surface of the wafer base. 3. The semiconductor package structure of the reinforced base according to the second aspect of the patent application, wherein the slots are laser cut holes. 4. The semiconductor package structure of the reinforced base according to claim 2, wherein the lower surface of the wafer base and the convex surface of the concave groove of the wafer are exposed outside the sealant . 5. According to the “Scope of Patent” 帛4 “Semiconductor package construction with reinforced pedestal, which is an external-lead package, except for these pins. The reinforcement of the 3, 4 or 5 item is such that the concave and convex groove is exposed to the sealant body 6 under the LSI ', and the semiconductor package structure of the base of the first and second types according to the patent application scope, 16 201216416 A three-dimensional pattern formed by cutting in a wafer stage. 7. According to the patent application scope 1, 2 4 . . ε ^ 2 3, 4 or 5, the I-conductor package with a reinforced base, and the other includes a number of first wire bonds. The wafer has a plurality of fresh ridges on its active surface to the pins of the lead frame. 8. The semiconductor package structure of the reinforced base according to claim 7 of the patent application scope, further comprising at least one second bonding wire electrically connected to the semiconductor package 晶片在其主動面之一銲墊至該導線架之該晶片基 座。 9、根據申請專利範圍第8項之具強化式基座之半導體 封裝構造’另包含一金屬接合層，係至少形成於該 晶片嵌合槽内之該定位格柵之表面。 i〇、根據申請專利範圍第9項之具強化式基座之半導 體封裝構造’其中該金屬接合層係更延伸至該晶片 基座在該晶片嵌合槽之外之周邊表面，以供該第二 銲線之接合。 [S1 17The wafer is soldered to one of its active faces to the wafer base of the leadframe. 9. A semiconductor package structure having a reinforced base according to claim 8 of the patent application, further comprising a metal bonding layer formed on at least a surface of the positioning grid in the wafer fitting groove. The semiconductor package structure of the reinforced base according to claim 9 of the patent application, wherein the metal bonding layer extends to a peripheral surface of the wafer base outside the wafer fitting groove for the first The bonding of the two bonding wires. [S1 17
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TWI480995B (en) * 2013-06-21 2015-04-11 矽品精密工業股份有限公司 Quad flat no leads package and method of manufacture
TWI509759B (en) * 2013-08-19 2015-11-21 Powertech Technology Inc Substrateless package having sawing streets on heat spreader and its fabricating method
TWI724104B (en) * 2016-03-08 2021-04-11 日商安靠科技日本公司 Semiconductor package and manufacturing method of semiconductor package
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US11887915B2 (en) 2016-03-08 2024-01-30 Amkor Technology Japan, Inc. Semiconductor device having outer terminal portions with conductive layer on outer end surfaces and a method of manufacturing a semiconductor device
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WO2023098266A1 (en) * 2021-11-30 2023-06-08 广州金升阳科技有限公司 Pin structure of module power supply, and module power supply

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