CN112038242A - Rewiring fan-out packaging method and structure - Google Patents
Rewiring fan-out packaging method and structure Download PDFInfo
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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Abstract
The invention provides a rewiring fan-out type packaging method and a rewiring fan-out type packaging structure, which comprise the following steps: forming a rewiring layer on a top surface of the silicon substrate; bonding a wafer on the top surface of the redistribution layer; forming a cavity on the bottom surface of the silicon substrate to expose the rewiring layer; placing a chip in the cavity and attached to the redistribution layer; forming a plastic packaging layer on the bottom surface of the silicon substrate; and after the wafer is removed, an insulating solder mask layer and a metal layer are formed on the top surface of the redistribution layer.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a rewiring fan-out type packaging method and structure.
Background
An Embedded Wafer Level Ball Grid Array (eWLB) is an advanced packaging technology developed on the basis of Wafer Level Chip Scaled Package (WLCSP) technology. For the same size chip, the final packaging size is larger than the WLCSP by adopting an eWLB packaging form, and more I/O can be realized. eWLB is also known as Fanout packaging technology, fan-out packaging technology.
The fan-out package can be divided into three mainstream forms, i.e., an upward-facing chip-first package, a downward-facing chip-first package, and a downward-facing Redistribution Layer-first package, according to a preparation sequence between a Die (i.e., a bare chip) and an RDL (i.e., a Redistribution Layer), and the Redistribution Layer-first package has the following advantages: the multilayer RDL wiring layer is directly prepared on the Carrier Wafer, and is not prepared on a plastic package reconstruction Wafer like other two fan-out packages, so that the preparation of multilayer high-density RDL wiring with small wire diameter and wide wire distance is facilitated. The bare chip is directly welded with a pre-prepared UBM (under-bump-metal) on the rewiring layer in a face-down flip-chip welding mode, so that the displacement of the bare chip and the subsequent photoetching alignment difficulty caused by the mold flow impact in the wafer level plastic packaging process are reduced. A chip-first mode is adopted, no matter the face is upward or downward, a bare chip is transferred onto a wafer through a high-precision chip mounter, and then wafer-level plastic package technology is adopted to realize preparation of a reconstituted wafer. In the wafer-level plastic package process, the bare chip transferred to the wafer is affected by the mold flow impact to shift, and large errors are introduced to the photoetching alignment and the like in the subsequent RDL preparation process.
However, the existing re-wiring layer packaging is difficult to break through the wiring density bottleneck of fan-out type packaging, and the warpage problem of the EWLB process needs to be further improved significantly.
Disclosure of Invention
The invention aims to provide a fan-out packaging method and a fan-out packaging structure for firstly rewiring, which aim to solve the problem that the wiring density bottleneck of the existing fan-out packaging is difficult to break through.
The invention also aims to provide a rewiring fan-out packaging method and a rewiring fan-out packaging structure so as to solve the problem of warping caused by the conventional embedded wafer-level ball grid array process.
To solve the above technical problem, the present invention provides a rewiring fan-out package method and structure, including:
forming a rewiring layer on a top surface of the silicon substrate;
bonding a wafer on the top surface of the redistribution layer;
forming a cavity on the bottom surface of the silicon substrate to expose the rewiring layer;
placing a chip in the cavity and attached to the redistribution layer;
forming a plastic packaging layer on the bottom surface of the silicon substrate;
and after the wafer is removed, an insulating solder mask layer and a metal layer are formed on the top surface of the redistribution layer.
Optionally, in the re-routing-before-fan-out packaging method, the forming a re-routing layer on the top surface of the silicon substrate includes:
forming a multilayer rewiring layer on the top surface of the silicon substrate by using a Damascus process method;
the line width of the heavy wiring layer is 0.3-1 micron, and the line distance of the heavy wiring layer is 0.5-2 microns.
Optionally, in the rewiring fan-out package method, the method further includes:
after bonding the wafer, carrying out mechanical thinning or polishing process on the bottom surface of the silicon substrate to thin the silicon substrate to a first thickness;
the first thickness is less than 200 microns.
Optionally, in the re-routing-first fan-out packaging method, forming a cavity on a bottom surface of the silicon substrate to expose the re-routing layer includes:
and carrying out a patterned photoetching, deep reactive ion etching or wet etching process on the bottom surface of the silicon substrate until the rewiring layer is exposed.
Optionally, in the rewiring-first fan-out packaging method, the placing the chip in the cavity and attaching the chip to the rewiring layer includes:
preparing a bonding micro-bump on the front surface of a chip to be mounted by adopting thick film photoetching, electroplating, refluxing or wet etching processes;
attaching an NCF adhesive film above the bonding micro-convex points;
and a plurality of chips are inversely mounted in the cavity by adopting an inverse hot-press welding process.
Optionally, in the rewiring fan-out packaging method, forming a molding layer on the bottom surface of the silicon substrate includes:
and forming a plastic packaging layer on the bottom surface of the silicon substrate by adopting wafer-level plastic packaging.
Optionally, in the re-wiring fan-out type packaging method, after a plastic package layer is formed on the bottom surface of the silicon substrate, a mechanical thinning and polishing process is performed on the plastic package layer until the chip is exposed.
Optionally, in the rewiring-first fan-out packaging method, forming an insulating solder resist layer on the top surface of the rewiring layer includes: preparing a material of an insulating solder mask layer on the top surface of the rewiring layer by adopting a photoetching process, and patterning the material;
the insulating solder mask layer is made of polyimide.
Optionally, in the method for packaging a fan-out package with rewiring first, forming a metal layer on a top surface of the rewiring layer includes: and preparing wafer-level ball planting or bonding micro bumps on the insulating solder mask layer, and dividing the wafer-level ball planting or bonding micro bumps into a plurality of subunits.
The invention also provides a rewiring fan-out package structure, comprising:
a silicon substrate having a top surface attached to the rewiring layer, the body of the silicon substrate having a cavity therethrough;
the chip is accommodated in the cavity, one surface of the chip is attached to the rewiring layer, and the other surface of the chip is exposed to the bottom surface of the silicon substrate through the cavity;
the plastic packaging layer is filled in a gap between the chip and the silicon substrate;
an insulating solder resist layer covering a part of the top surface of the rewiring layer;
and the metal layer covers part of the top surface of the rewiring layer.
In the rewiring fan-out type packaging method and structure provided by the invention, the rewiring layer is formed on the top surface of the silicon substrate, the wafer is bonded on the top surface of the rewiring layer, the cavity is formed on the bottom surface of the silicon substrate, the rewiring layer is exposed, the chip is placed in the cavity and is attached to the rewiring layer, the plastic packaging layer is formed on the bottom surface of the silicon substrate, the insulating solder mask layer and the metal layer are formed on the top surface of the rewiring layer after the wafer is removed, the partial retention of the silicon substrate is realized, the plastic packaging layer is replaced, the warping of the whole packaging structure can be effectively reduced, the silicon substrate with a certain thickness is retained, and the whole warping is effectively reduced by increasing the area of the silicon structure on the basis of enhancing the strength of the plastic packaging layer.
According to the invention, by utilizing the Damascus process method, a plurality of layers of heavy wiring layers are formed on the top surface of the silicon substrate, so that the line width can reach 0.2um and below, the line distance can reach 0.2um and below, the number of wiring layers can reach 6 and above, and the ultra-high density wiring capability is realized.
According to the invention, after the plastic packaging layer is formed on the bottom surface of the silicon substrate, a mechanical thinning and polishing process is adopted on the plastic packaging layer until the chip is exposed.
The packaging structure has the advantages of ultrahigh-density wiring capacity, no expensive processes such as TSV and the like, small plastic package material occupation ratio, small overall warpage, exposed integrated chip substrate, heat dissipation, low cost and the like; the method is suitable for the application requirements of multi-chip high-density low-cost packaging. Compared with the traditional EWLB scheme, the wiring layer can be realized based on the front BEOL process, and the bottleneck of wiring density does not exist; and the volume of the plastic packaging material is small, the warpage is small, and the process difficulty is low.
Drawings
FIGS. 1-11 are schematic diagrams of a rewiring fan-out package method according to an embodiment of the present invention;
FIG. 12 is a cross-sectional SEM of a multi-layer BEOL interconnect layer implemented based on a damascene process in accordance with an embodiment of the invention;
shown in the figure: 10-a silicon substrate; 21-a metal wiring layer; 22-insulating dielectric layer; 31-a wafer; 32-temporary bonding glue; 40-a cavity; 50-chip; 51-NCF glue film; 52-bonding the micro-bumps; 60-plastic packaging layer; 70-insulating solder mask; 80-metal layer.
Detailed Description
The rewiring fan-out package method and structure according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Furthermore, features from different embodiments of the invention may be combined with each other, unless otherwise indicated. For example, a feature of the second embodiment may be substituted for a corresponding or functionally equivalent or similar feature of the first embodiment, and the resulting embodiments are likewise within the scope of the disclosure or recitation of the present application.
The core idea of the invention is to provide a fan-out packaging method and structure with rewiring firstly, so as to solve the problem that the wiring density bottleneck of the existing fan-out packaging is difficult to break through.
The core idea of the invention is to provide a re-wiring fan-out packaging method and structure to solve the problem of warpage caused by the existing embedded wafer-level ball grid array process.
In order to realize the thought, the invention provides a rewiring fan-out type packaging method and a rewiring fan-out type packaging structure, which comprise the following steps: a silicon substrate having a top surface attached to the rewiring layer, the body of the silicon substrate having a cavity therethrough; the chip is accommodated in the cavity, one surface of the chip is attached to the rewiring layer, and the other surface of the chip is exposed to the bottom surface of the silicon substrate through the cavity; the plastic packaging layer is filled in a gap between the chip and the silicon substrate; an insulating solder resist layer covering a part of the top surface of the rewiring layer; and the metal layer covers part of the top surface of the rewiring layer.
The fan-out package can be divided into three main flow forms, namely, Die-First-Face Down, Die-First-Face up, and Die-Last-Face Down, according to the preparation sequence between a Die (i.e., a bare Die) and an RDL (i.e., a Redistribution Layer). In the Die-first mode, no matter Die Face up or Die Face down, a Thermal peeling film (e.g., Thermal Release Tape of Nitto corporation, japan) is generally attached to a Carrier Wafer (i.e., a support Wafer, generally a stainless steel disc, a glass Wafer, a silicon Wafer, etc.), then a high-precision chip mounter is used to pick up bare chips, the picked bare chips are transferred to the Carrier Wafer, and then a Wafer-level plastic package process is used to implement preparation of a reconstituted Wafer (so-called reconstituted Wafer, which means that the bare chips on the Carrier Wafer may not be prepared on the same Wafer or on the same batch of wafers, or even be prepared based on different substrate materials or different process node technologies, but after the chips are transferred to the Carrier Wafer, a Wafer-level plastic package process is used to finally present a whole Wafer, i.e., a reconstituted Wafer). And then preparing a plurality of layers of RDLs and preparing micro bumps, and finally cutting to obtain a single chip packaging body. The Die Last Face Down process, although a typical form of fan-out package, is also referred to as "RDL-First Fanout", i.e., "rewiring fan-out package".
By comparing three main flow fan-out type packaging process flows, it can be easily found that the RDL-first Fanout package has the following advantages: 1) the multilayer RDL wiring layer is directly prepared on the Carrier Wafer, and is not prepared on a plastic package reconstruction Wafer like other two fan-out packages, so that the preparation of the multilayer high-density RDL wiring with a small wire diameter and a wide wire distance is facilitated. The RDL carrier wafer has a smooth surface, the warpage can be controlled within 2-5um, and the warpage of the plastic packaging reconstruction wafer can reach 3mm or even higher. The preparation of the RDL is realized by Physical-Vapor Deposition (PVD), photolithography, electroplating, wet photoresist removal, wet etching and other processes, and the warpage of the substrate wafer seriously affects the photolithography precision. The larger the warpage, the worse the lithography accuracy. Therefore, it can be seen that, by using the RDL-first Fanout package technology, the RDL is fabricated on the low warpage carrier wafer, and the fabrication process thereof can be implemented by Back-End-Of-Line (BEOL) in the standard CMOS process, and can be completely implemented by the current advanced semiconductor node fabrication process, so that the fabrication Of multilayer RDL wiring (the number Of wiring layers can reach 5-6 layers) with a Line width Of 0.2 um/a Line distance Of 0.2um can be easily implemented. And the preparation of multilayer RDL can be gradually realized on the release layer by adopting photosensitive polymer as an insulating medium layer. And adopt fan-out type encapsulation of Die first mode, current RDL linewidth/line spacing are 5um/5um, and most advanced is about 2um/2um, has not realized 1um/1um yet. 2) The bare chip is directly welded with a UBM (under-bump metal) prepared in advance on an RDL Carrier in a face Down flip-chip welding mode, so that the displacement of the bare chip caused by mold flow impact in the wafer-level plastic package process and the difficulty in subsequent photoetching alignment are favorably reduced. And a Die first mode, namely a Face up mode or a Face down mode is adopted, the bare chip is transferred onto a carrier through a high-precision chip mounter, and then the wafer-level plastic package process is adopted to realize the preparation of the reconstituted wafer. In the wafer level plastic package process, a bare chip transferred to a carrier is subjected to the influence of mold flow impact to generate displacement, and large errors are introduced to photoetching alignment and the like in the subsequent RDL preparation process.
In view of the above advantages of RDL-first Fanout package, companies such as Amkor, Samsung, unimicon, and the like, all propose their own RDL-first Fanout package technology on the basis of the basic RDL-first Fanout package, and realize the multilayer RDL preparation by adopting photosensitive Polyimide (Polyimide) as an insulating medium layer on a release layer and electroplating, and the like. At present, the line width spacing of RDL wiring which can be realized by adopting the scheme is about 2um/2um, and the line width spacing is gradually increased towards the direction of 1um/1 um.
A typical package structure process for TSV-Less (i.e., SWIFT, Silicon-Wafer-Integrated Fan-out Technology) from Amkor is as follows: 1) realizing the preparation of high-density multilayer RDL wiring and a top layer UBM on a silicon wafer by utilizing a BEOL (wafer-level integrated circuit) process; 2) flip-chip bonding the bare chip with the micro-bump prepared on the surface to UBM prepared on a silicon wafer; 3) filling underfill (underfill) in the gaps of the flip chip and the upper and lower stacked chips; 4) carrying out wafer-level plastic package; 5) removing the silicon substrate, and only reserving the multilayer RDL and the insulating medium layer prepared on the silicon substrate; 6) carrying out wafer-level ball planting; 7) and (5) carrying out plastic packaging and cutting to obtain a single chip packaging body.
Silicon-based Fanout packaging technology, eSiFO, is a fan-out packaging technology proposed by huatian technology in 2015. It is essentially a Die-first Face-up fan-out package, except that the substrate of the reconstituted wafer is silicon rather than plastic.
The invention adopts the technical scheme of RDL-First Fanout, as shown in figures 1-11, comprising the following steps: forming a rewiring layer on a top surface of the silicon substrate; bonding a wafer on the top surface of the redistribution layer; forming a cavity on the bottom surface of the silicon substrate to expose the rewiring layer; placing a chip in the cavity and attached to the redistribution layer; forming a plastic packaging layer on the bottom surface of the silicon substrate; and after the wafer is removed, an insulating solder mask layer and a metal layer are formed on the top surface of the redistribution layer.
As shown in fig. 1, in the rewiring-before-fan-out packaging method, the forming of the rewiring layer on the top surface of the silicon substrate 10 includes: forming a plurality of heavy wiring layers (including a metal wiring layer 21 and an insulating medium layer 22) on the top surface of the silicon substrate 10 by using a Damascus process method; the line width of the heavy wiring layer is 0.3-1 micron, and the line distance of the heavy wiring layer is 0.5-2 microns.
As shown in fig. 2, applying a temporary bonding paste 32 on the top surface of the redistribution layer, and bonding a wafer 31 on the temporary bonding paste 32; in the rewiring-first fan-out package method, as shown in fig. 3, the method further includes: after bonding the wafer 31, performing a mechanical thinning or polishing process on the bottom surface of the silicon substrate 10 to thin the silicon substrate 10 to a first thickness; the first thickness is less than 200 microns, and if the first thickness is too large, the process cost is greatly increased.
As shown in fig. 4, in the rewiring-before-fan-out packaging method, forming a cavity 40 on the bottom surface of the silicon substrate 10 to expose the rewiring layer includes: and carrying out a patterned photoetching, deep reactive ion etching or wet etching process on the bottom surface of the silicon substrate 10 until the rewiring layer is exposed.
As shown in fig. 5, in the rewiring-fan-out packaging method, placing a chip 50 in the cavity 40 and attaching the rewiring layer includes: preparing a bonding micro-bump 52 on the front surface of the chip 50 to be mounted by adopting thick film photoetching, electroplating, refluxing or wet etching processes; attaching an NCF adhesive film 51 above the bonding micro-convex points; a plurality of chips 50 are flip-chip mounted into the cavity 40 using a flip-chip thermocompression bonding process.
As shown in fig. 6, in the rewiring fan-out packaging method, forming a molding layer 60 on the bottom surface of the silicon substrate 10 includes: a plastic package layer 60 is formed on the bottom surface of the silicon substrate 10 by using wafer-level plastic package.
As shown in fig. 7, in the rewiring fan-out packaging method, after a molding layer 60 is formed on the bottom surface of the silicon substrate 10, a mechanical thinning and polishing process is performed on the molding layer 60 until the chip 50 is exposed.
As shown in fig. 8, the wafer 31 is removed. In the rewiring-first fan-out type packaging method, as shown in fig. 9, forming an insulating solder resist layer on the top surface of the rewiring layer includes: preparing a material of the insulating solder mask layer 70 on the top surface of the rewiring layer by adopting a photoetching process, and patterning the material; the material of the insulating solder resist layer 70 is polyimide.
In addition, in the rewiring-fan-out type packaging method, forming the metal layer 80 on the top surface of the rewiring layer includes: on the insulating solder resist layer 70, wafer level ball-planting (as shown in fig. 10) or bonding micro-bumps (as shown in fig. 11) are prepared and divided into a plurality of sub-units.
Compared with a silicon-based Fanout mainstream scheme, the integrated chip is exposed from the silicon substrate, so that the heat dissipation performance is better; compared with the traditional EWLB and other schemes, the wiring layer can be realized based on the front BEOL process, and the bottleneck of wiring density does not exist; the volume of the plastic packaging material is small, the warpage is small, and the process difficulty is low; compared with the eSIFO scheme, the integrated chip substrate is exposed, the heat dissipation performance is better, the step sequence is different, the RDL is formed firstly, so that the method has the advantages that the ultra-high-density RDL wiring can be realized based on the front BEOL process, the line width and the line distance can be further reduced to 0.2um or even lower, and no wiring density bottleneck exists; compared with the RDL-first Fanout packaging technology of company of Amkor, Samsung, Unimicon and the like, the scheme is that a release layer with a photothermal effect is firstly spin-coated on a glass wafer, and multilayer RDL preparation is sequentially realized on the release layer; the invention realizes the multilayer RDL preparation meeting the actual requirement directly on the conventional common silicon substrate based on the conventional BEOL process, so the method has the advantages of realizing the ultra-high density RDL wiring, further reducing the line width and the line distance to 0.2um or even lower and having no wiring density bottleneck; in the scheme, the support wafer in the process of preparing the multilayer RDL is finally detached and separated through detaching the bond, and the silicon substrate in the invention is reserved in the final packaging body, so that the advantages of reducing warpage and improving the structural strength of the packaging body are achieved; compared with the TSV-Less scheme developed by the Amkor company, the Amkor scheme only utilizes a plurality of layers of RDL wiring layers, and a bulk silicon substrate is integrally etched by a wet method after a wafer-level plastic package process, but in the invention, the final part of the bulk silicon substrate is reserved in a plastic package layer to reduce warping; in the Amkor scheme, firstly, multilayer RDL preparation is realized on the front surface of a bulk silicon wafer, and flip-chip welding from a chip to the wafer is sequentially realized on the front surface of the wafer; in addition, the residual bulk silicon part can form a packaging body framework, so that the structural strength of the packaging body is improved.
A damascene process, i.e., a copper damascene process, is a BEOL process proposed by IBM to replace the conventional aluminum interconnect, and the process design inspiration is said to originate from the damascene process. The Damascus process is divided into two process forms of 'single Damascus' and 'dual Damascus', wherein the 'single Damascus' process is relatively simple, and mainly changes the manufacture of a single-layer metal wire from traditional metal etching + dielectric deposition + CMP into dielectric etching + metal filling + CMP. CMP, Chemical-Mechanical-Polishing.
A typical "dual damascene" process flow is briefly described as follows: a) covering the wafer surface with the M1 metal layer with an Inter-layer-Dielectric (ILD); b) preparing the SiN etching mask layer by utilizing a photoetching process; c) implementing partial dry Etching of the SiN layer by using a Reactive-Ion-Etching (RIE) process; d) removing the photoresist (ashing process is generally adopted in the previous wafer factory), and depositing an inter-Metal-Dielectric (IMD) layer; e) and preparing the etching mask layer by utilizing a photoetching process. Fig. 11 shows a flow in which a "dual damascene" method of Trench first and Via second is adopted; f) utilizing RIE (reactive ion etching) technology to realize Trench etching, utilizing photoetching technology to realize Via etching mask layer preparation, then utilizing RIE to realize Via etching, and stopping till reaching the SiN layer above the M1(Cu) layer; g) removing the photoresist, and etching and windowing SiN above M1 by RIE etching; h) utilizing a Physical-Vapor-deposition (PVD) process sequence to realize Ta/TaN/Cu barrier layer/seed layer deposition; i) utilizing a wafer electroplating process to realize Trench/Via inner copper electroplating filling; j) and removing the residual layer of the redundant electroplated copper on the surface of the wafer by using a Chemical Mechanical Polishing (CMP) process, and depositing a SiN layer by using a Low-Pressure-Chemical-Vapor-Deposition (LPCVD) process to finish the preparation of M2-RDL. The multilayer RDL preparation can be subsequently achieved according to the above described process sequence. As shown in fig. 12, a cross-sectional SEM of a multi-layer BEOL interconnect layer is implemented based on a damascene process. It can be seen that the structure realizes 9 layers of interconnection lines in total, and the minimum line width and line distance is less than 0.5 um.
In summary, the above embodiments have described the detailed descriptions of the different configurations of the rewiring fan-out package method and structure, but it is understood that the present invention includes but is not limited to the configurations listed in the above embodiments, and any modifications based on the configurations provided in the above embodiments are within the scope of the present invention. One skilled in the art can take the contents of the above embodiments to take a counter-measure.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A rewiring fan-out package method, comprising:
forming a rewiring layer on a top surface of the silicon substrate;
bonding a wafer on the top surface of the redistribution layer;
forming a cavity on the bottom surface of the silicon substrate to expose the rewiring layer;
placing a chip in the cavity and attached to the redistribution layer;
forming a plastic packaging layer on the bottom surface of the silicon substrate;
and after the wafer is removed, an insulating solder mask layer and a metal layer are formed on the top surface of the redistribution layer.
2. The rewiring fan-out package method of claim 1 wherein said forming a rewiring layer on the top surface of the silicon substrate comprises:
forming a multilayer rewiring layer on the top surface of the silicon substrate by using a Damascus process method;
the line width of the heavy wiring layer is 0.3-1 micron, and the line distance of the heavy wiring layer is 0.5-2 microns.
3. The rewiring fan-out package method of claim 1 further comprising:
after bonding the wafer, carrying out mechanical thinning or polishing process on the bottom surface of the silicon substrate to thin the silicon substrate to a first thickness;
the first thickness is less than 200 microns.
4. The rewiring fan-out package method of claim 1 wherein forming a cavity in the bottom surface of the silicon substrate to expose the rewiring layer comprises:
and carrying out a patterned photoetching, deep reactive ion etching or wet etching process on the bottom surface of the silicon substrate until the rewiring layer is exposed.
5. The rewiring fan-out package method of claim 1 wherein placing a chip in a cavity and attached to the rewiring layer comprises:
preparing a bonding micro-bump on the front surface of a chip to be mounted by adopting thick film photoetching, electroplating, refluxing or wet etching processes;
attaching an NCF adhesive film above the bonding micro-convex points;
and a plurality of chips are inversely mounted in the cavity by adopting an inverse hot-press welding process.
6. The rewiring fan-out package method of claim 1, wherein forming a molding layer on the bottom surface of the silicon substrate comprises:
and forming a plastic packaging layer on the bottom surface of the silicon substrate by adopting wafer-level plastic packaging.
7. The rewiring fan-out package method of claim 1, wherein after forming a molding layer on the bottom surface of the silicon substrate, a mechanical thinning polishing process is applied to the molding layer until the chip is exposed.
8. The rewiring fan-out package method of claim 1, wherein forming an insulating solder mask layer on the top surface of the rewiring layer comprises: preparing a material of an insulating solder mask layer on the top surface of the rewiring layer by adopting a photoetching process, and patterning the material;
the insulating solder mask layer is made of polyimide.
9. The rewiring fan-out package method of claim 1 wherein forming a metal layer on a top surface of said rewiring layer comprises: and preparing wafer-level ball planting or bonding micro bumps on the insulating solder mask layer, and dividing the wafer-level ball planting or bonding micro bumps into a plurality of subunits.
10. A rewiring fan-out package structure, comprising:
a silicon substrate having a top surface attached to the rewiring layer, the body of the silicon substrate having a cavity therethrough;
the chip is accommodated in the cavity, one surface of the chip is attached to the rewiring layer, and the other surface of the chip is exposed to the bottom surface of the silicon substrate through the cavity;
the plastic packaging layer is filled in a gap between the chip and the silicon substrate;
an insulating solder resist layer covering a part of the top surface of the rewiring layer;
and the metal layer covers part of the top surface of the rewiring layer.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112928077A (en) * | 2021-01-20 | 2021-06-08 | 上海先方半导体有限公司 | Multi-chip heterogeneous integrated packaging unit and manufacturing method and stacking structure thereof |
| CN113035813A (en) * | 2021-03-02 | 2021-06-25 | 华进半导体封装先导技术研发中心有限公司 | Chip packaging structure and chip packaging method |
| WO2023087847A1 (en) * | 2021-11-19 | 2023-05-25 | 华天科技（昆山）电子有限公司 | Ultra-thin fan-out package structure for chip and manufacturing method therefor |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020001937A1 (en) * | 2000-06-30 | 2002-01-03 | Nec Corporation | Semiconductor package board using a metal base |
| CN1417855A (en) * | 2001-10-31 | 2003-05-14 | 新光电气工业株式会社 | Multilayer substrate for semiconductor device |
| US20030161129A1 (en) * | 2002-01-15 | 2003-08-28 | Sony Corporation | Flexible multilayer wiring board and manufacture method thereof |
| JP2005333006A (en) * | 2004-05-20 | 2005-12-02 | Nec Toppan Circuit Solutions Inc | Printed wiring board and semiconductor device |
| US20090134530A1 (en) * | 2007-11-21 | 2009-05-28 | Shinko Electric Industries Co., Ltd. | Wiring substrate and method of manufacturing the same |
| CN104600039A (en) * | 2014-12-26 | 2015-05-06 | 南通富士通微电子股份有限公司 | Double-side interconnecting fan-out process |
| CN105448752A (en) * | 2015-12-01 | 2016-03-30 | 华天科技（昆山）电子有限公司 | Fan-out package method of embedded silicon substrate |
| CN208655611U (en) * | 2018-06-26 | 2019-03-26 | 华天科技（昆山）电子有限公司 | Improve the fan-out-type wafer stage chip encapsulating structure of warpage |
| TWI685284B (en) * | 2018-12-11 | 2020-02-11 | 欣興電子股份有限公司 | Package structure and manufacturing method thereof |
| CN111490025A (en) * | 2019-01-29 | 2020-08-04 | 矽品精密工业股份有限公司 | Electronic package, package substrate thereof and manufacturing method thereof |
-
2020
- 2020-09-10 CN CN202010945047.0A patent/CN112038242A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020001937A1 (en) * | 2000-06-30 | 2002-01-03 | Nec Corporation | Semiconductor package board using a metal base |
| CN1417855A (en) * | 2001-10-31 | 2003-05-14 | 新光电气工业株式会社 | Multilayer substrate for semiconductor device |
| US20030161129A1 (en) * | 2002-01-15 | 2003-08-28 | Sony Corporation | Flexible multilayer wiring board and manufacture method thereof |
| JP2005333006A (en) * | 2004-05-20 | 2005-12-02 | Nec Toppan Circuit Solutions Inc | Printed wiring board and semiconductor device |
| US20090134530A1 (en) * | 2007-11-21 | 2009-05-28 | Shinko Electric Industries Co., Ltd. | Wiring substrate and method of manufacturing the same |
| CN104600039A (en) * | 2014-12-26 | 2015-05-06 | 南通富士通微电子股份有限公司 | Double-side interconnecting fan-out process |
| CN105448752A (en) * | 2015-12-01 | 2016-03-30 | 华天科技（昆山）电子有限公司 | Fan-out package method of embedded silicon substrate |
| CN208655611U (en) * | 2018-06-26 | 2019-03-26 | 华天科技（昆山）电子有限公司 | Improve the fan-out-type wafer stage chip encapsulating structure of warpage |
| TWI685284B (en) * | 2018-12-11 | 2020-02-11 | 欣興電子股份有限公司 | Package structure and manufacturing method thereof |
| CN111490025A (en) * | 2019-01-29 | 2020-08-04 | 矽品精密工业股份有限公司 | Electronic package, package substrate thereof and manufacturing method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112928077A (en) * | 2021-01-20 | 2021-06-08 | 上海先方半导体有限公司 | Multi-chip heterogeneous integrated packaging unit and manufacturing method and stacking structure thereof |
| CN113035813A (en) * | 2021-03-02 | 2021-06-25 | 华进半导体封装先导技术研发中心有限公司 | Chip packaging structure and chip packaging method |
| CN113035813B (en) * | 2021-03-02 | 2022-07-19 | 华进半导体封装先导技术研发中心有限公司 | Chip packaging structure and chip packaging method |
| WO2023087847A1 (en) * | 2021-11-19 | 2023-05-25 | 华天科技（昆山）电子有限公司 | Ultra-thin fan-out package structure for chip and manufacturing method therefor |
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Application publication date: 20201204 |