JP2006059863A - Package substrate and its manufacturing method - Google Patents

Package substrate and its manufacturing method Download PDF

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Publication number
JP2006059863A
JP2006059863A JP2004237379A JP2004237379A JP2006059863A JP 2006059863 A JP2006059863 A JP 2006059863A JP 2004237379 A JP2004237379 A JP 2004237379A JP 2004237379 A JP2004237379 A JP 2004237379A JP 2006059863 A JP2006059863 A JP 2006059863A
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Japan
Prior art keywords
component mounting
mounting pad
package substrate
pad portion
interlayer connection
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JP2004237379A
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Japanese (ja)
Inventor
Masaru Kojima
勝 小島
Masayuki Shiobara
正幸 塩原
Junichi Ishibashi
純一 石橋
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Nippon CMK Corp
CMK Corp
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Nippon CMK Corp
CMK Corp
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Priority to JP2004237379A priority Critical patent/JP2006059863A/en
Publication of JP2006059863A publication Critical patent/JP2006059863A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a package substrate wherein a part mounting pad is made smaller in diameter and the joint strength of the pad is improved. <P>SOLUTION: The package substrate has no land on the surface layer of a part mounting pad, and a circuit surface and an interlayer connection via surface are formed on the same plane as an insulating layer surface in the part mounting pad. Its manufacturing method includes a step where a nickel plating is used as a supporting body and an insulating layer and an interlayer connection via are formed thereon, and a step where the nickel supporting body is peeled off to form the part mounting pad having the interlayer connection via as the surface layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、小径かつパッド接続強度の高い部品実装パッド部を有するパッケージ基板及びその製造方法に関する。   The present invention relates to a package substrate having a component mounting pad portion having a small diameter and high pad connection strength, and a method for manufacturing the same.

近年、フリップチップ実装に代表されるように、部品を受ける側となるパッケージ基板の部品実装用のパッドを小径化及びそれに対応する狭ピッチ化の技術が重要とされている。ここで、従来の技術における部品実装用のパッケージ基板、特に部品実装パッド部における背景技術について説明する。   2. Description of the Related Art In recent years, as represented by flip chip mounting, a technique for reducing the diameter of a component mounting pad on a package substrate on a component receiving side and reducing the pitch corresponding thereto is important. Here, a background art in a component mounting package substrate, particularly a component mounting pad portion, in the conventional technique will be described.

従来の部品実装用のパッケージ基板としては、例えば図5に示される構造のものが既に報告されている(特許文献1参照)。すなわち、まず図5(a)のように基板の内層部にあたるコア材料部13に回路部4aの形成を行ない、次いで、必要に応じて図5(b)に示されるようにビルドアップ構造を形成し、回路形成を行なった後に、部品実装パッド部19a、19bにはんだペースト14を塗布し、目的とする部品15を実装することで、図5(c)に示される構造の部品実装後の基板を得る。因に、この部品実装パッド部としては、部品実装面積の小スペース化の背景を受け、回路形成により形成される部品実装パッド部(平パッド構造)19aの他に、層間接続ビアを使用した部品実装パッド部(BVHパッド構造)19bを形成し、層間での電気的な接続が取れるような構造体にすることが多くなってきている。   As a conventional package substrate for component mounting, for example, a substrate having a structure shown in FIG. 5 has already been reported (see Patent Document 1). That is, first, the circuit portion 4a is formed on the core material portion 13 corresponding to the inner layer portion of the substrate as shown in FIG. 5 (a), and then a build-up structure is formed as shown in FIG. 5 (b) if necessary. Then, after the circuit is formed, the solder paste 14 is applied to the component mounting pad portions 19a and 19b, and the target component 15 is mounted, so that the substrate having the structure shown in FIG. Get. Incidentally, as the component mounting pad portion, in response to the background of the reduction of the component mounting area, a component using an interlayer connection via in addition to the component mounting pad portion (flat pad structure) 19a formed by circuit formation. Increasingly, a mounting pad portion (BVH pad structure) 19b is formed to make a structure that can be electrically connected between layers.

しかしながら、前項で記述のBVHパッド構造の部品実装パッド部19bは、前記部品実装用のパッドの小径化及び実装面積の小スペース化を形成する際に、次のような点が問題となっていた。   However, the component mounting pad portion 19b having the BVH pad structure described in the previous section has the following problems in forming the component mounting pad with a small diameter and a small mounting area. .

1点目は、従来のBVHの構造的な問題である。それは、従来のBVHの穴あけ方法は主にレーザで行なわれているため、表層の開口部が底部の開口部よりも大きい構造となる。この開口部が大きい器状の構造は、底部のデスミア工程などによる洗浄の行ない易さやBVH用めっき液の入りやすさという点では利点があるものの、前記小径の層間接続ビアを有する部品実装パッドを考えた場合、BVH構造を小径にするとBVH底部の開口部はさらに小径となり、前記デスミア工程による洗浄の困難さやBVH用めっき液の入りにくさが原因となり、層間での電気的な接続箇所で接続不良を生じやすく、小径な部品実装パッド部を形成する背景において構造的な不具合を生じさせることである。   The first point is a structural problem of the conventional BVH. This is because a conventional BVH drilling method is mainly performed by a laser, so that the opening of the surface layer is larger than the opening of the bottom. Although this vessel-shaped structure with a large opening has advantages in terms of easy cleaning by a desmear process at the bottom and the ease of entering the plating solution for BVH, the component mounting pad having the small-diameter interlayer connection via is provided. When considered, if the BVH structure is made smaller in diameter, the opening at the bottom of the BVH becomes smaller in diameter, causing difficulty in cleaning by the desmear process and difficulty in entering the plating solution for BVH. It is easy to produce a defect and causes a structural defect in the background of forming a small component mounting pad portion.

2点目は、部品実装パッド部を小径化すると、当該実装パッドと絶縁層との接合部の面積が小さくなり、部品の実装時や物理的な衝撃を受けた際にパッド剥がれが生じることである。
特開2004−140412号公報
Secondly, when the diameter of the component mounting pad portion is reduced, the area of the joint between the mounting pad and the insulating layer is reduced, and pad peeling occurs when the component is mounted or when a physical impact is applied. is there.
Japanese Patent Laid-Open No. 2004-140412

以上のような従来の問題に鑑み、本発明は、部品実装パッド部を小径化すると共に、当該パッド部の接続強度を向上させたパッケージ基板とその製造方法を提供することを課題としている。   In view of the conventional problems as described above, it is an object of the present invention to provide a package substrate and a manufacturing method thereof in which the component mounting pad portion is reduced in diameter and the connection strength of the pad portion is improved.

発明者は上記課題を解決するために種々研究を重ねた。その結果、部品実装パッド部にランド部を設けない構造とすれば、パッド部の小径化を実現できると共に、部品実装パッド部となる層間接続ビアの内層部に鍔状に張出したランド部を設ければ、当該パッド部の接続強度を向上させることができることを見出して発明を完成するに至った。   The inventor has conducted various studies in order to solve the above problems. As a result, if the structure in which the land portion is not provided in the component mounting pad portion, the diameter of the pad portion can be reduced, and the land portion protruding in a hook shape is provided in the inner layer portion of the interlayer connection via that becomes the component mounting pad portion. Then, the present inventors have found that the connection strength of the pad portion can be improved and completed the invention.

すなわち、本発明は、部品実装パッド部の表層部にランド部が存在せず、かつ当該部品実装パッド部において回路面及び層間接続ビア面が絶縁層面と同一平面上に形成されているパッケージ基板により上記課題を解決したものである。   That is, the present invention provides a package substrate in which no land portion exists in the surface layer portion of the component mounting pad portion, and the circuit surface and the interlayer connection via surface are formed on the same plane as the insulating layer surface in the component mounting pad portion. It solves the above problems.

また、本発明パッケージ基板は、上記層間接続ビアが内層部に鍔状に張出したランド部を有することを特徴とする。   In addition, the package substrate of the present invention is characterized in that the interlayer connection via has a land portion protruding in a hook shape on the inner layer portion.

また、本発明パッケージ基板は、上記部品実装パッド部が部品を収容するキャビティ構造体となっていることを特徴とする。   The package substrate of the present invention is characterized in that the component mounting pad portion is a cavity structure that accommodates components.

また、本発明パッケージ基板は、上記部品実装パッド部に部品が実装されていることを特徴とする。   The package substrate of the present invention is characterized in that a component is mounted on the component mounting pad portion.

また、本発明は、導体箔の片側にニッケルめっきを付着する工程と、当該ニッケルめっきの上に銅めっきを付着する工程と、当該銅めっき部のみを回路形成する工程と、当該銅めっき上に絶縁層と導体層とを交互に積層した後に、当該ニッケルめっき直上に層間接続ビアを形成する工程と、当該ニッケルめっきの剥離により該層間接続ビアを表層部とした部品実装パッド部を形成する工程とを含んでいるパッケージ基板の製造方法により上記課題を解決したものである。   The present invention also includes a step of attaching nickel plating to one side of the conductor foil, a step of attaching copper plating on the nickel plating, a step of forming a circuit only for the copper plating portion, and the copper plating. After alternately laminating insulating layers and conductor layers, a step of forming an interlayer connection via directly on the nickel plating, and a step of forming a component mounting pad portion using the interlayer connection via as a surface layer portion by peeling off the nickel plating The above-described problems are solved by a method for manufacturing a package substrate including:

また、本発明パッケージ基板の製造方法は、上記層間接続ビアを形成する工程において、内層部に鍔状に張出したランド部を形成することを特徴とする。   The method for manufacturing a package substrate of the present invention is characterized in that, in the step of forming the interlayer connection via, a land portion protruding in a hook shape is formed on the inner layer portion.

また、本発明パッケージ基板の製造方法は、上記部品実装パッド部を形成する工程において、当該部品実装パッド部を、部品を収容するキャビティ構造体とすることを特徴とする。   The method for manufacturing a package substrate of the present invention is characterized in that, in the step of forming the component mounting pad portion, the component mounting pad portion is a cavity structure that accommodates the component.

また、本発明パッケージ基板の製造方法は、上記部品実装パッド部の形成後、更に部品を実装する工程を有することを特徴とする。   Moreover, the manufacturing method of the package substrate of the present invention is characterized by further comprising a step of mounting a component after the formation of the component mounting pad portion.

本発明のパッケージ基板は、部品実装パッド部表層部にランド部を有しない構造となっているため、当該パッド部の小径化を実現することができ、しかも部品実装パッド部となる層間接続ビアの内層部に鍔状に張出したランド部が設けられているため、パッド部と絶縁層の接続強度を向上させることができる。しかも、実際に部品を実装する際には、部品実装パッド部が平坦面となっていると共に、キャビティ構造体となっているため、部品実装の歩留まりや信頼性をより向上させることができる。   Since the package substrate of the present invention has a structure that does not have a land portion on the surface layer portion of the component mounting pad portion, the pad portion can be reduced in diameter, and the interlayer connection via serving as the component mounting pad portion can be realized. Since the land portion projecting in a hook shape is provided on the inner layer portion, the connection strength between the pad portion and the insulating layer can be improved. In addition, when components are actually mounted, the component mounting pad portion has a flat surface and a cavity structure, so that the yield and reliability of component mounting can be further improved.

以下図面を使用して本発明の実施の形態を説明する。
また、本発明において特に重要なポイントを以下に示し、その優位点を順に説明する。
ポイント1):部品実装パッド部の小径化に適した構造
ポイント2):部品実装パッド部の高接続強度化に適した構造
ポイント3):部品実装パッド部の平坦化構造
ポイント4):部品実装パッド部のキャビティ構造
Embodiments of the present invention will be described below with reference to the drawings.
In addition, particularly important points in the present invention are shown below, and their advantages are described in order.
Point 1): Structure suitable for reducing the diameter of the component mounting pad part Point 2): Structure suitable for increasing the connection strength of the component mounting pad part Point 3): Flattening structure of the component mounting pad part Point 4): Component mounting Cavity structure of pad part

本発明のパッケージ基板の製造方法について、図2〜図4を用いて説明する。   A method for manufacturing a package substrate according to the present invention will be described with reference to FIGS.

まず、図2(a)に示したように、導体箔1として例えばベース銅箔を用意し、その片面に電解ニッケルめっき2を付着させて図2(b)に示した構造体を得る。次いで、得られた当該構造体の両面に電解銅めっき3を付着させて図2(c)に示した構造体を得る。次いで、図2(d)で示したように目的とする回路部4aを形成した後、ビルドアップ部を積層し、図2(e)に示される多層基板を得る。   First, as shown in FIG. 2 (a), for example, a base copper foil is prepared as the conductor foil 1, and electrolytic nickel plating 2 is attached to one surface thereof to obtain the structure shown in FIG. 2 (b). Next, electrolytic copper plating 3 is adhered to both surfaces of the obtained structure to obtain the structure shown in FIG. Next, as shown in FIG. 2D, the target circuit portion 4a is formed, and then the build-up portion is laminated to obtain the multilayer substrate shown in FIG.

次いで、図3(a)〜(d)に示したようにレーザにて非貫通穴7をあけ、フィルドビアめっき8処理した後、回路形成と共に、層間接続ビア9(底部ランドなし),10(底部ランドあり)を形成し、更に必要に応じ複数回の積層と共に、層間接続ビア9,10を形成して多層パッケージ基板を得る。尚、レーザによる非貫通穴7の形成は、非貫通穴7の底部がニッケルめっき2もしくは回路部(BVH受けランド)4bの直上部になるようにレーザ条件をコントロールして行なう。   Next, as shown in FIGS. 3A to 3D, after the non-through hole 7 is formed with a laser and filled via plating 8 is processed, the interlayer connection vias 9 (no bottom land) and 10 (bottom part) are formed along with circuit formation. And a plurality of times of lamination as necessary, and interlayer connection vias 9 and 10 are formed to obtain a multilayer package substrate. The non-through hole 7 is formed by laser by controlling the laser conditions so that the bottom of the non-through hole 7 is directly above the nickel plating 2 or the circuit part (BVH receiving land) 4b.

次いで、前記で得られた図3(d)に示した構造体の表面の導体層6に、図4(a)及び図4(b)に示したとおり回路部4aを形成し、ソルダーレジスト16を施す。次いで、図3(d)に示した構造体の裏面の銅めっき3に回路部を形成する。因に、ここでの回路形成は、図3(d)に示した構造体が表裏でその導体厚みが違うために、表裏を片面ごとに行なう。また、この裏面における回路形成の際に、前記図4(b)に示したように、部品実装パッド部を形成する部位の銅めっき3を残存せしめる。   Next, as shown in FIGS. 4A and 4B, the circuit portion 4a is formed on the conductor layer 6 on the surface of the structure shown in FIG. Apply. Next, a circuit portion is formed on the copper plating 3 on the back surface of the structure shown in FIG. Incidentally, the circuit formation here is performed for each side because the structure shown in FIG. 3D is front and back and the conductor thickness is different. Further, at the time of circuit formation on the back surface, as shown in FIG. 4B, the copper plating 3 in the portion where the component mounting pad portion is formed is left.

次いで、図4(b)に示された残存銅めっき3側の空いたスペースに、樹脂ないしプリプレグを塗布又は積層して充填し、図4(c)に示したキャビティ形成部11を形成する。その後、当該残存銅めっき3をエッチング除去して図4(c)に示した構造体を得る。   Next, resin or prepreg is applied or laminated to fill the vacant space on the side of the remaining copper plating 3 shown in FIG. 4B to form the cavity forming portion 11 shown in FIG. Thereafter, the remaining copper plating 3 is removed by etching to obtain the structure shown in FIG.

次いで、図4(c)に示されたニッケルめっき2の剥離を行ない、図4(d)に示したように、層間接続ビア9を表層部とした部品実装パッド部12を有する本発明のパッケージ基板を得る。斯くして得られた本発明のパッケージ基板への部品の実装は、図1(a)及び図1(b)に示したように行なわれる。而して、本発明のパッケージ基板は図1(a)に示したように、部品実装パッド部12において、回路部4a面及び層間接続ビア9面が絶縁層5面と同一平面上に形成され、平坦な構造となっていると共に、当該部品実装パッド部12は、キャビティ形成部11の存在によりキャビティ構造体となっている。   Next, the nickel plating 2 shown in FIG. 4C is peeled off, and, as shown in FIG. Get the substrate. The component mounting on the package substrate of the present invention thus obtained is performed as shown in FIGS. 1 (a) and 1 (b). Thus, in the package substrate of the present invention, as shown in FIG. 1A, in the component mounting pad portion 12, the surface of the circuit portion 4a and the surface of the interlayer connection via 9 are formed on the same plane as the surface of the insulating layer 5. The component mounting pad portion 12 has a cavity structure due to the presence of the cavity forming portion 11.

ポイント1):部品実装パッド部の小径化に適した構造   Point 1): Structure suitable for reducing the diameter of the component mounting pad

近年、高密度化される基板を背景とし、本発明では部品実装パッド部を小径化できる構造体としている。従来、部品実装パッド部の小径化は単純に当該パッド部を回路形成により小径化することが主に行なわれてきた。しかし、当該従来の手法を用いた場合、図6に示したように、界面にあたる接合部17において部品実装パッド部19a,19bが絶縁層5から剥がれて、剥離箇所18が形成され、基板としての品質を損なうこととなる。そのような背景を受け、本発明ではBVH構造の底部が表層開口部より小径であること及び部品実装パッド部の表層部にランド部が存在しないランドレス構造の2点について着目した。   In recent years, against the background of high-density boards, the present invention provides a structure capable of reducing the diameter of the component mounting pad portion. Conventionally, the component mounting pad portion has been mainly reduced in diameter by simply reducing the diameter of the pad portion by circuit formation. However, when the conventional method is used, as shown in FIG. 6, the component mounting pad portions 19 a and 19 b are peeled off from the insulating layer 5 at the bonding portion 17 corresponding to the interface, and a peeling portion 18 is formed. Quality will be impaired. In view of such a background, the present invention focused on two points: the bottom of the BVH structure is smaller in diameter than the surface layer opening, and the landless structure in which no land portion exists in the surface layer of the component mounting pad.

本発明者は、前記2点について具体化を考えた場合には、従来のBVH構造を支持媒体の上に形成し、加えて、必要となる多層構造は前記BVH構造の上方向に積み重ね、後に前記支持媒体を外すことが重要であると考えた。またその際に、前記2点目のランドレス構造を形成するために、前記支持媒体とBVH構造の界面部分には構造的に何も存在しないことが好ましいと考えた。   When the present inventor considers the above two points, the conventional BVH structure is formed on the support medium. In addition, the necessary multilayer structure is stacked in the upward direction of the BVH structure. We thought it important to remove the support medium. At that time, in order to form the second landless structure, it was considered preferable that nothing is structurally present at the interface between the support medium and the BVH structure.

そこで本発明では、前述の如く、支持媒体をニッケルめっき2(図2(b))とし、当該ニッケルの上方向に絶縁層5(図2(e))を積層し、次いで層間接続ビア9,10(図3(c))を設けることとした。また、目的とする部品実装パッド部の小径化のために、後にニッケルめっき2を剥離(図4(d))し、層間接続ビア9の底部側を表層部とし、当該層間接続ビア9の底部を部品実装パッド部12として使用することとした。   Therefore, in the present invention, as described above, the support medium is the nickel plating 2 (FIG. 2B), the insulating layer 5 (FIG. 2E) is laminated above the nickel, and then the interlayer connection vias 9, 10 (FIG. 3C) is provided. Further, in order to reduce the diameter of the target component mounting pad portion, the nickel plating 2 is peeled off later (FIG. 4D), the bottom side of the interlayer connection via 9 is used as the surface layer portion, and the bottom portion of the interlayer connection via 9 is formed. Was used as the component mounting pad portion 12.

このようにして得られた本発明の部品実装パッド部は、前記2点の小径であること及びランドレス構造であることを満たす構造体である。   The component mounting pad portion of the present invention thus obtained is a structure that satisfies the two small diameters and the landless structure.

ポイント2):部品実装パッド部の高強度化に適した構造   Point 2): Structure suitable for increasing the strength of the component mounting pad

図6は、部品実装パッド部19a,19bに部品を実装した状態を模式図的に示している。例えば、図6(a)では部品実装パッド部(平パッド構造)19aに、はんだペースト14を介し、部品15を実装した場合を示しており、当該部品実装パッド部19aと絶縁層5との界面にあたる接合部17が小径化することで、接合面積が小さくなり、当該部品実装パッド部19aと絶縁層5との密着箇所、すなわち接合部17が弱くなり、結果として図6(c)に示したように、前記部品の実装時や物理的な衝撃を受けた際に剥離箇所18を生じさせることがある。これは図6(d)〜図6(f)に示した部品実装パッド部(BVH構造)19bの場合でも同様であり、図6(f)に示したように剥離箇所18を生じさせることがある。つまり、部品実装パッド部を小径化した場合にパッド剥がれの不具合を生じる問題がある。   FIG. 6 schematically shows a state in which components are mounted on the component mounting pad portions 19a and 19b. For example, FIG. 6A shows a case where the component 15 is mounted on the component mounting pad portion (flat pad structure) 19a via the solder paste 14, and the interface between the component mounting pad portion 19a and the insulating layer 5 is shown. By reducing the diameter of the joint portion 17 corresponding to the contact portion, the joint area is reduced, and the contact portion between the component mounting pad portion 19a and the insulating layer 5, that is, the joint portion 17 is weakened. As a result, as shown in FIG. As described above, the peeled portion 18 may be generated when the component is mounted or when a physical impact is applied. The same applies to the component mounting pad portion (BVH structure) 19b shown in FIGS. 6D to 6F, and the peeled portion 18 may be generated as shown in FIG. 6F. is there. That is, when the component mounting pad portion is reduced in diameter, there is a problem of causing a problem of pad peeling.

図6に示したようなパッド剥がれ問題のように、部品実装パッド部を小径にすることで、パッド部の密着面積も小さくなるためにパッドが剥がれやすくなる。そこで本発明では、小径なパッドでも剥がれにくい、高い強度を有する構造について考えた。   As in the case of the pad peeling problem as shown in FIG. 6, by making the component mounting pad portion small in diameter, the contact area of the pad portion becomes small, so that the pad is easily peeled off. Therefore, in the present invention, a structure having high strength, which is difficult to peel off even with a small-diameter pad, has been considered.

その構造体を具体的にするために、本発明では、係止性に優れた鍔状のような張出構造体を部品実装パッド部の内層に設ければ、当該パッドの接続強度は向上すると考えた。それを図示すると、図1(a)内における層間接続ビア9の鍔状ランド部20が効果的である。この鍔状ランド部20は、部品実装パッド部の内層側の底部に位置し、絶縁層5との係止性に優れており、この構造であれば小径なパッドでも剥がれにくく、高い強度を部品実装パッド部に持たせることが可能になる。さらに、垂直方向へ引抜かれる際の耐久性も、従来の部品実装パッド部に比し、本発明の構造体の方が大きい。   In order to make the structure concrete, in the present invention, if a hook-like overhang structure having excellent locking properties is provided in the inner layer of the component mounting pad portion, the connection strength of the pad is improved. Thought. As shown in FIG. 1, the hook-shaped land portion 20 of the interlayer connection via 9 in FIG. 1A is effective. The hook-shaped land portion 20 is located at the bottom on the inner layer side of the component mounting pad portion, and has excellent locking properties with the insulating layer 5. With this structure, even a small-diameter pad is difficult to peel off and has high strength. The mounting pad portion can be held. Further, the durability of the structure according to the present invention is higher when it is pulled out in the vertical direction than the conventional component mounting pad portion.

ポイント3):部品実装パッド部の平坦化構造   Point 3): Flattened structure of component mounting pad

パッケージ基板への具体的な部品実装を行なった場合、部品実装箇所は平坦であることが部品実装の際の歩留まりや信頼性の向上という観点から好ましい。そこで本発明では、図4(c)に示す如く、ニッケルめっき2の平坦な構造を利用し、その平坦な部分を剥離することによって図4(d)に示したように、回路部4a面及び層間接続ビア9面が絶縁層5面と同一面上に形成され、平坦な構造体の部品実装パッド部12を形成した。   When specific component mounting is performed on the package substrate, it is preferable that the component mounting location is flat from the viewpoint of improving yield and reliability in mounting components. Therefore, in the present invention, as shown in FIG. 4 (c), the flat structure of the nickel plating 2 is used, and the flat portion is peeled off to remove the flat portion as shown in FIG. 4 (d). The surface of the interlayer connection via 9 was formed on the same surface as the surface of the insulating layer 5 to form the component mounting pad portion 12 having a flat structure.

ポイント4):部品実装パッド部付近に設けたキャビティ構造   Point 4): Cavity structure near the component mounting pad

また、本発明ではパッケージ基板へ具体的な部品実装を行なった場合、小型な部品を実装することを背景に置き、位置ずれなどを生じさせない利点として、図4(c)に示す如く、キャビティ形成部11を設け、部品実装パッド部12をキャビティ構造体とした。このキャビティ構造は、図4(a)から図4(c)において作成することが可能、すなわち基板の製造過程で形成できるために有利である。   Further, in the present invention, when a specific component is mounted on the package substrate, the advantage of preventing the occurrence of misalignment and the like is shown in FIG. The part 11 is provided, and the component mounting pad part 12 is a cavity structure. This cavity structure is advantageous because it can be created in FIGS. 4 (a) to 4 (c), that is, can be formed in the process of manufacturing the substrate.

以下実施例を挙げて、本発明を図2〜図4と共に更に説明する。   Hereinafter, the present invention will be further described with reference to FIGS.

まず、図2(a)に示したように、導体箔1としてベース銅箔(厚み250μm)を用意し、該導体銅箔1の片面にめっき保護テープ(又は感光性ドライフィルム)を張り付け、次いで電解ニッケルめっき2(目標厚み:5μm)を付着させた後に、前記めっき保護テープを剥がして、前記導体箔1の片面にニッケルめっき2を有する図2(b)に示した構造体を得た。   First, as shown in FIG. 2 (a), a base copper foil (thickness 250 μm) is prepared as the conductor foil 1, and a plating protective tape (or photosensitive dry film) is pasted on one side of the conductor copper foil 1, After the electrolytic nickel plating 2 (target thickness: 5 μm) was adhered, the plating protective tape was peeled off to obtain the structure shown in FIG. 2B having the nickel plating 2 on one side of the conductor foil 1.

次に、図2(c)に示したように電解銅めっき3(目標厚み:20μm)処理を前記図2(b)で得られたニッケルめっき2付着後の導体箔1の両面に行ない、図2(c)に示した構造体を得た。   Next, as shown in FIG. 2 (c), the electrolytic copper plating 3 (target thickness: 20 μm) treatment is performed on both surfaces of the conductor foil 1 after the nickel plating 2 obtained in FIG. 2 (b). The structure shown in 2 (c) was obtained.

次に、図2(d)に示したように、サブトラクティブ工法における回路形成方法にて、耐アルカリエッチング性のドライフィルムレジストを図2(c)で得られた構造体の両面にラミネートし、次いで、露光(条件:80mj/cm2)、現像(条件:30℃)を行ない、次いで回路形成部のアルカリエッチング(条件:40℃)を行ない、前記ドライフィルムレジストを剥離(条件:2.5vol%水酸化ナトリウム水溶液)し、目的とする回路部4aを形成した図2(d)に示した構造体を得た。 Next, as shown in FIG. 2 (d), an alkali etching resistant dry film resist is laminated on both sides of the structure obtained in FIG. 2 (c) by the circuit forming method in the subtractive construction method, Next, exposure (condition: 80 mj / cm 2 ) and development (condition: 30 ° C.) are performed, then alkali etching (condition: 40 ° C.) of the circuit forming portion is performed, and the dry film resist is removed (condition: 2.5 vol. % Sodium hydroxide aqueous solution) to obtain the structure shown in FIG. 2D in which the desired circuit portion 4a was formed.

次に、上記で得られた図2(d)に示す構造体の回路部4aに、積層前処理としてメック社製CZ表面処理を行ない、ビルドアップ部の絶縁層5となる日立化成社製の絶縁材料(「プリプレグMCL−E67」厚み60μm)及び導体層6となる三井金属社製のスタンダード銅箔材料(厚み12μm)を使用し、積層プレス(条件:昇温速度3.4℃/min、温度条件185℃、68分保持、圧力35kgf/cm2)して、図2(e)に示される多層パッケージ基板を得た。 Next, the circuit part 4a of the structure shown in FIG. 2 (d) obtained above is subjected to CZ surface treatment made by MEC as a pre-lamination process, and the insulating layer 5 of the build-up part is made by Hitachi Chemical Co., Ltd. Using an insulating material (“prepreg MCL-E67” thickness 60 μm) and a standard copper foil material (thickness 12 μm) manufactured by Mitsui Kinzoku Co., Ltd. to be the conductor layer 6, laminating press (condition: temperature increase rate 3.4 ° C./min, The temperature was maintained at 185 ° C. for 68 minutes and the pressure was 35 kgf / cm 2 ) to obtain the multilayer package substrate shown in FIG.

次に、図2(e)で得られた多層パッケージ基板を用い、図3(a)〜図3(d)に示したように、層間接続ビアの作成と複数層のビルドアップ部を積層した。すなわち、図2(e)で得られた多層パッケージ基板のビルドアップ部にレーザを照射し、非貫通穴7をあけ(図3(a))、フィルドビアめっき8処理(図3(b))した後、回路形成して層間接続ビア(底部ランドなし)9及び層間接続ビア(底部ランドあり)10を形成した(図3(c))。尚、レーザによる非貫通穴7の形成は、非貫通穴7の底部がニッケルめっき2もしくは回路部(BVH受けランド)4bの直上部になるようにレーザ条件をコントロールした。   Next, using the multilayer package substrate obtained in FIG. 2 (e), as shown in FIG. 3 (a) to FIG. . That is, the build-up part of the multilayer package substrate obtained in FIG. 2 (e) was irradiated with a laser to form non-through holes 7 (FIG. 3 (a)) and filled via plating 8 treatment (FIG. 3 (b)). Thereafter, a circuit was formed to form interlayer connection vias (without bottom lands) 9 and interlayer connection vias (with bottom lands) 10 (FIG. 3C). In forming the non-through hole 7 by laser, the laser conditions were controlled so that the bottom of the non-through hole 7 was directly above the nickel plating 2 or the circuit part (BVH receiving land) 4b.

因に、このレーザ加工には、レーザ機として三菱電機株式会社社製「ML605GTX(発振器:5100U−S1)」を使用すると共に、レーザ光の絞り用のマスクを使用し、絶縁層5を燃焼させるレーザエネルギーを調整した。また、このレーザ照射条件としては、周波数100Hz、パスル幅5μm、ショット数5、マスク3.0mm、エネルギー5.9mj、サイクル式パルスモードを使用し、狙いとするビア径は100μmとした。   For this laser processing, “ML605GTX (oscillator: 5100U-S1)” manufactured by Mitsubishi Electric Corporation is used as a laser machine, and the insulating layer 5 is burned by using a mask for narrowing the laser beam. The laser energy was adjusted. As the laser irradiation conditions, a frequency of 100 Hz, a pulse width of 5 μm, a shot number of 5, a mask of 3.0 mm, an energy of 5.9 mj, a cycle pulse mode was used, and a target via diameter was set to 100 μm.

また、前記のフィルドビアめっき8処理は、非貫通穴7をデスミア工程により洗浄した後に、フィルドビアめっき8として銅めっきにて充填する化学銅めっき及びビアフィリング用の電解銅めっき(目標厚み:20μm)を使用して行なった。   The filled via plating 8 treatment includes chemical copper plating and electrolytic copper plating for via filling (target thickness: 20 μm) filled with copper plating as the filled via plating 8 after the non-through holes 7 are washed by a desmear process. Used to do.

また、図3(c)後のビルドアップ部は、前記と同様に絶縁層5と導体層6を順次積層して形成した。   Further, the build-up portion after FIG. 3C was formed by sequentially laminating the insulating layer 5 and the conductor layer 6 in the same manner as described above.

次に、前記で得られた図3(d)の構造体の回路形成を図4(a)及び図4(b)に示す通りに行なった。ここでの回路形成は、図3(d)で得られた構造体が表裏の導体厚みが違うために、表裏を片面ごとに異なる回路形成条件で行なった。   Next, circuit formation of the structure of FIG. 3D obtained as described above was performed as shown in FIGS. 4A and 4B. The circuit formation here was performed under different circuit formation conditions for each side, because the structure obtained in FIG. 3D had different conductor thicknesses on the front and back sides.

初めに図4(a)に示したように、薄い導体層6側の回路形成を、サブトラクティブ工法における回路形成方法にて行なった。すなわち、ドライフィルムレジストを図4(a)に示した構造体の両面にラミネートし、次いで、露光(条件:80mj/cm2)、現像(条件:30℃)を行ない、塩化第二鉄液(条件:40℃)によりエッチングを行ない、目的とする回路部4aを形成し、図4(a)に示した構造体を得た。次いで、前記回路部4aが形成された面に、目的とするパッケージ基板の構造体に応じ、図4(b)に示したように液状の感光性ソルダーレジストを塗布し、露光(条件:350mj/cm2)、現像、ポストキュア(150℃、1h)を行ない、ソルダーレジスト16を形成した。 First, as shown in FIG. 4A, the circuit formation on the thin conductor layer 6 side was performed by the circuit formation method in the subtractive construction method. That is, a dry film resist is laminated on both surfaces of the structure shown in FIG. 4 (a), followed by exposure (condition: 80 mj / cm 2 ) and development (condition: 30 ° C.). Etching was performed under conditions (40 ° C.) to form the target circuit portion 4a, and the structure shown in FIG. 4A was obtained. Next, as shown in FIG. 4B, a liquid photosensitive solder resist is applied to the surface on which the circuit portion 4a is formed in accordance with the structure of the target package substrate, and exposure (condition: 350 mj / cm 2 ), development, and post cure (150 ° C., 1 h) were performed to form a solder resist 16.

次に、導体層として厚い銅めっき3側の回路形成を、サブトラクティブ工法における回路形成方法にて行なった。すなわち、耐アルカリエッチング性のドライフィルムレジストを図4(b)に示した構造体の両面にラミネートし、次いで、銅めっき3側を選択的に、露光(条件:70mj/cm2)、現像(条件:30℃)を行ない、アルカリエッチング液(条件:45℃)により、部品実装パッド部を形成する部位の銅めっき3を残存せしめて、銅めっき3のエッチングを行なった。その後、前記ドライフィルムレジストを剥離し、図4(b)に示した構造体を得た。 Next, the circuit formation on the side of the thick copper plating 3 as the conductor layer was performed by the circuit formation method in the subtractive construction method. That is, an alkali etching resistant dry film resist is laminated on both surfaces of the structure shown in FIG. 4B, and then the copper plating 3 side is selectively exposed (condition: 70 mj / cm 2 ) and developed ( The copper plating 3 was etched by leaving the portion of the copper plating 3 where the component mounting pad portion is to be formed with an alkaline etching solution (condition: 45 ° C.). Thereafter, the dry film resist was peeled off to obtain the structure shown in FIG.

次に、部品実装パッド部12をキャビティ構造体とするために、前記銅めっき3のエッチングにて溶融した回路形成部の空いたスペースにキャビティ形成部11を形成した。すなわち図4(b)における残存銅めっき3側の空いたスペースに、プリプレグを積層工法にて充填し、図4(c)に示されるキャビティ形成部11を形成した。その後、当該残存銅めっき3を前記エッチング条件にて溶融除去し、プリント配線板の片側にキャビティ構造を有する図4(c)に示した構造体を得た。   Next, in order to make the component mounting pad portion 12 into a cavity structure, the cavity forming portion 11 was formed in a space in which the circuit forming portion melted by the etching of the copper plating 3 was vacated. That is, the vacant space on the side of the remaining copper plating 3 in FIG. 4B was filled with the prepreg by the laminating method to form the cavity forming portion 11 shown in FIG. Thereafter, the remaining copper plating 3 was melted and removed under the above etching conditions to obtain a structure shown in FIG. 4C having a cavity structure on one side of the printed wiring board.

次に、図4(c)で得られた構造体の表面に露出するニッケルめっき2を、硝酸系のニッケルめっき剥離液にて剥離し、図4(d)に示した本発明パッケージ基板を得た。   Next, the nickel plating 2 exposed on the surface of the structure obtained in FIG. 4C is stripped with a nitric acid-based nickel plating stripper to obtain the package substrate of the present invention shown in FIG. It was.

斯くして得られた本発明のパッケージ基板を図1(a)に示したように、部品実装パッド部12を上面に配置し、当該部品実装パッド部12に、はんだペースト14を介して部品15を実装し、図1(b)に示した本発明パッケージ基板を得た。   As shown in FIG. 1A, the package substrate of the present invention thus obtained is arranged with the component mounting pad portion 12 on the upper surface, and the component mounting pad portion 12 is connected to the component 15 via the solder paste 14. The package substrate of the present invention shown in FIG. 1B was obtained.

試験例
本発明における部品実装用のパッド部は小径構造への対応が可能であり、加えてパッド部の接続強度値が高いという効果を奏する。そこで、従来パッケージ基板に比し、本発明パッケージ基板の斯かる効果がより優れていることを具体的に示すために、パッド引抜き強度値を測定し、従来パッケージ基板と本発明パッケージ基板との比較を行なった。
Test Example The pad portion for component mounting in the present invention can cope with a small-diameter structure, and in addition, has an effect that the connection strength value of the pad portion is high. Therefore, in order to specifically show that the effect of the package substrate of the present invention is superior to that of the conventional package substrate, the pad pull-out strength value is measured, and the comparison between the conventional package substrate and the package substrate of the present invention is performed. Was done.

パッド引抜き強度値の手順としては、初めに試験用の基板を用意した。従来パッケージ基板としては、図5(c)に示される構造体の基板を使用し、部品実装パッド部には平パッド構造(19a)とBVH構造パッド(19b)の2種類を用いた。また、本発明パッケージ基板としては、図1(a)に示される構造体の基板、すなわちキャビティ構造体の部品実装パッド部12を有するものを用いた。   As a procedure for the pad pull-out strength value, a test substrate was first prepared. As the conventional package substrate, the substrate having the structure shown in FIG. 5C was used, and two types of flat pad structure (19a) and BVH structure pad (19b) were used for the component mounting pad portion. In addition, as the package substrate of the present invention, a substrate having the structure shown in FIG. 1A, that is, a substrate having the component mounting pad portion 12 of the cavity structure was used.

また、部品実装パッド部の小径構造を意図して、パッドの大きさは、φ100μm、φ150μm及びφ200μmの3種類を使用し、その強度値を比較した。   In addition, with the intention of the small-diameter structure of the component mounting pad portion, three types of pads of φ100 μm, φ150 μm, and φ200 μm were used, and their strength values were compared.

測定に至る手順としては、前期試験用の部品実装パッド部に、はんだボールをリフロー加熱(加熱ピーク:240℃)にて搭載し、アークテック株式会社社製の万能型プルテスター(型式:BT2400)を使用し、アークテック株式会社社製の測定ピン(型式:BP−01−27L)を加温状態で前記はんだボールに埋め込みした後に、常温まで冷却させて、200μm/秒の速度で引抜き強度値を測定した。その結果を表1及び表2に示す。   As a procedure leading to the measurement, a solder ball is mounted on the component mounting pad part for the previous test by reflow heating (heating peak: 240 ° C.), and an all-purpose pull tester (model: BT2400) manufactured by Arctech Co., Ltd. A measurement pin (model: BP-01-27L) manufactured by Arctec Co., Ltd. was embedded in the solder ball in a heated state, cooled to room temperature, and pulled strength value at a speed of 200 μm / second. Was measured. The results are shown in Tables 1 and 2.

Figure 2006059863
Figure 2006059863

Figure 2006059863
Figure 2006059863

上記部品実装パッド部の引抜き測定結果より、本発明パッケージ基板における部品実装パッド部の強度値は、従来パッケージ基板における該測定値より約3倍の強度があることが確認された。   From the result of the above-mentioned pull-out measurement of the component mounting pad portion, it was confirmed that the strength value of the component mounting pad portion in the package substrate of the present invention is about three times stronger than the measurement value in the conventional package substrate.

この試験結果は本発明パッケージ基板における部品実装パッド部12の構造的な特徴より得られる結果である。すなわち、部品実装パッド部12における層間接続ビア9の鍔状ランド部20が絶縁層5と強固に係止する結果、引抜き強度値を向上させていることに起因する。   This test result is a result obtained from the structural characteristics of the component mounting pad portion 12 in the package substrate of the present invention. That is, this is because the hook-shaped land portion 20 of the interlayer connection via 9 in the component mounting pad portion 12 is firmly locked to the insulating layer 5 and, as a result, the pull-out strength value is improved.

而して、この試験結果は、本発明の背景技術で要求される部品実装のパッド部の小径化及びパッケージ基板としての実装面積の小スペース化を形成する際に有利であることを明確にしている。   Therefore, it is clarified that this test result is advantageous in forming a reduced diameter of a pad portion for component mounting and a reduced mounting area as a package substrate required in the background art of the present invention. Yes.

本発明のパッケージ基板に部品を実装した状態を示す概略断面説明図。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 本発明のパッケージ基板の製造例を示す概略断面工程説明図。The schematic cross-sectional process explanatory drawing which shows the manufacture example of the package substrate of this invention. 図2に引き続く本発明のパッケージ基板の製造例を示す概略断面工程説明図。The schematic cross-sectional process explanatory drawing which shows the manufacture example of the package board | substrate of this invention following FIG. 図3に引き続く本発明のパッケージ基板の製造例を示す概略断面工程説明図。FIG. 4 is a schematic cross-sectional process explanatory diagram illustrating a manufacturing example of the package substrate of the present invention subsequent to FIG. 3. 従来のパッケージ基板の製造例を示す概略断面工程説明図。The schematic cross-sectional process explanatory drawing which shows the example of manufacture of the conventional package substrate. 従来のパッケージ基板に部品を実装した場合の不具合を示す概略断面説明図。Schematic cross-sectional explanatory drawing which shows the malfunction at the time of mounting components on the conventional package substrate.

符号の説明Explanation of symbols

1:導体箔
2:ニッケルめっき
3:銅めっき
4a:回路部
4b:回路部(BVH受けランド)
5:絶縁層
6:導体層
7:非貫通穴
8:フィルドビアめっき
9:層間接続ビア(底部ランドなし)
10:層間接続ビア(底部ランドあり)
11:キャビティ形成部
12:部品実装パッド部
13:コア材料部
14:はんだペースト
15:部品
16:ソルダーレジスト
17:接合部
18:剥離箇所
19a:部品実装パッド部(平パッド構造)
19b:部品実装パッド部(BVHパッド構造)
20:鍔状ランド部
1: Conductor foil 2: Nickel plating 3: Copper plating 4a: Circuit portion 4b: Circuit portion (BVH receiving land)
5: Insulating layer 6: Conductor layer 7: Non-through hole 8: Filled via plating 9: Interlayer connection via (no bottom land)
10: Interlayer connection via (with bottom land)
11: Cavity forming part 12: Component mounting pad part 13: Core material part 14: Solder paste 15: Part 16: Solder resist 17: Joining part 18: Peeling part 19a: Component mounting pad part (flat pad structure)
19b: component mounting pad (BVH pad structure)
20: Sponge land

Claims (8)

部品実装パッド部の表層部にランド部が存在せず、かつ当該部品実装パッド部において回路面及び層間接続ビア面が絶縁層面と同一平面上に形成されていることを特徴とするパッケージ基板。   A package substrate, wherein a land portion is not present in a surface layer portion of a component mounting pad portion, and a circuit surface and an interlayer connection via surface are formed on the same plane as the insulating layer surface in the component mounting pad portion. 上記層間接続ビアが、内層部に鍔状に張出したランド部を有することを特徴とする請求項1に記載のパッケージ基板。   The package substrate according to claim 1, wherein the interlayer connection via has a land portion protruding in a hook shape on the inner layer portion. 上記部品実装パッド部が、部品を収容するキャビティ構造体となっていることを特徴とする請求項1又は2に記載のパッケージ基板。   The package substrate according to claim 1, wherein the component mounting pad portion is a cavity structure that accommodates a component. 上記部品実装パッド部に、部品が実装されていることを特徴とする請求項1〜3の何れか1項に記載のパッケージ基板。   The package substrate according to any one of claims 1 to 3, wherein a component is mounted on the component mounting pad portion. 導体箔の片側にニッケルめっきを付着する工程と、当該ニッケルめっきの上に銅めっきを付着する工程と、当該銅めっき部のみを回路形成する工程と、当該銅めっき上に絶縁層と導体層とを交互に積層した後に、当該ニッケルめっき直上に層間接続ビアを形成する工程と、当該ニッケルめっきの剥離により該層間接続ビアを表層部とした部品実装パッド部を形成する工程とを含んでいることを特徴とするパッケージ基板の製造方法。   A step of attaching nickel plating to one side of the conductor foil, a step of attaching copper plating on the nickel plating, a step of forming a circuit only on the copper plating portion, and an insulating layer and a conductor layer on the copper plating. After alternately laminating layers, a step of forming an interlayer connection via directly on the nickel plating and a step of forming a component mounting pad portion having the interlayer connection via as a surface layer by peeling of the nickel plating are included. A manufacturing method of a package substrate characterized by the above. 上記層間接続ビアを形成する工程において、内層部に鍔状に張出したランド部を形成することを特徴とする請求項5に記載のパッケージ基板の製造方法。   6. The method of manufacturing a package substrate according to claim 5, wherein, in the step of forming the interlayer connection via, a land portion protruding in a hook shape is formed on the inner layer portion. 上記部品実装パッド部を形成する工程において、当該部品実装パッド部を、部品を収容するキャビティ構造体とすることを特徴とする請求項5又は6に記載のパッケージ基板の製造方法。   7. The method of manufacturing a package substrate according to claim 5, wherein in the step of forming the component mounting pad portion, the component mounting pad portion is a cavity structure that accommodates the component. 上記部品実装パッド部の形成後、更に部品を実装する工程を有することを特徴とする請求項5〜7の何れか1項に記載のパッケージ基板の製造方法。   8. The method of manufacturing a package substrate according to claim 5, further comprising a step of mounting a component after the component mounting pad portion is formed.
JP2004237379A 2004-08-17 2004-08-17 Package substrate and its manufacturing method Pending JP2006059863A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011109152A (en) * 2011-03-09 2011-06-02 Internatl Business Mach Corp <Ibm> Printed wiring board and method of manufacturing the same
WO2011126973A3 (en) * 2010-04-06 2012-01-19 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
JP2012146793A (en) * 2011-01-11 2012-08-02 Shinko Electric Ind Co Ltd Wiring board and manufacturing method of the same
CN111490025A (en) * 2019-01-29 2020-08-04 矽品精密工业股份有限公司 Electronic package, package substrate thereof and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09148477A (en) * 1995-11-21 1997-06-06 Oki Electric Ind Co Ltd Semiconductor element package and its manufacture
JP2001068858A (en) * 1999-08-27 2001-03-16 Shinko Electric Ind Co Ltd Multilayer wiring board, manufacture thereof, and semiconductor device
JP2001185653A (en) * 1999-10-12 2001-07-06 Fujitsu Ltd Semiconductor device and method for manufacturing substrate
JP2003142617A (en) * 2001-10-31 2003-05-16 Shinko Electric Ind Co Ltd Package for semiconductor device
JP2004152884A (en) * 2002-10-29 2004-05-27 Shinko Electric Ind Co Ltd Semiconductor device, substrate therefor and its manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09148477A (en) * 1995-11-21 1997-06-06 Oki Electric Ind Co Ltd Semiconductor element package and its manufacture
JP2001068858A (en) * 1999-08-27 2001-03-16 Shinko Electric Ind Co Ltd Multilayer wiring board, manufacture thereof, and semiconductor device
JP2001185653A (en) * 1999-10-12 2001-07-06 Fujitsu Ltd Semiconductor device and method for manufacturing substrate
JP2003142617A (en) * 2001-10-31 2003-05-16 Shinko Electric Ind Co Ltd Package for semiconductor device
JP2004152884A (en) * 2002-10-29 2004-05-27 Shinko Electric Ind Co Ltd Semiconductor device, substrate therefor and its manufacturing method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011126973A3 (en) * 2010-04-06 2012-01-19 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US8319318B2 (en) 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US8507324B2 (en) 2010-04-06 2013-08-13 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
JP2012146793A (en) * 2011-01-11 2012-08-02 Shinko Electric Ind Co Ltd Wiring board and manufacturing method of the same
US8797757B2 (en) 2011-01-11 2014-08-05 Shinko Electric Industries Co., Ltd. Wiring substrate and manufacturing method thereof
JP2011109152A (en) * 2011-03-09 2011-06-02 Internatl Business Mach Corp <Ibm> Printed wiring board and method of manufacturing the same
CN111490025A (en) * 2019-01-29 2020-08-04 矽品精密工业股份有限公司 Electronic package, package substrate thereof and manufacturing method thereof

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