JP4973494B2 - Multilayer printed wiring board - Google Patents

Description

The present invention relates to a multilayer printed wiring board, and more particularly to a build-up multilayer printed wiring board that can be suitably used for a package substrate for mounting an IC chip.

As component mounting boards for mounting IC chips and other components, build-up type multilayer printed wiring boards (mainly the method of manufacturing printed wiring boards by additive method) and multilayer multilayer printed wiring boards for interlayer connection by via holes (Mainly, a method for producing a printed wiring board by a sub-tra method).
In a build-up type multilayer printed wiring board, an interlayer insulating resin is formed on both sides or one side of a core substrate having a through hole by a drill or the like, and via holes for interlayer conduction are opened by laser or photoetching. An interlayer resin insulating layer having holes is formed. If necessary, a roughened layer is formed on the inner wall of the interlayer insulating layer or via hole. A conductor layer is formed on the inner wall of the via hole by plating or the like, and after etching or the like, a pattern is formed on the interlayer insulating layer to form a conductor circuit. Furthermore, a build-up type multilayer printed wiring board can be obtained by repeatedly forming an interlayer insulating layer and a conductor layer.
In addition, in the build-up multilayer wiring board, a conductor layer (cover plating layer) covering the surface of the through hole is provided, a via hole is formed on the cover plating, and a filled via that fills the via hole with a conductor is formed. A so-called stacked via structure in which a filled via is provided immediately above the filled via is used.

On the other hand, in the multilayer multilayer printed wiring board, an opening (via hole) penetrating the insulating layer is formed in the copper-clad laminate by laser or drill, and a conductor layer is formed in the opening by plating, conductive paste or the like. A multilayer multilayer printed wiring board can be obtained by stacking a plurality of these substrates and laminating them sequentially or collectively by pressing or the like with the substrate as a unit.
Further, a filled via may be used as a via hole of this multilayer multilayer printed wiring board, or a stacked via for forming a filled via immediately above the filled via may be formed.

As a prior art of a build-up type multilayer printed wiring board, there is Patent Document 1, and as a prior art of a build-up type multilayer printed wiring board having filled vias, there is Patent Document 2. Moreover, there exists patent document 3 as a prior art of a multilayer multilayer printed wiring board.
JP 2001-127435 A Japanese Patent Laid-Open No. 11-251749 JP 2003-37366 A

Due to the demand for higher density of printed wiring boards, it is necessary to reduce L (line) / S (space) and to reduce the via hole diameter in order to increase the wiring density. In order to achieve higher density, a filled via that fills the through hole with a conductor or a stacked via structure in which a via is stacked is employed. As a result, the density of the area where the wiring is formed is increased.

When the via hole diameter is reduced, the connection area in the via hole between the upper conductor layer (referring to a conductor circuit on the interlayer insulating layer or a conductor circuit including a via hole) via the interlayer insulating layer and the lower conductor layer is also increased. Get smaller. The bond strength between the via hole and the land tends to decrease, and when a reliability test such as a heat cycle condition or a high temperature and high humidity condition is performed, the connection resistance tends to increase between the two.

Even if the via hole has a filled via or stacked via structure, if the connection area between the conductor formed in the via hole and the lower layer conductor (land) is small, the bonding force between the via hole and the land tends to decrease, and the heat cycle conditions When reliability tests were performed under conditions such as under and high temperature and high humidity conditions, there was a tendency for connection resistance to increase between the two.
In addition, the filled via and stacked via structures are easy to transmit thermal stress and stress generated at the time of impact. If the stress generated for this purpose is not buffered at the via hole and its periphery, problems such as cracks in the interlayer insulation layer and the conductor layer in the vicinity of the via hole are caused, and as a result, the electrical connectivity and reliability are deteriorated early. Sometimes it was a factor.

Here, in the build-up type multilayer printed wiring board or the multilayer multilayer printed wiring board, the via hole is formed by forming an electroless plating film and an electrolytic plating film in this order. Since the electroless plating film formed earlier has low ductility, it is considered that cracks and breaks are likely to occur in the electroless plating film. Further, when the printed wiring board is warped when an electronic component such as an IC chip is mounted, the electroless plating film cannot follow the warp, so the via hole is considered to be easily peeled off from the land.
Even if the diameter of the via hole is increased in consideration of the above, the connectivity and reliability of the via hole may be deteriorated.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a multilayer printed wiring board capable of ensuring via hole connectivity and reliability.

In order to solve the above-described problem, an interlayer insulating layer and an upper conductor layer are formed on a lower conductor layer provided on the surface of the core substrate, and the lower conductor layer and the upper conductor layer are connected via via holes. In an electrically connected multilayer printed wiring board,
In the connecting portion between the bottom portion of the via hole, Ri Contact said recess in the lower conductive layer side it is provided,
The lower conductor layer is technically characterized in that it is formed on a filled via formed in a core substrate .

In the connection part between the upper conductor layer and the lower conductor layer at the bottom of the via hole, a recess is provided on the lower conductor layer side, so the connection is higher than the upper surface position of the lower conductor layer, which is the conventional via hole connection part. The interface can be on the bottom. Originally, the thermal stress during heat shrinkage and the stress generated at the time of impact are concentrated, and this is the largest via hole connection, and when the position of the connection is the upper surface of the conventional lower conductor layer, the stress Since it is difficult to be buffered, a crack or the like is generated in the interlayer insulating layer or the conductor layer in the vicinity of the via hole, thereby reducing the connection reliability of the via hole. On the other hand, in the present application, the connection interface at the connection portion of the via hole is lower than the upper surface of the lower conductor layer. Therefore, the connection interface can be shifted downward from the point where stress is concentrated (upper surface position of the lower conductor layer), and breakage hardly occurs along the connection interface. On the other hand, since the stress generated at the connection interface can be buffered, cracks are hardly generated in the interlayer insulating layer and the conductor layer in the vicinity of the via hole, and the connection reliability of the via hole can be ensured. As a result, the manufactured printed wiring board can ensure resistance to thermal stress and resistance to impact.
Furthermore, even if the via hole diameter is reduced and the connection area at the via hole connection portion is reduced, the effect is the same, and the effect is not hindered by the size of the area.

In the connection portion between the bottom of the via hole and the lower conductor layer, the connection interface is shifted downward from the upper surface of the lower conductor layer. Originally, the thermal stress during heat shrinkage and the stress generated at the time of impact are concentrated, and this is the largest via hole connection, and when the position of the connection is the upper surface of the conventional lower conductor layer, the stress Since it is hard to be buffered, a crack or the like is generated in the interlayer insulating layer or the conductor layer in the via hole, and the connection reliability of the via hole is lowered. On the other hand, in the present application, the connection interface at the connection portion of the via hole is lower than the upper surface of the lower conductor layer. Therefore, the connection interface can be shifted downward from the point where stress is concentrated (upper surface position of the lower conductor layer), and breakage hardly occurs along the connection interface. On the other hand, since the stress generated at the connection interface can be buffered, cracks are hardly generated in the interlayer insulating layer and the conductor layer in the vicinity of the via hole, and the connection reliability of the via hole can be ensured. Moreover, the printed wiring board manufactured by this application can ensure the tolerance with respect to a thermal stress, and the tolerance at the time of an impact.
Furthermore, even if the via hole diameter is reduced and the connection area at the via hole connection portion is reduced, the effect is the same, and the effect is not hindered by the size of the area.

By shifting the filled via filled with metal downward from the upper surface of the lower conductor layer, the same effect as described above can be obtained. As a result, even if a via hole is formed with a filled via, cracks are unlikely to occur in the interlayer insulating layer and the conductor layer in the vicinity of the via hole, and the connection reliability of the via hole can be ensured. Moreover, the printed wiring board manufactured by this application can ensure the tolerance with respect to a thermal stress, and the tolerance at the time of an impact.

In the stacked via, the connection interface is shifted downward from the upper surface of the lower conductor layer at the connection portion between the bottom of the via hole and the lower conductor layer. Originally, the thermal stress during heat shrinkage and the stress generated at the time of impact are concentrated, and this is the largest via hole connection, and when the position of the connection is the upper surface of the conventional lower conductor layer, the stress Since it is hard to be buffered, cracks and the like are generated in the interlayer insulating layer and the conductor layer in the vicinity of the via hole, and the connection reliability of the via hole is reduced. On the other hand, in the present application, the connection interface can be shifted downward from the point where stress is concentrated (the upper surface position of the lower conductor layer), and breakage hardly occurs along the connection interface. On the other hand, since the stress generated at the connection interface can be buffered, cracks are hardly generated in the interlayer insulating layer and the conductor layer in the vicinity of the via hole, and the connection reliability of the via hole can be ensured. Moreover, the printed wiring board manufactured by this application can ensure the tolerance with respect to a thermal stress, and the tolerance at the time of an impact.
In the case of the stacked via structure, the maximum effect can be obtained by shifting the connection interface to the lower side of the upper surface of the lower conductor layer at the connection portion of the via hole located in the lowermost layer of the stack. The effect can be obtained by positioning the connection interface of any one of the via holes or the connection interface of all the via holes below the upper surface of the corresponding lower conductor circuit.

In the case where the dent and the shift are provided in the lower conductor layer, it is desirable that the size (diameter) of the dent is equal to or larger than the via hole diameter. As a result, the metal layer that is the upper conductor layer penetrates into the recess. In the upper layer conductor circuit, the metal layer is integrated inside the via hole and the lower layer conductor layer, and is configured to fit to the interlayer insulating layer. It becomes easy to secure the bonding strength in the via hole. Therefore, the electrical connectivity and reliability are not easily lowered. Moreover, since it is an integrated structure, it becomes easy to ensure drop resistance. Furthermore, it is more desirable that the size (diameter) of the recess is larger than the via hole diameter. Thereby, the via hole which is the upper conductor layer has a bowl shape. Since it has this shape, there are two characteristics. One is shifting the via hole connection downward. The other is that the side surface spreads outside the via hole, so that the resin layer and the via hole are fitted together. Thereby, it becomes easy to ensure electrical connectivity and reliability, and resistance to thermal stress and resistance to impact can be ensured.

By shifting the electroless plating layer with low via hole toughness below the upper surface of the lower conductor layer, defects such as cracks in the interlayer insulation layer and the conductor layer in the via hole are less likely to occur. Connection reliability can be ensured. Moreover, the printed wiring board manufactured by this application can ensure the tolerance with respect to a thermal stress, and the tolerance at the time of an impact.

The connection interface between the bottom of the via hole, the upper conductor layer, and the lower conductor layer is shifted downward by 2 μm or more from the upper surface of the lower conductor layer. For this reason, thermal stress such as heat shrinkage and stress generated at the time of impact are concentrated, and it is the top surface position of the lower conductor layer that maximizes, and the connection interface that is most susceptible to cracking is surely lower than the upper surface of the lower conductor layer. As a result, the connection interface can be shifted downward from the stress-concentrated position. As a result, defects such as cracks are less likely to occur in the interlayer insulation layer and the conductor layer in the vicinity of the via hole. Reliability can be ensured.
Moreover, the printed wiring board manufactured by this application can ensure the tolerance with respect to a thermal stress, and the tolerance at the time of an impact.

The connection interface between the upper conductor layer and the lower conductor layer at the bottom of the via hole is shifted by 3 μm or more from the upper surface of the lower conductor layer and downward from the upper surface of the lower conductor layer. For this reason, the connection interface that is most prone to cracking is surely below the upper surface of the lower conductor layer and the stress is concentrated more than the upper surface position of the lower conductor layer where the stress at the time of heat shrinkage and impact is maximized. As a result, it is less likely to cause defects such as breakage at the connection interface and cracks in the conductor layer near the interlayer insulating layer and via hole, thereby ensuring connection reliability of the via hole. Become. Here, since the displacement is 3 μm or more from the upper surface position of the lower conductor layer, the applied stress value is lowered, and the resistance can be ensured. On the other hand, even if the connection interface is displaced by 5 μm or more, the applied stress value does not decrease. However, if the lower conductor layer is recessed more than this, the lower conductor layer becomes thinner at the portion depending on the thickness of the lower conductor layer. In the concave portion of the lower conductor layer that is the part, cracks are likely to occur, and it may be difficult to ensure connectivity and the like.

Further, since the via hole has a bowl shape, the interlayer insulating layer and the via hole are in a fitted state, and the upper conductor layer and the lower conductor layer are easily joined. Therefore, it is easy to ensure connectivity and reliability.

[Example 1]
(Example 1-1)
First, the structure of the multilayer printed wiring board 10 which concerns on Example 1 of this invention is demonstrated with reference to FIGS. 8 shows a cross-sectional view of the multilayer printed wiring board 10 and FIG. 9 shows a state in which the IC chip 90 is attached to the multilayer printed wiring board 10 shown in FIG. As shown in FIG. 8, in the multilayer printed wiring board 10, a conductor circuit 34 is formed on the surface of the core substrate 30. The front surface and the back surface of the core substrate 30 are connected through a through hole 36. The through hole 36 includes a lid plating layer 36a constituting the through hole land and a side wall conductor layer 36b, and the side wall conductor layer 36b is filled with a resin filler 37. Formation of interlayer resin insulation layer 50 in which filled via 60 and conductor circuit 58 are formed on lid plating layer (through-hole land) 36a, interlayer resin insulation layer 150 in which filled via 160 and conductor circuit 158 are formed, and filled via 260 An interlayer resin insulation layer 250 is disposed. A solder resist layer 70 is formed above the filled via 260, and bumps 78 U and 78 D made of solder are formed on the filled via 260 constituting the solder pad via the opening 71 of the solder resist layer 70. .

As shown in FIG. 9, the solder bumps 78 </ b> U on the upper surface side of the multilayer printed wiring board 10 are connected to the lands 92 of the IC chip 90. On the other hand, the lower solder bump 78D is connected to the land 96 of the daughter board 94.

The lid plating layer 36a, filled via 60, filled via 160, filled via (solder pad) 260, and bump 78U made of solder in the circle C in FIG. 8 are shown enlarged in FIG.
A recess 36h is provided on the side of the lid plating layer 36a at the connecting portion between the bottom of the lowermost filled via 60 having a stacked via structure and the lid plating layer (lower conductor layer) 36a. That is, at the connection portion between the bottom of filled via 60 and lid plating layer 36a, the connection interface between the upper conductor layer and the lid plating layer (lower conductor layer) is deeper than the upper surface of lid plating layer (lower conductor layer) 36a. It is shifted by d1 minutes. In addition, the recess 36h has a k1 partial diameter wider than the bottom of the via hole (the diameter of the via hole on the top surface of the lid plating layer 36a).

In the multilayer printed wiring board of Example 1, the connection interface between the upper conductor layer and the lower conductor layer is the upper surface of the lid plating layer 36a at the connection portion between the bottom of the lowermost filled via 60 and the lid plating layer (lower conductor layer) 36a. Since the depth d1 is shifted further downward, compared to the case where the connection interface is formed at the upper surface position of the lid plating layer 36a, the connection interface is on the lower side, and the connection interface is moved from the position where stress is concentrated. As a result, breakage at the connection interface can be prevented. In addition, defects such as cracks are less likely to occur in the interlayer insulating layer and the conductor layer near the via hole, and the connection reliability of the via hole can be ensured. Moreover, the printed wiring board manufactured by this application can ensure the tolerance with respect to a thermal stress, and the tolerance at the time of an impact.
Further, since the connection interface between the upper conductor layer and the lower conductor layer is shifted by the width k1 in the outer peripheral direction of the lid plating layer 36a, the metal layer of the upper conductor circuit penetrates into the via hole and the recess. In the upper layer conductor circuit, the metal layer is integrated inside the via hole and the lower layer conductor layer, and is configured to fit to the interlayer insulating layer. It becomes easy to secure the bonding strength in the via hole. Therefore, the electrical connectivity and reliability are not easily lowered. Moreover, since it is an integrated structure, it becomes easy to ensure drop resistance.

Similarly, a recess 60h is provided on the lowermost filled via 60 side at the connection portion between the bottom of the filled via 160 and the lowermost filled via 60 that are located in the middle layer of the stacked via structure. That is, at the connection portion between the bottom of filled via 160 and filled via 60, the connection interface between the middle layer filled via conductor layer and the lowermost filled via conductor layer is deeper below the upper surface of the lowermost filled via 60 conductor layer. It is shifted by d2. Further, the uppermost filled via 260 and the middle filled via 160 are similarly provided with a recess 160 h in the conductor layer of the middle filled via 160, and the conductor layer of the uppermost filled via 260 and the conductor layer of the middle filled via 160 are arranged. Are connected by shifting the connection interface by a depth d3 from the upper surface of the conductor layer of the filled via 160 in the middle layer.
The lid plating layer (lower conductor layer) 60a is shifted by k2 from the bottom of the via hole. Further, the recess 60h has a k2 partial diameter wider than the bottom of the via hole 160 (the diameter of the via hole 160 at the upper surface position of the via hole 60). Similarly, the recess 160h has a diameter k3 wider than the bottom of the via hole 260 (the diameter of the via hole 260 at the upper surface position of the via hole 160).

In the multilayer printed wiring board according to the first embodiment, the connection interface between the bottom filled filler via 60 and the bottom filled filler via 60 is connected to the filled via 60 at the connection between the bottom filled via 60 and the bottom filled via 60. Since the depth d2 is shifted downward from the upper surface, the connection interface can be shifted from the position where stress is concentrated (the upper surface position of the filled via), and breakage at the connection interface is difficult to occur. As a result, cracks are hardly generated in the interlayer insulating layer and the conductor layer in the vicinity of the via hole, and the connection reliability of the via hole can be ensured. Moreover, the printed wiring board manufactured by this application can raise the tolerance with respect to a thermal stress, and the tolerance at the time of an impact.

Further, since the connection interface between the upper conductor layer and the lower conductor layer is shifted by the width k2 in the outer peripheral direction of the lid plating layer 60, the metal layer of the upper conductor circuit enters into the via hole and the recess. In the upper layer conductor circuit, the metal layer is integrated inside the via hole and the lower layer conductor layer, and is configured to fit to the interlayer insulating layer. It becomes easy to secure the bonding strength in the via hole. Therefore, the electrical connectivity and reliability are not easily lowered. Moreover, since it is an integrated structure, it becomes easy to ensure drop resistance.
As a result, the connection reliability between the lowermost filled via 60 and the middle level filled via 160 is enhanced, and similarly, the connection reliability between the middle level filled via 160 and the uppermost filled via 260 can be ensured.

Here, since the filled vias 60 and 160 are filled with a metal, unlike a via hole (non-filled via shape) filled with resin, stress hardly escapes inside. In the first embodiment, it is possible to ensure the connection reliability of the via hole by providing the concave portion on the conductor layer side which is the filled via corresponding to the lower layer of the filled via of all the filled vias in the inner layer.
Moreover, the tolerance with respect to a thermal stress and the tolerance at the time of an impact can be improved.

Furthermore, it is desirable that the recesses have a size (diameter) equal to or larger than the via hole on the side of the lower circuit connected to each via hole. That is, the end of the recess is displaced. As a result, the metal layer of the upper conductor circuit enters the via hole and the recess. In the upper layer conductor circuit, the metal layer is integrated inside the via hole and the lower layer conductor layer, and is configured to fit to the interlayer insulating layer. It becomes easy to secure the bonding strength in the via hole. Therefore, the electrical connectivity and reliability are not easily lowered. Moreover, since it is an integrated structure, it becomes easy to ensure drop resistance.

In the first embodiment, the filled via 60, the filled via 160, and the filled via 260 include the electroless plating layer 52 and the electrolytic plating layer 56. The electroless plating layer 52 contains impurities and tends to be more fragile than the electrolytic plating layer 56. By shifting the lower surface of the electroless plating layer 52 with low toughness of the filled vias 60 and 160, which are the inner layers, downward from the upper surface of the lower filled via or the upper surface of the lid plating layer 36a, the stress is concentrated from the position. And breakage at the electroless plating layer 52 can be prevented. As a result, defects such as cracks are less likely to occur in the interlayer insulating layer and the conductor layer near the via hole, and the connection reliability of the via hole can be ensured. Moreover, the tolerance with respect to a thermal stress and the tolerance at the time of an impact can be improved.

Furthermore, it is desirable that the concave portion be equal to or larger than the via hole on the lower circuit side connected to each via hole. That is, the end of the recess is displaced. As a result, the metal layer of the upper conductor circuit enters the via hole and the recess. In the upper layer conductor circuit, the metal layer is integrated inside the via hole and the lower layer conductor layer, and is configured to fit to the interlayer insulating layer. It becomes easy to secure the bonding strength in the via hole. Therefore, the electrical connectivity and reliability are not easily lowered. Moreover, since it is an integrated structure, it becomes easy to ensure drop resistance.

Here, it is desirable that the connection interface between the bottom of the upper layer filled via and the lower layer filled via or the lower layer filled via and the lid plating layer 36a is shifted by 2 μm or more below the upper surface of the lower layer filled via or the lid plating layer 36a. By setting the thickness to 2 μm, the connection interface can be disposed below the upper surface of the lower conductor layer even when the electroless plating thickness, the thickness of the lower conductor layer, and the like are taken into consideration. Therefore, as compared with the case where the connection interface is positioned on the upper surface of the lower filled via or the lid plating layer 36a, the connection interface is surely on the lower side, and the fracture at the connection interface is eliminated. As a result, the interlayer insulating layer and the via hole Problems such as cracks are less likely to occur in the nearby conductor layer, and it is possible to ensure connection reliability of the via hole. Moreover, the tolerance with respect to a thermal stress and the tolerance at the time of an impact can be improved.
On the other hand, if it is less than 2 μm from the upper surface position of the lower layer filled via or the lid plating layer 36a, the buffering of stress may be hindered depending on the plating thickness to be used and the thickness of the conductor layer on the lower layer side, thereby improving the via hole connectivity. In some cases, resistance to thermal stress and resistance to impact cannot be increased.

More preferably, the connection interface between the upper conductor layer and the lower conductor layer is preferably shifted to the lower side by 3 μm or more from the upper surface of the conductor layer of the lower filled via and lid plating layer 36a.
That is, it has been experimentally proved that a displacement of 3 μm or more from the upper surface of the conductor layer of the lower filled via or the cover plating layer 36a lowers the stress value applied from the outside or the inside. Resistance can be increased. On the other hand, even if it is displaced by 5 μm or more, it is difficult to lower the stress value applied from the outside or the inside. In other words, a displacement of 5 μm becomes a limit point for lowering the stress value. If the lid plating layer 36a is recessed beyond 5 μm, depending on the thickness of the lower conductor layer, the lid plating layer 36a may become thin at that portion, and the lower layer starts from the position of the tip of the recess. The conductor layer may easily cause problems such as cracks. It is difficult to further improve the via hole connectivity.

As a result of the stress analysis, in the stacked filled via, the stress value is highest in the lowermost filled via. In the first embodiment, the connection interface is shifted downward from the upper surface of the lid plating layer 36a at the connection portion between the bottom surface of the three-tiered bottom layer filled via 60 and the lid plating layer 36a. For this reason, the stress concentration point can be shifted, cracks in the conductor layer in the vicinity of the interlayer insulating layer and via hole are hardly generated, via hole connectivity can be improved, and resistance to thermal stress and at the time of impact It is possible to increase the resistance.

Here, in Example 1, since the solder 78U and 78D use lead-less solder (Sn / Ag / Cu = 65 / 32.5 / 2.5), the toughness is low as compared with the lead solder, Solder is easy to peel from the solder pad.

Here, the result of simulating the stress applied during the filled via 60 heat cycle will be described.
Here, 3D thermal stress simulation by the finite element method (FEM) was performed. When a material with remarkable plasticity and creep properties such as solder is included in the analysis structure, nonlinear thermal stress simulation considering the plasticity and creep properties is required. Using a multi-scaling (sub-modeling) method that analyzes the mesh and uses the displacement calculated from it as the boundary condition of the sub-model divided by the fine mesh, and performs precise analysis of the problem area. The thermal stress at the time of the thermal shock test applied to the micro via of the density organic package was analyzed. That is, the Coarse model of the package is analyzed, the displacement is set as a sub-model boundary condition, and the nonlinear thermal stress analysis is performed under the thermal shock test conditions of −55 ° C. to Comparative Example 5 ° C. in consideration of the plasticity of the solder. It was.

FIG. 17 shows an arrangement example of filled vias subjected to stress analysis. In the arrangement example of FIG. 17A, the lower layer filled via 3rdV, the middle layer filled via 2ndV, and the upper layer filled via 1stV are arranged so as to be displaced. Similarly, the arrangement example of FIG. 17B and the arrangement of FIG. In the arrangement example, the lower filled via 3rdV, the middle filled via 2ndV, and the upper filled via 1stV are arranged so as to be displaced. Here, the difference between the arrangement example of FIG. 17A and the arrangement example of FIG. 17B is that in FIG. 17A, the conductor circuits 1stC, 2ndC, and 3rdC are arranged away from the filled via, and FIG. In B), they are located close to each other. Further, the difference between the arrangement example of FIG. 17A and the arrangement example of FIG. 17E is that in FIG. 17A, the middle filled via 2ndV and the upper filled via 1stV are laterally arranged with respect to the lower filled via 3rdV. While the displacement is large and the influence of the stress is small, the displacement amount is small in FIG. 17E and the influence of the stress is greatly received.

In the arrangement examples of FIGS. 17C and 17D, the lower layer filled via 3rdV, the middle layer filled via 2ndV, and the upper layer filled via 1stV are arranged on a straight line. Here, in FIG. 17C, the conductor circuits 1stC, 2ndC, and 3rdC are arranged close to the filled via, and in FIG. 17B, they are arranged apart from each other.

FIG. 18 shows the result of simulating the stress applied to the left and right points at the lower end of the lower layer filled via 3rdV, the middle layer filled via 2ndV, and the upper layer filled via 1stV.
Here, the stress value in the arrangement example of FIG. 17C and FIG. 17D of the three-tier stack is higher than that in the arrangement example of FIG. 17A and FIG. 17B, and the upper filled via 1stV. It can be seen that the stress value applied to the middle layer filled via 2ndV is larger than that, and the stress value applied to the lower layer filled via 3rdV is larger than that of the middle layer filled via 2ndV. That is, in the stacked filled vias, the stress value increases as it goes down.

On the other hand, in the arrangement example shown in FIG. 17E, since the displacement amount of the middle filled via 2ndV and the upper filled via 1stV is small in the lateral direction with respect to the lower filled via 3rdV, the lower filled via 3rdV is greatly affected by the mutual stress. The stress value applied to is increased.

By applying the configuration of the first embodiment to the filled via having a high stress value found by the above-described simulation, it is possible to prevent the filled via from being broken by the stress generated at the time of thermal contraction.

FIG. 19 shows the result of simulating the stress value applied to the lower end of the middle layer filled via 2ndV. FIG. 19A is a schematic diagram of the middle filled via 2ndV, and FIG. 19B is a graph showing simulation values.
Here, at the upper surface position (0 μm) of the lower filled via 3rdV, 312.7 MPa is added to the lower right end of the middle filled via 2ndV, and 245.2 MPa is added to the lower left end. Here, the value on the left side is low due to the influence of the lower layer filled via 3rdV on the right side. At a position 1 μm lower than the upper surface position (−1 μm), a stress of 220.6 MPa is applied on the right side and 185.3 MPa on the left side. At a position 2 μm lower than the upper surface position (−2 μm), a stress of 99.2 MPa is applied on the right side and 108.8 MPa on the left side. At a position 3 μm lower than the upper surface position (−3 μm), 93.6 MPa is applied on the right side and 92.4 MPa is added on the left side. At a position 4 μm lower than the upper surface position (−4 μm), 74.4 MPa is added on the right side and 75.8 MPa is added on the left side. At a position 5 μm lower than the upper surface position (−5 μm), 73.6 MPa is added on the right side and 74.6 MPa is added on the left side.
At a position 6 μm lower than the upper surface position (−6 μm), 73.7 MPa is added on the right side and 74.4 MPa is added on the left side.

From the above simulation results, the connection interface between the bottom of the upper filled via, the lower filled via, and the lid plating layer 36a is shifted down by 2 μm or more from the upper surface of the lower filled via and lid plating layer 36a to about 100 MPa required for the via hole. It became clear that the stress value could be reduced. Furthermore, it has been found that the stress value can be further reduced by lowering the connection interface from 3 μm to 5 μm. However, it has been found that the stress value does not decrease even if the connection interface is lowered beyond 5 μm.

In the first embodiment described above, the three-layer stack via is formed. However, even if it is a two-layer stack via or a stack via having four or more layers, the connection interface is similarly formed as a lower filled via and a lid plating layer. The same effect can be obtained by shifting downward by 2 μm or more from the upper surface of the substrate.

Further, in Example 1 described above, filled vias 60, 160, and 260 are formed by the electroless plating film 52 and the electrolytic plating film 56, but the same effect can be obtained when a filled via is formed by a conductor such as sputtering or paste. Have. Also, for example, a combination of conductor layers of different plating methods such as upper layer: electrolytic plating film, middle layer: electroless plating film, lower layer electrolytic plating film has the same effect.

Next, a method for manufacturing the multilayer printed wiring board 10 described above with reference to FIG. 8 will be described with reference to FIGS.
(1) Copper-clad laminate 30A in which a 5-250 μm copper foil 32 is laminated on both surfaces of an insulating substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.2-0.8 mm. As a starting material (FIG. 1A). First, this copper-clad laminate is drilled to form through holes 16 (FIG. 1 (B)), electroless plating treatment and electrolytic plating treatment (plating solution and conditions described later (step (13), ( 15))), and the side wall conductor layer 36b of the through hole 36 was formed (FIG. 1C). The opening diameter of the through holes 16 was 0.1 to 0.25 mmΦ according to the selection of the drill, and the pitch was 0.15 to 0.575 mm.

(2) The substrate 30 on which the through hole 36 is formed is washed with water and dried, and then an aqueous solution containing NaOH (10 g / l), NaClO ₂ (40 g / l), Na ₃ PO ₄ (6 g / l) is blackened. Blackening treatment (oxidation bath) and reduction treatment using an aqueous solution containing NaOH (10 g / l) and NaBH ₄ (6 g / l) as a reduction bath are performed on the side wall conductor layer 36b and the surface of the through hole 36. A roughened surface 36α is formed (FIG. 1D).

(3) Next, a filler 37 containing copper particles having an average particle diameter of 10 μm (non-conductive hole-filling copper paste made by Tatsuta Electric Wire, trade name: DD paste) is filled into the through-holes 36 by screen printing, and dried. Curing is performed (FIG. 1E). In this method, a through-hole is filled by applying it by a printing method on a substrate on which a mask having an opening in the through-hole portion is placed, and then dried and cured.

Subsequently, the filler 37 protruding from the through hole 36 is removed by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku), and further, buff polishing for removing scratches due to this belt sander polishing is performed. The surface of the substrate 30 is flattened (see FIG. 2A). In this way, the substrate 30 is obtained in which the side wall conductor layer 36b of the through hole 36 and the resin filler 37 are firmly adhered via the roughened layer 36α.

(4) A palladium catalyst (manufactured by Atotech) is applied to the surface of the substrate 30 flattened in (3), and electroless copper plating is performed, thereby forming an electroless copper plating film 23 having a thickness of 0.6 μm. (See FIG. 2B).

(5) Next, electrolytic copper plating is performed under the following conditions to form an electrolytic copper plating film 24 having a thickness of 15 μm, thickening a portion to become the conductor circuit 34, and a filler 37 filled in the through hole 36. A portion to be a cover plating layer (through hole land) is formed (FIG. 2C).
(Electrolytic plating aqueous solution)
Sulfuric acid 180 g / l
Copper sulfate 80 g / l
Additive (product name: Kaparaside GL, manufactured by Atotech Japan)
1 ml / l
[Electrolytic plating conditions]
Current density 1A / dm ²
Time 30 minutes Temperature Room temperature

(6) A commercially available photosensitive dry film is pasted on both surfaces of the substrate 30 on which the conductor circuit and the lid plating layer are formed, and a mask having a pattern is placed on the substrate 30 and exposed at 100 mJ / cm ² , 0.8 Development processing is performed with% sodium carbonate to form an etching resist 25 having a thickness of 15 μm (FIG. 2D).

(7) The portions of the plating films 23 and 24 and the copper foil 32 where the etching resist 25 is not formed are dissolved and removed with an etching solution containing cupric chloride as a main component. The lid plating layer 36a covering the independent conductor circuit 34 and the filler 37 is formed by peeling off with% KOH (FIG. 3A). This is a so-called tenting method.

(8) Next, a roughened layer (concave / convex layer) 34β having a thickness of 2.5 μm was formed on the surface of the lid plating layer 36a covering the conductor circuit 34 and the filler 27 with an etching solution. (FIG. 3B).

(9) On both surfaces of the substrate, a resin film for interlayer resin insulation layer (made by Ajinomoto Co., Inc .: trade name; ABF-45SH) 50γ that is slightly larger than the substrate is placed on the substrate, pressure 0.45 MPa, temperature 80 ° C., After temporarily crimping and cutting under the condition of a crimping time of 10 seconds, an interlayer resin insulating layer was formed by pasting using a vacuum laminator apparatus by the following method (FIG. 3C). That is, the resin film for an interlayer resin insulation layer was subjected to main pressure bonding on a substrate under conditions of a degree of vacuum of 67 Pa, a pressure of 0.47 MPa, a temperature of 85 ° C., and a pressure bonding time of 60 seconds, and then thermally cured at 170 ° C. for 40 minutes.

(10) Next, with a CO2 gas laser with a wavelength of 10.4 .mu.m, a beam diameter of 4.0 mm, a top hat mode, a pulse width of 3 to 30 .mu.s, a mask through-hole diameter of 1.0 to 5.0 mm, and 1-3. Via hole openings 51 were formed in the interlayer resin insulation layer 50 under the shot conditions (FIG. 3D). Here, in the interlayer resin insulating layer 50, the above laser conditions were adjusted so that the diameter of the bottom of the filled via was φ50 μm.

(11) Immerse the substrate with the filled via openings 51 in an 80 ° C. solution containing 60 g / l permanganic acid for 10 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulation layer 50. Thus, a roughened surface 50α was formed on the surface of the interlayer resin insulating layer 50 including the inner wall of the filled via opening 51 (FIG. 4A). The opening 51 shown by C1 in the drawing is enlarged and shown in FIG.

(12) Next, a recess 36 h having a depth of 3 μm is formed on the surface of the lid plating layer 36 a exposed through the opening 51 with an etching solution mainly containing cupric chloride. This depth is set to a desired value by adjusting the time of light etching (FIG. 4B). The opening 51 shown by C2 in the figure is enlarged and shown in FIG.

The substrate after the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and then washed with water.
Further, a catalyst was attached to the surface of the interlayer resin insulation layer and the inner wall surface of the filled via opening by applying a palladium catalyst to the surface of the substrate subjected to the roughening treatment (roughening depth: 3 μm). That is, the substrate was immersed in a catalyst solution containing palladium chloride (PbCl ₂ ) and stannous chloride (SnCl ₂ ), and the catalyst was applied by depositing palladium metal.

(13) Next, the substrate provided with the catalyst is immersed in an electroless copper plating aqueous solution (Sulcup PEA) manufactured by Uemura Kogyo Co., Ltd., and the electroless copper having a thickness of 0.3 to 3.0 μm is formed on the entire rough surface. A plating film was formed, and a substrate having an electroless copper plating film 52 of 2 μm formed on the surface of the interlayer resin insulating layer 50 including the inner wall of the via hole opening 51 was obtained (FIG. 4C).
[Electroless plating conditions]
45 minutes at a liquid temperature of 34 degrees

(14) A commercially available photosensitive dry film is attached to the substrate on which the electroless copper plating film 52 is formed, a mask is placed, exposed at 110 mJ / cm @ 2, and developed with a 0.8% aqueous sodium carbonate solution. Thus, a plating resist 54 having a thickness of 25 μm was provided (FIG. 4D).

(15) Next, the substrate 30 is washed and degreased with 50 ° C. water, washed with 25 ° C. water and further washed with sulfuric acid, and then subjected to electrolytic plating under the following conditions to form an electrolytic plated film 56. The filled via 60 and the conductor circuit 58 made of the electroless plating film 52 and the electrolytic plating film were provided (FIG. 5A).
[Electrolytic plating solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
Leveling agent 50 mg / l
Brightener 50 mg / l
[Electrolytic plating conditions]
Current density 1 A / dm ²
Time 70 minutes Temperature 22 ± 2 ℃
A portion indicated by C3 in FIG. 5A is shown in FIG. The filled via 60 in FIG. 11C is further enlarged and shown in FIG. Here, the electroless plating layer 52 having a thickness of 2 μm of the filled via 60 is provided in the recess 36h having a depth of 3 μm, so that the electroless plating layer 52 having low toughness is provided below the upper surface of the lid plating layer 36a. is there. Thereby, it becomes difficult to produce a crack between filled via 60 and lid plating layer 36a, and resistance to thermal stress and resistance at impact can be increased.

(16) Further, after removing the plating resist 54 with 5% KOH, the electroless plating film under the plating resist is etched and removed with a mixed solution of sulfuric acid and hydrogen peroxide to remove an independent conductor circuit. 58 and filled via 60 (FIG. 5B).

(17) Next, the same processing as in the above (4) was performed to form a roughened surface 58α on the surfaces of the conductor circuit 58 and the filled via 60. The thickness of the upper conductor circuit 58 was 15 μm (FIG. 5C).

(18) By performing the steps (9) to (11), an interlayer insulating layer 150 having an opening 151 is formed on the filled via 60 and the conductor circuit 58 (FIG. 5D). An opening 151 indicated by C4 in the figure is enlarged and shown in FIG.

(19) Next, recessed portions 60 h and 58 h having a depth of 3 μm are formed on the surface of the filled via 60 and the conductor circuit 58 exposed by the opening 151 with an etchant containing cupric chloride as a main component. This depth is set to a desired value by adjusting the time of light etching (FIG. 6A). The opening 51 shown by C5 in the figure is enlarged and shown in FIG.

(20) By performing the steps (13) to (17), the interlayer insulating layer 150 having the filled via 160 and the conductor circuit 158 is formed (FIG. 6B). The filled via 160 indicated by C6 in the drawing is enlarged and shown in FIG. The filled via 160 is further enlarged and shown in FIG.
Here, the electroless plating layer 52 having a thickness of 2 μm of the filled via 160 is provided in the recess 60 h having a depth d 2 (3 μm), so that the electroless plating layer 52 having low toughness is provided below the upper surface of the filled via 60. It is. Thereby, it becomes difficult to produce a crack between the filled via 60 and the filled via 160, and resistance to thermal stress and resistance at impact can be increased.

(21) By repeating the steps (19) and (20), an interlayer insulating layer 250 having an upper filled via 260 was formed to obtain a multilayer wiring board (FIG. 6C).

(22) Next, after applying a commercially available solder resist composition 70 to a thickness of 20 μm on both sides of the multilayer wiring board and performing a drying treatment at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, A photomask having a thickness of 5 mm on which a pattern of the opening of the solder resist is drawn is brought into close contact with the solder resist layer 70, exposed to 1000 mJ / cm ² of ultraviolet light, and developed with a DMTG solution to form an opening 71 having a diameter of 200 μm. (FIG. 7A).
Further, the solder resist layer is cured by heating at 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours. A solder resist pattern layer having a thickness of 15 to 25 μm was formed. The opening 71 indicated by C7 in the drawing is enlarged and shown in FIG.

(24) Next, an OSP (Organic Solderability Preserbvative: Preflux) layer 72 is provided on the solder pad 160 (FIG. 7B).

(25) Thereafter, a solder paste containing lead-less (Sn / Ag / Cu = 65 / 32.5 / 2.5) solder in the opening 71 of the solder resist layer 70 on the surface on which the IC chip of the substrate is placed. Is printed, and solder paste containing tin-antimony is printed on the opening of the solder resist layer on the other side, and then solder bumps (solder bodies) are formed by reflowing at 200 ° C., and solder bumps 78U and 78D are formed. A multi-layer printed wiring board having the above was manufactured (FIG. 8).

FIG. 15B is an enlarged view of a portion surrounded by a circle C in the drawing. FIG. 16 is an enlarged view of the filled via (solder pad) in FIG.

  Finally, the IC chip 90 is attached via the solder bump 78U. And it attaches to the daughter board 94 via the solder bump 78D (FIG. 9).

(Example 1-2)
Example 1-2 was the same as Example 1-1 above, but the recess depth by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 0.5 μm.
(Example 1-3)
Example 1-3 was the same as Example 1-1 above, but the recess depth by etching of lid plating layer 36a and filled vias 60, 160, and 260 was adjusted to 1 μm.
(Example 1-4)
Example 1-2 was the same as Example 1-1 above, but the recess depth by etching of the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 2 μm.
(Example 1-5)
Example 1-5 was the same as Example 1-1 above, but the recess depth by etching of the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 4 μm.
(Example 1-6)
Example 1-6 was the same as Example 1-1 above, but the recess depth by etching of the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 5 μm.
(Example 1-7)
Example 1-7 was the same as Example 1-1 above, but the recess depth by etching of the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 6 μm.

(Example 1-8)
Example 1-8 was the same as Example 1-1 above, but the recess depth by etching of the lid plating layer 36a and filled vias 60, 160, 260 was adjusted to 1 μm. Here, in Example 1-1, there was a maximum of three stacked vias, but in Example 1-8, filled vias were stacked up to two.
(Example 1-9)
Example 1-9 is similar to Example 1-8, but has a structure in which filled vias are not stacked.

(Example 1-10)
Example 1-10 is similar to Example 1-1 above, but the bottom diameter of the filled via is 60 μm.
It was.
(Example 1-11)
Example 1-11 was the same as Example 1-10 above, but the recess depth by etching of lid plating layer 36a and filled vias 60, 160, 260 was adjusted to 0.5 μm.
(Example 1-12)
Example 1-12 was the same as Example 1-10 above, but the recess depth due to etching of the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 1 μm.
(Example 1-13)
Example 1-13 was the same as Example 1-10 described above, but the depth of the recess formed by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 2 μm.
(Example 1-14)
Example 1-14 is the same as Example 1-10, except that the depth of the recess formed by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 4 μm.
(Example 1-15)
Example 1-15 was the same as Example 1-10 above, but the recess depth due to etching of the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 5 μm.
(Example 1-16)
Example 1-16 was the same as Example 1-10 above, but the depth of the recess formed by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 6 μm.

(Comparative Example 1-1)
As Comparative Example 1-1, the structure is the same as that of Example 1-1 described above with reference to FIG. 8, but the lid plating layer 36a and the filled vias 60, 160, 260 are not provided with recesses.
(Comparative Example 1-2)
As Comparative Example 1-2, the structure is the same as that of Example 1-1 described above with reference to FIG. 8, but the bottom diameter of the filled via is set to 60 μm, and the lid plating layer 36 a and the filled vias 60, 160, and 260 are formed. It was set as the structure which does not provide a recessed part.

[Example 2]
(Example 2-1)
A multilayer printed wiring board according to Example 2 will be described with reference to the cross-sectional view of FIG.
In the first embodiment described above with reference to FIG. 8, the solder bumps 78 </ b> U and 78 </ b> D are provided on the filled via 260. On the other hand, in the multilayer printed wiring board according to the second embodiment, solder bumps 78U and 78D are provided on the filled via 260 and the conductor circuit 258. Further, in Example 1, the OSP layer 72 was provided in the opening 71 of the solder resist layer 70 and on the filled via 260. On the other hand, in Example 2, the solder bumps 78U and 78D are disposed in the opening 71 of the solder resist layer 70 through the nickel plated layer 73 and the gold plated layer 74 formed on the filled via 260 and the conductor circuit 258. Is provided.
In Example 2-1, the depth of the concave portion formed by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 3 μm as in Example 1-1.

(Example 2-2)
Example 2-2 was the same as Example 2-1 above, but the depth of the recess formed by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 0.5 μm.
(Example 2-3)
Example 2-3 was the same as Example 2-1 described above, but the depth of the recess formed by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 1 μm.
(Example 2-4)
Example 2-2 is the same as Example 2-1 described above, but the depth of the recess formed by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 2 μm.
(Example 2-5)
Example 2-5 was the same as Example 2-1 above, but the depth of the recesses formed by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 4 μm.
(Example 2-6)
Example 2-6 was the same as Example 2-1 above, but the depth of the recess formed by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 5 μm.
(Example 2-7)
Example 2-7 was the same as Example 2-1 above, but the depth of the recesses formed by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 6 μm.

(Example 2-8)
Example 2-8 was the same as Example 2-1 above, but the depth of the recess formed by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 1 μm. Here, in Example 2-1, there was a maximum of 3 stacked layers of filled vias, but in Example 2-8, filled vias were stacked up to 2 layers.
(Example 2-9)
Example 2-9 is similar to Example 2-8 above, but has a structure in which filled vias are not stacked.

(Example 2-10)
Example 2-10 is similar to Example 2-1 above, but the bottom diameter of the filled via is 60 μm.
(Example 2-11)
Example 2-11 was the same as Example 2-10, except that the depth of the recess formed by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 0.5 μm.
(Example 2-12)
Example 2-12 was the same as Example 2-10 described above, but the depth of the recess formed by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 1 μm.
(Example 2-13)
Example 2-13 was the same as Example 2-10 above, but the recess depth due to etching of lid plating layer 36a and filled vias 60, 160, 260 was adjusted to 2 μm.
(Example 2-14)
Example 2-14 was the same as Example 2-10 described above, but the depth of the recess formed by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 4 μm.
(Example 2-15)
Example 2-15 was the same as Example 2-10 described above, but the depth of the recess formed by etching the lid plating layer 36a and the filled vias 60, 160, and 260 was adjusted to 5 μm.
(Example 2-16)
Example 2-16 was the same as Example 2-10 described above, but the recess depth due to etching of lid plating layer 36a and filled vias 60, 160, and 260 was adjusted to 6 μm.

(Comparative Example 2-1)
As Comparative Example 2-1, the structure is the same as that of Example 2-1 described above with reference to FIG. 8 except that the lid plating layer 36a and the filled vias 60, 160, 260 are not provided with recesses.
(Comparative Example 2-2)
As Comparative Example 2-2, the structure is the same as that of Example 2-1 described above with reference to FIG. 8, but the bottom diameter of the filled via is set to 60 μm, and the lid plating layer 36 a and filled vias 60, 160, and 260 are formed. It was set as the structure which does not provide a recessed part.

[Example 3]
(Example 3-1)
A multilayer printed wiring board according to Example 3 will be described with reference to the cross-sectional view of FIG.
In the first embodiment described above with reference to FIG. 8, filled vias are used, but in the third embodiment, via holes 60 and 160 filled with resin are used. In Example 1, the through hole was provided with a lid plating layer, and a filled via was provided on the lid plating layer. On the other hand, in Example 3, the through hole 36 does not have a lid plating layer, and the via hole 60 is connected to the land of the through hole.
In Example 3-1, the depth of the recesses formed by etching the conductor circuit 34 and the conductor circuit 58 was adjusted to 3 μm as in Example 1-1.

Also in the third embodiment, as in the first embodiment, the connection interface between the via hole 60 and the conductor circuit 34 and the via hole 160 and the conductor circuit 58 is lower than the upper surfaces of the conductor circuits 34 and 58. Therefore, the connection interface that is most prone to crack is lower than the upper surface position of the conductor circuits 34 and 58 where the stress at the time of thermal contraction and impact is maximized, and cracks are less likely to occur. Resistance to thermal stress and resistance to impact can be increased. As a result, the connection reliability between the via hole 60 and the conductor circuit 34 and between the via hole 160 and the conductor circuit 58 is improved.

(Example 3-2)
Example 3-2 is the same as Example 3-1 above, but the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 0.5 μm.
(Example 3-3)
Example 3-3 is the same as Example 3-1 above, but the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 1 μm.
(Example 3-4)
Example 3-2 is the same as Example 3-1 above, but the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 2 μm.
(Example 3-5)
Example 3-5 is the same as Example 3-1. However, the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 4 μm.
(Example 3-6)
Example 3-6 was the same as Example 3-1, but the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 5 μm.
(Example 3-7)
Example 3-7 is the same as Example 3-1 above, but the recess depth of the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 by etching was adjusted to 6 μm.

(Example 3-8)
Example 3-8 is similar to Example 3-1 above, but the bottom diameter of the filled via is 60 μm.
(Example 3-9)
Example 3-9 is the same as Example 3-8, but the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 0.5 μm.
(Example 3-10)
Example 3-10 is the same as Example 3-8, except that the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 1 μm.
(Example 3-11)
Example 3-11 is the same as Example 3-8, but the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 2 μm.
(Example 3-12)
Example 3-12 is the same as Example 3-8, but the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 4 μm.
(Example 3-13)
Example 3-13 is the same as Example 3-8, but the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 5 μm.
(Example 3-14)
Example 3-14 is the same as Example 3-8, except that the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 6 μm.

(Comparative Example 3-1)
As Comparative Example 3-1, the structure is the same as that of Example 3-1 described above with reference to FIG. 8, but the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 have no recess.
(Comparative Example 3-2)
As Comparative Example 3-2, the structure is the same as that of Example 3-1 described above with reference to FIG. 8, but the bottom diameter of the filled via is set to 60 μm, and the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 are provided. It was set as the structure which does not provide a recessed part.

[Example 4]
(Example 4-1)
A multilayer printed wiring board according to Embodiment 4 will be described with reference to FIGS.
Examples 1 to 3 are build-up type multilayer printed wiring boards, but Example 4 is a laminated multilayer printed wiring board formed by laminating a plurality of substrates. FIG. 26 is a cross-sectional view of the multilayer printed wiring board of Example 4.
The multilayer printed wiring board 10 is formed by stacking substrates 30. Each substrate 30 is provided with a conductor circuit 42 on one surface and a conductor circuit 44 on the other surface, and the conductor circuit 42 and the conductor circuit are connected via a via hole 46. The via hole 46 is connected to the conductor circuit 42 through a recess 32 h provided on the inner surface side of the conductor circuit 42. A solder bump 78U is connected to the via hole 46 of the substrate 30 on the upper surface layer side via a recess 46h. Similarly, the solder bump 78D is connected to the via hole 46 of the substrate 30 on the lower surface layer side through the recess 46h. The upper surface layer and the lower surface layer are provided with a solder resist layer 70 in which openings 71 for projecting the solder bumps 78U and 78D are formed.

As shown in FIG. 27, electronic components 90 and 90B are connected to the solder bump 78U and the solder bump 78D on the upper surface side of the multilayer printed wiring board 10.

In the multilayer printed wiring board of Example 4, in the connection portion between the bottom of the via hole 46 and the conductor circuit (lower conductor layer) 42, the connection interface between the via hole 46 and the lower conductor layer 42 corresponds to the recess 32h on the back surface of the lower conductor layer. Since they are shifted, the connection interface can be shifted downward from the upper surface position of the conductor circuit 42 where the stress is concentrated, and as a result, breakage at the connection interface can be prevented. The multilayer printed wiring board manufactured by this application can raise the tolerance with respect to a thermal stress, and the tolerance at the time of an impact.

Next, a method for manufacturing the multilayer printed wiring board of Example 4 will be described with reference to FIGS.
(1) First, a double-sided circuit board constituting a multilayer circuit board is manufactured. This circuit board uses, as a starting material, a double-sided copper-clad laminate 30A obtained by laminating a prepreg 30 in which epoxy resin is crushed in a glass cloth to form a B stage, and a copper foil 32 and heat-pressing ( FIG. 22 (A)).

The insulating substrate has a thickness of 75 μm and the copper foil has a thickness of 16 μm. If necessary, the insulating base material may be etched to reduce the thickness of the copper foil 32 (for example, 14 μm) (FIG. 22B).

(2) The etched double-sided circuit board is irradiated with a carbon dioxide laser to form a via-hole forming opening 16 that penetrates the copper foil 32 and the insulating base material 30 and reaches the copper foil 32 on the opposite surface ( FIG. 22 (C)) and the inside of the opening were further subjected to desmear treatment by chemical treatment with permanganic acid.
In this embodiment, the opening 16 for forming the via hole is formed by using a high peak short pulse oscillation type carbon dioxide gas laser processing machine manufactured by Hitachi Via, and a glass cloth epoxy resin substrate having a substrate thickness of 75 μm is coated with copper. The foil is directly irradiated with a laser beam at a speed of 100 holes / sec.
An opening for forming a via hole of 0 μmφ was formed.

(3) A depth of 3 μm is formed on the back surface of the copper foil 32 exposed by the opening 16 with an etching solution mainly containing cupric chloride on the surface of the copper foil 32 having opened the insulating substrate after the desmear treatment. The concave portion 32h is formed. This depth is set to a desired value by adjusting the time of light etching (FIG. 22D). At this time, the thickness of the copper foil 32 was adjusted to 12 μm.

(4) An electrolytic copper plating process using the copper foil as a plating lead was performed on the substrate having the recess 32h formed on the copper foil surface under the following conditions.
[Electrolytic plating solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive A (reaction accelerator) 10.0 ml / l
Additive B (reaction inhibitor) 10.0 ml / l
[Electrolytic plating conditions]
Current density 1 A / dm ²
Time 65 minutes Temperature 22 ± 2 ℃
Additive A promotes the formation of an electrolytic copper plating film in the via hole (opening), and conversely adheres to the copper foil portion mainly by additive B, thereby suppressing the formation of the plating film. Further, when the inside of the via hole is filled with electrolytic copper plating and becomes almost the same height as the copper foil, the additive B is attached, so that the formation of the plating film is suppressed similarly to the copper foil portion. As a result, the electrolytic copper plating 14 was filled into the opening 16 to form a flattened via hole 46 (FIG. 23A).

At that time, when the electrolytic copper plating rises at the upper portion of the opening 16, the raised portion may be removed by a physical method such as sander belt polishing or buff polishing and planarized.

(5) A photosensitive dry film etching resist 38 was formed on the copper foil 32 and the copper plating 14 of the insulating base material 30 that had undergone the above step (3) (FIG. 23B). The resist 38 was formed to have a thickness of 15 to 20 μm, and a resist non-formation portion was formed on the copper plating 14 and the copper foil 32 through exposure and development.

(6) The non-formed portion of the resist 38 is etched with an etching solution made of copper chloride to remove the copper plating film 14 and the copper foil 32 corresponding to the non-formed portion. Thereafter, the resist is peeled off with an alkaline solution to form a conductor circuit 44 including the conductor circuit 42 and the via hole 46 (FIG. 23C). Thereby, there is a via hole 46 for connecting the front and back, and a circuit board in which the via hole 46 and the copper foil portion forming the conductor circuit are flattened can be obtained. Thereafter, a blackening process may be performed to form a blackened layer 44B on the conductor circuits 42 and 44 (FIG. 23D).

(7) Thereafter, the circuit board 30 obtained through the steps (1) to (6) is regarded as one unit (FIG. 24 (A)), and an adhesive layer 48 such as a prepreg is sandwiched between the substrates, and pressing conditions The multilayer substrate 10 was formed by heating and pressing at 80 to 250 ° C. and a pressure of 1 to 10 kgf / cm 2 (FIG. 24B).

On this, a single-sided copper-clad laminate or a double-sided copper-clad laminate in which a circuit is formed on one side by etching is laminated on the circuit board 30 with the adhesive layer 48 interposed therebetween, and the copper foil side of the laminated substrate is Through the steps (1) to (6), there can be obtained a multilayer substrate in which there are via holes that connect the front and back surfaces in the same manner, and the via holes and the copper foil portions that form the conductor circuit are flattened. it can. Furthermore, multilayering can be performed by repeating this process. In this lamination, the direction of the via hole may be the same direction or may be opposed. In addition to this, multilayering may be performed by combination.

(8) A solder resist layer was formed on the surface of the circuit board located in the uppermost layer and the lowermost layer of the multilayer substrate 10. A solder resist layer having a thickness of 20 to 30 μm was formed on the substrate by applying a film-formed solder resist layer or applying it with a varnish whose viscosity was adjusted in advance.
Next, after drying at 70 ° C. for 20 minutes and at 100 ° C. for 30 minutes, a 5 mm thick soda lime glass base slope on which a circular pattern (mask pattern) of the solder resist opening is drawn is applied to the solder resist layer. The film was exposed to 1000 mJ / cm ² of ultraviolet light and DMTG developed. Furthermore, heat treatment was performed at 120 ° C. for 1 hour and 150 ° C. for 3 hours to form a solder resist layer (thickness 20 μm) 70 having an opening 71 corresponding to the pad portion (opening diameter 200 μm) (FIG. 24C )).

(9) Next, the substrate on which the solder resist layer is formed is placed in an electroless nickel plating solution having a pH of 5 consisting of 30 g / 1 of nickel chloride, 10 g / 1 of sodium hypophosphite, and 10 g / 1 of sodium citrate for 20 minutes. Immersion was performed to form a nickel plating layer 73 having a thickness of 5 μm in the opening 71 (FIG. 25A).

(10) Further, the substrate was placed at 93 ° C. in an electroless gold plating solution composed of 2 g / l gold cyanide, 75 g / 1 ammonium chloride, 50 g / 1 sodium citrate, and 10 g / 1 sodium hypophosphite. The film was immersed for 23 seconds to form a 0.03 μm-thick gold plating layer 74 on the nickel plating layer 73, and a coated metal layer composed of the nickel plating layer 73 and the gold plating layer 74 was formed (FIG. 25 ( B)).

(11) A solder paste made of Sn / Pb solder having a melting point T2 of about 183 ° C. is printed on the solder pad exposed from the opening 71 of the solder resist layer 70 that covers the uppermost multilayer circuit board. Then, solder bumps (or solder layers) 78U and 78 (D) were formed (FIG. 26).

(Example 4-2)
Example 4-2 is similar to Example 4-1 above, but the recess depth by etching of the conductor layer was adjusted to 0.5 μm.
(Example 4-3)
Example 4-3 was the same as Example 4-1 above, but the recess depth by etching of the conductor layer was adjusted to 1 μm.
(Example 4-4)
Example 4-4 is similar to Example 4-1 above, but the recess depth by etching of the conductor layer was adjusted to 2 μm.

(Example 4-5)
Example 4-5 was the same as Example 4-1 above, but the recess depth by etching of the conductor layer was adjusted to 4 μm.
(Example 4-6)
Example 4-6 was the same as Example 4-1 above, but the depth of the recess by etching of the conductor layer was adjusted to 5 μm.

(Example 4-7)
Example 4-7 was the same as Example 4-1 above, but the recess depth by etching of the conductor layer was adjusted to 6 μm.

(Comparative Example 4-1)
As Comparative Example 4-1, it has the same structure as Example 4-1 described above with reference to FIG.
The conductor layer 32 and the via hole 46 are not provided with a recess.

(Modification of Example 4)
With reference to FIGS. 28-30, the manufacturing method of the multilayer printed wiring board which concerns on the modification of Example 4 is demonstrated.
Here, since the manufacturing method of the fourth embodiment described above with reference to FIGS. 22 and 23 is the same as the manufacturing method of the modified example of the fourth embodiment, illustration and description thereof are omitted.
(1) A single-sided copper-clad laminate 30B obtained by laminating a prepreg 30 in which a glass cloth is impregnated into a glass cloth and making a B stage and a copper foil 32 and hot pressing is shown in FIG. It arrange | positions to the upper surface of the circuit board 30 to show, and a lower surface (FIG. 28 (A)), and press-presses and forms the multilayer substrate 10 (FIG. 28 (B)).

(2) The multilayer substrate 10 is irradiated with a carbon dioxide laser to pierce the copper foil 32 and the insulating base material 30 on the outer layer side and pierce the via hole forming opening 16 reaching the inner layer conductor circuits 44 and 42. (FIG. 29A).

(3) Concave portions 44h and 42h having a depth of 3 μm are formed in the inner-layer conductor circuits 44 and 42 exposed by the opening 16 with an etching solution (FIG. 29B). This depth is set to a desired value by adjusting the light etching time.

(4) Electrolytic copper plating is performed on the substrate on which the recesses 44h and 42h are formed, and the opening 16 is filled with the electrolytic copper plating 14 to form a flattened via hole 46 (FIG. 30A).
.

(5) A photosensitive dry film etching resist was formed on the copper foil 32 and the copper plating 14, and a resist non-formation portion was formed through exposure and development. Then, etching is performed on the resist non-formed portion with an etching solution made of copper chloride, and the copper plating film 14 and the copper foil 32 corresponding to the non-formed portion are removed. Thereafter, the resist was peeled off with an alkaline solution to form a conductor circuit 44 including the via hole 46 (FIG. 30B). Subsequent steps are the same as those in the fourth embodiment described above with reference to FIGS.

[Example 5]
(Example 5-1)
A multilayer printed wiring board according to Embodiment 5 will be described with reference to the cross-sectional view of FIG.
The multilayer printed wiring board 10 according to the fifth embodiment is formed by stacking the substrates 30 as in the fourth embodiment. However, in Example 5, a part of the via hole has a stacked via structure in which the via hole is disposed immediately above the via hole. Here, in the fifth embodiment, as in the fourth embodiment, the via hole 46 is connected to the conductor circuit 42 via a recess 32 h provided on the inner surface side of the conductor circuit 42. Thereby, the fracture | rupture in the connection interface of the via hole 46 and the conductor circuit 42 is prevented.

(Example 5-2)
Example 5-2 was the same as Example 5-1 above, but the recess depth by etching of the conductor layer was adjusted to 0.5 μm.
(Example 5-3)
Example 5-3 was the same as Example 5-1 above, but the recess depth by etching of the conductor layer was adjusted to 1 μm.
(Example 5-4)
Example 5-4 is the same as Example 5-1 above, but the recess depth by etching of the conductor layer was adjusted to 2 μm.

(Example 5-5)
Example 5-5 was the same as Example 5-1 above, but the recess depth by etching of the conductor layer was adjusted to 4 μm.
(Example 5-6)
Example 5-6 is similar to Example 5-1 above, but the recess depth by etching of the conductor layer was adjusted to 5 μm.

(Example 5-7)
Example 5-7 was the same as Example 5-1 above, but the recess depth by etching of the conductor layer was adjusted to 6 μm.

(Comparative Example 5-1)
As Comparative Example 5-1, the structure was the same as that of Example 5-1 described above with reference to FIG. 31, but the conductor layer 32 and the via hole 46 were not provided with a recess.

Hereafter, about the result of having performed the drop test and the reliability test about the printed wiring board of Example 1-1 to Example 5-7 and Comparative Example 1-1 to Comparative Example 5-1, FIG. 33 to FIG. This will be described with reference to the chart in FIG.

(Reliability test)
First, an IC chip was mounted on the multilayer printed wiring boards of each of the examples and comparative examples, and then an IC mounting substrate was formed by filling a sealing resin between the IC chip and the multilayer printed wiring board. Then, the electrical resistance of the specific circuit through the IC chip (the electrical resistance between the pair of electrodes exposed to the surface opposite to the IC chip mounting surface of the IC mounting substrate and conducting to the IC chip) is measured, The value was taken as the initial value. Thereafter, a heat cycle test was performed on these IC-mounted substrates, with −55 degrees × 5 minutes and Comparative Example 5 degrees × 5 minutes as one cycle, and this was repeated 2500 times. In this heat cycle test, the electrical resistance at the 500th, 1000th, 1500th, 2000th and 2500th cycles was measured, and the change rate from the initial value (100 × (measured value−initial value) / initial value (%)) was determined. . The results are shown in FIGS. In the figure, when the rate of change in electrical resistance is within ± 5%, “good” (◯), when ± 5-10% is “normal” (△), and when the rate of change exceeds ± 10, “bad” (× ). The target specification is that the rate of change at the 1000th cycle is within ± 10% (that is, “good” or “normal” in evaluation). Moreover, the thing within +/- 10% was set as the "pass".

As a result of the reliability test, as the bottom diameter of the via hole (filled via) becomes smaller, the reliability decreases. However, even if the bottom diameter is 50 μm, the reliability is ensured by providing a recess having a depth of 0.5 μm or more. I knew I would get it. Further, it has been revealed that the reliability can be remarkably improved by providing a recess having a depth of 2 μm, more preferably 3 μm. On the other hand, if a recess having a depth exceeding 5 μm is provided, the reliability is lowered. In particular, from the results of Examples 2-7 and 2-16, a depth of 6 μm is provided when a solder pad is provided on a conductor circuit. It was found that the reliability decreases when the concave portion is provided.

Further, from the comparison between the first and second embodiments using the filled via and the third embodiment using the via hole, the filled via has a lower connection reliability with respect to thermal stress than the via hole. It has been found that the connection reliability of filled vias can be improved by the structure provided with. Further, from the comparison between Example 1-3, Example 1-8, and Example 1-9, the reliability decreases as the number of overlaid vias increases. However, as in Example 1-1, the reliability is 3 μm or more. It has been found that the desired reliability can be obtained by providing a recess having a depth.

(Drop test)
As shown in FIG. 32 (A), the substrates 10 of Examples 1-1 to 5-7 and Comparative Examples 1-1 to 5-1 are mounted on the daughter board 60, and each is housed in a housing 98. Secure with screws. As shown in FIG. 32 (B), this fixed casing 98 is naturally dropped from a height of 1 m with the vertical (head wall TP on the upper side and bottom wall BT on the lower side) side down. After the drop test, the electrical connection was checked for each example.
Number of drop tests: 10, 20, 30

If the drop test of 10 times was cleared, the drop resistance could be increased compared to the conventional product (Comparative Example 1-1), and this could be cleared in all of Examples 1-1 to 5-7. . On the other hand, clearing the 30-time drop test indicates that it has high drop resistance, and Example 1-2, Example 2-2, Example 3-2, Example 4-2, and Example 5- Except for Example 2, Example 1-1 to Example 5-7 were able to clear 30 times.

It is process drawing which shows the manufacturing method of the multilayer printed wiring board of Example 1 of this invention. 3 is a process diagram illustrating a method for manufacturing the multilayer printed wiring board of Example 1. FIG. 3 is a process diagram illustrating a method for manufacturing the multilayer printed wiring board of Example 1. FIG. 3 is a process diagram illustrating a method for manufacturing the multilayer printed wiring board of Example 1. FIG. 3 is a process diagram illustrating a method for manufacturing the multilayer printed wiring board of Example 1. FIG. 3 is a process diagram illustrating a method for manufacturing the multilayer printed wiring board of Example 1. FIG. 3 is a process diagram illustrating a method for manufacturing the multilayer printed wiring board of Example 1. FIG. 1 is a cross-sectional view of a multilayer printed wiring board according to Example 1. FIG. 3 is a cross-sectional view showing a state where an IC chip is placed on a multilayer printed wiring board according to Embodiment 1. FIG. FIG. 9 is an enlarged view of a portion surrounded by a circle C in FIG. 8. 3 is a process diagram illustrating a method for manufacturing the multilayer printed wiring board of Example 1. FIG. It is an enlarged view of the filled via in FIG. 3 is a process diagram illustrating a method for manufacturing the multilayer printed wiring board of Example 1. FIG. FIG. 14 is an enlarged view of the filled via in FIG. 3 is a process diagram illustrating a method for manufacturing the multilayer printed wiring board of Example 1. FIG. FIG. 16 is an enlarged view of a filled via in FIG. It is a schematic diagram which shows the example of arrangement | positioning of a filled via. It is a graph which shows the stress value with respect to the etching amount of the filled via | veer in FIG. FIG. 19A is a schematic diagram illustrating an example of the arrangement of filled vias, and FIG. 19B is a graph illustrating a stress value with respect to the amount of etching of filled vias in FIG. 19A. 6 is a cross-sectional view of a multilayer printed wiring board according to Embodiment 2. FIG. 6 is a cross-sectional view of a multilayer printed wiring board according to Example 3. FIG. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of Example 4. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of Example 4. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of Example 4. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of Example 4. 6 is a cross-sectional view of a multilayer printed wiring board according to Example 4. FIG. 6 is a cross-sectional view illustrating a state in which electronic components are placed on a multilayer printed wiring board according to Embodiment 4. FIG. 6 is a process diagram illustrating a method for manufacturing a multilayer printed wiring board according to a modification of Example 4. FIG. 6 is a process diagram illustrating a method for manufacturing a multilayer printed wiring board according to a modification of Example 4. FIG. 6 is a process diagram illustrating a method for manufacturing a multilayer printed wiring board according to a modification of Example 4. FIG. 10 is a cross-sectional view of a multilayer printed wiring board according to Embodiment 5. FIG. It is explanatory drawing which shows the content of the drop test. It is a graph which shows the result of the drop test of Example 1 and the comparative example 1, and a reliability test. It is a graph which shows the result of the drop test of Example 2 and the comparative example 2, and a reliability test. It is a graph which shows the result of the drop test of Example 3 and the comparative example 3, and a reliability test. It is a graph which shows the result of the drop test of Example 4 and the comparative example 4, and a reliability test. It is a graph which shows the result of the drop test of Example 5 and the comparative example 5, and a reliability test.

Explanation of symbols

30 Substrate 32 Conductor circuit 32h Recess 34 Conductor circuit 36 Through hole 36a Lid plating layer (through hole land)
36b Side wall conductor layer 36h Recess 40 Resin filled layer 46 Via hole 46h Recess 50 Interlayer resin insulation layer 58 Conductor circuit 60 Filled via 60h Recess 78U, 78D Solder bump 70 Solder resist layer 71 Opening 78U, 78D Solder bump 160 Filled via

Claims (2)

A multilayer print in which an interlayer insulating layer and an upper layer conductor layer are formed on a lower layer conductor layer provided on the surface of the core substrate, and the lower layer conductor layer and the upper layer conductor layer are electrically connected via a via hole In the wiring board,
In the connecting portion between the bottom portion of the via hole, Ri Contact said recess in the lower conductive layer side it is provided,
The multilayer printed wiring board , wherein the lower conductor layer is formed on a filled via formed on a core substrate . The multilayer printed wiring board according to claim 1, wherein the filled via includes an electroless plating layer and an electrolytic plating layer, and the thickness of the electroless plating layer is smaller than the depth of the recess.

Images