JP2004158703A - Printed wiring board and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce electric connection failure between conductive layers generated due to the thermal expansion difference of an insulating layer and a conductor layer in the via hole of a printed wiring board. <P>SOLUTION: In this printed wiring board, the area of a joint face 18 of a first conductor 12 and a second conductor 15 at a via bottom part, and the second conductor 15 is provided with a fringe(collar) area 21 connected to a surface 17 of the second insulating layer at an outer peripheral part 20 of the opening of the second insulating layer 14 at the via bottom part. Therefore, the printed wiring board can be stabilized against a tensile stress generated due to the thermal expansion difference of the insulating layer and the conductor layer, and any electric connection failure between the conductor layers in the via can be prevented from being generated. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to a printed wiring board and a method for manufacturing the same, and more particularly, to a multilayer printed wiring board having via holes for electrical connection between conductor layers separated by an insulating layer and a method for manufacturing the same. .
[0002]
[Prior art]
A multilayer printed wiring board manufactured by a method such as a build-up method has via holes for electrical connection between conductor layers separated by an insulating layer. FIG. 1 is a diagram showing a cross section of a conventional via hole. In FIG. 1, a patterned conductor layer 2 generally called a "land" is provided on an insulating layer 1 made of a resin or the like serving as a base. The conductor layer 2 is covered with an insulating layer 4 made of resin or the like except for the opening 3 of the via. The via opening 3 is formed by making a hole to the conductor layer 2 in the insulating layer 4 by wet etching, laser, or the like. The inside of the opening 3 of the insulating layer 4 is covered with the conductor layer 5 by a plating method or the like. The conductor layer 5 is connected to the conductor layer 2 and also to a conductor layer (not shown) on the insulating layer 4. The electrical connection between the upper and lower conductive layers of the insulating layer 4 is achieved by the conductive layer 5.
[0003]
In a printed wiring board, a thermal stress is generated inside the printed wiring board due to a difference in thermal expansion coefficient between the insulating layer and the conductor layer. The thermal stress acts in a direction indicated by an arrow 6 in the via hole of FIG. That is, a force acts in a direction to separate the bonding between the conductor layer 2 of the land and the conductor layer 5 of the via in FIG. As a result, a situation (disconnection) occurs in which the bonding surface 7 is separated and the electrical connection between the conductor layer 2 and the conductor layer 5 is cut off. This phenomenon becomes more remarkable as the diameter of the via hole becomes smaller. The reason is that as the opening at the bottom of the via hole becomes smaller, the area of the land conductor 2 exposed to the opening also becomes smaller. As a result, the area of the joint surface 7 (FIG. 1) between the conductor layer 2 and the conductor layer 5 of the via becomes smaller. It is because. In addition, this phenomenon becomes remarkable in an environment where a temperature change is large, and significantly reduces the reliability of the printed wiring board.
[0004]
A conventional technique relating to a printed wiring board for the purpose of enhancing the reliability of conductor connection with respect to a peeling force in a via hole is disclosed in, for example, Japanese Patent Laid-Open Publication No. 2001-24329. However, the printed wiring board of this publication does not disclose any technique for preventing a situation (disconnection) in which the electrical connection between the conductor layer 2 and the conductor layer 5 is cut off due to the thermal stress separating the bonding surface 7 in FIG. .
[0005]
As a conventional example which discloses a technique for preventing a situation (disconnection) in which the electrical connection between the conductor layer 2 and the conductor layer 5 is cut off, there is Japanese Patent Laid-Open Publication No. Hei 5-67882. The technique disclosed in this publication increases the bonding area between the conductor layer 2 and the conductor layer 5 by increasing the hole diameter at the bottom of the via or increasing the depth of the via using a laser. Therefore, the technique disclosed in this publication does not solve the problem in the case where the hole diameter and the depth of the via cannot be increased due to the design. In other words, the technology disclosed in the publication is not effective for the fine via hole specification (for example, hole diameter: several tens of micrometers or less) required for the current and future printed wiring boards.
[0006]
[Problems to be solved by the invention]
An object of the present invention is to eliminate electrical connection (disconnection) defects between conductor layers caused by a difference in thermal expansion between an insulating layer and a conductor layer in a via hole of a printed wiring board.
[0007]
An object of the present invention is to improve the reliability of a printed wiring board against temperature changes.
[0008]
[Means for Solving the Problems]
The present invention provides a first conductor formed on a first insulating layer, a second insulating layer formed on a first insulating layer including the first conductor, and a first conductor formed on the first conductor. A second hole provided in the second insulating layer and reaching the first conductor, and a second insulating layer covering at least the inner peripheral surface of the hole and the surface of the second insulating layer around the opening of the hole to be connected to the first conductor. Wherein the first conductor and the second conductor are joined below the contact surface between the first conductor and the second insulating layer at the bottom of the hole, and the diameter of the joint surface is at the bottom of the hole. A printed wiring board having a via hole, wherein the diameter is larger than the opening diameter of the second insulating layer.
[0009]
The printed wiring board of the present invention has a large bonding area between the first conductor and the second conductor at the bottom of the via, and furthermore, the second conductor is formed at the outer periphery of the opening of the second insulating layer at the bottom of the via. 2 has a fringe region joined to the surface of the insulating layer, so that it is stable against a tensile stress generated due to a difference in thermal expansion between the insulating layer and the conductive layer, and the electrical connection failure between the conductive layers in the via is reduced. Does not occur.
[0010]
The method for manufacturing a printed wiring board of the present invention includes:
(A) providing a first insulating layer;
(B) providing a first conductor layer on the first insulating layer;
(C) providing a second insulating layer on the first insulating layer including the first conductor layer;
(D) providing a hole to the first conductive layer in the second insulating layer on the first conductive layer;
(E) providing an opening having a diameter larger than the opening diameter at the bottom of the hole in the first conductor layer facing the hole;
(F) filling the opening and forming a second conductor layer covering at least the inner peripheral surface of the hole and the surface of the second insulating layer around the opening of the hole. It is.
[0011]
The printed wiring board manufactured by the method for manufacturing a printed wiring board according to the present invention has a large bonding area between the first conductor and the second conductor at the bottom of the via, and the second conductor has a second insulating layer at the bottom of the via. Has a fringe region that is joined to the surface of the second insulating layer in the outer peripheral portion of the opening, so that it is stable against tensile stress generated due to the difference in thermal expansion between the insulating layer and the conductor layer, and No electrical connection failure occurs.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention will be described in detail below. The following description is made mainly with respect to a via hole which is a feature of the present invention. The other parts of the printed wiring board may be made by a conventional general manufacturing method, and a description thereof is omitted here. Needless to say, the via hole structure of the present invention can be applied to all printed wiring boards including a multi-layer build-up board.
[0013]
FIG. 2 is a diagram showing a cross section of one embodiment of the via hole portion of the printed wiring board of the present invention. On the insulating layer 11, there is a conductor layer 12 serving as a land. The insulating layer 14 is on the insulating layer 11 including the conductor layer 12. The insulating layer 14 on the conductor layer 12 has a hole 13. The conductor layer 15 covers the inner peripheral surface 16 of the hole 13 and the surface 17 of the insulating layer 14 around the opening of the hole 13, and is connected to the conductor layer 12 at the bonding surface 18. The bonding surface 18 is below a plane 19 including a contact surface between the conductor layer 12 and the insulating layer 14 at the bottom of the hole 13. The diameter L of the joining surface 18 is larger than the opening diameter L1 of the insulating layer 14 at the bottom of the hole.
[0014]
The conductor 15 has a fringe region 21 that is joined to the surface 20 of the insulating layer 14 at the outer periphery 20 of the opening of the insulating layer 14 at the bottom of the hole 13. The portion 22 of the conductor 15 below the plane 19 has a so-called nail or screw head shape. Due to the presence of the conductor portion 22, the area of the joint surface 18 with the conductor layer 12 becomes larger than the area of the conventional joint surface 7 of FIG. Further, since the conductor portion 22 has a shape like a screw head (having the fringe region 21), a tensile force generated due to a difference in thermal expansion coefficient between the insulating layer and the conductor layer due to a synergistic effect thereof. (Direction of arrow 23).
[0015]
The conductor portion 22 can be as large as the size indicated by the dotted line 24 in FIG. That is, the diameter L of the conductor portion 22 (the diameter of the joint surface 24) can be expanded up to the width L2 of the conductor 12. Further, the thickness H of the conductor portion 22 can be expanded up to the thickness H1 of the conductor 12. As the size of the conductor portion 22 increases, the area of the joint surface 18 increases, and at the same time, the fringe region 21 in contact with the insulating layer surface 20 also increases, so that it becomes stronger against the tensile force (in the direction of the arrow 23). In this case, there is a tendency that the resistance to the tensile force increases in proportion to the area of the joint surface 18 with the conductor portion 22.
[0016]
FIG. 3 is a diagram showing a cross section of another embodiment of the via hole portion of the printed wiring board of the present invention. FIG. 3 shows a structure in which the hole 13 of FIG. All other configurations are the same as the configuration in FIG. Also in the via structure of FIG. 3, as in the case of FIG. 2, the presence of the conductor portion 22 below the dotted line 19 increases the tensile force (in the direction of the arrow 23).
[0017]
FIG. 4 is a diagram showing a flow of the method for manufacturing a printed wiring board of the present invention.
In step (a), a first insulating layer 11 is prepared. The first insulating layer 11 can be provided over the substrate or over the insulating layer over the substrate. As the insulating layer, for example, resin is used. In step (b), a first conductor layer 12 is provided on the first insulating layer 11. The conductor layer 12 is obtained by patterning (etching) the conductor layer provided on the entire first insulating layer 11 by photolithography. Alternatively, the patterned conductor layer 12 is obtained by a so-called pattern plate method. In step (c), a second insulating layer 14 is provided on the first insulating layer 11 including the first conductor layer 12. The second insulating layer 14 is obtained by, for example, pressing a resin film and then curing the resin film.
[0018]
In step (d), a hole 13 reaching the first conductor layer 12 is provided in the second insulating layer 14 on the first conductor layer 12. The holes 13 are obtained by photolithography (etching) technology or laser irradiation (removal). In step (e), an opening 30 having a diameter L larger than the opening diameter L1 at the bottom of the hole is provided in the first conductor layer 12 facing the hole 13. The opening 30 is formed by a so-called wet etching method using a solution such as an acid for removing (etching) the conductive layer 12. The size (width L and thickness H) of the opening 30 is controlled by the concentration of the etchant, the etching time, and the like. What is important here is that the conductor layer 12 is etched not only in the vertical direction but also in the horizontal direction as in the so-called anisotropic etching. That is, so-called isotropic etching is performed. This step (e) exposes the surface 20 of the second insulating layer at the outer periphery 20 of the opening 13 of the second insulating layer 14 at the bottom of the hole. When the conductor layer is formed by plating in a later step, a “roughening step” for forming fine irregularities on the surface of the insulating layer 14 in the hole 13 is performed before step (e). The reason is to improve the adhesion between the plating metal and the insulating layer 14.
[0019]
In step (f), a second conductor layer 15 is formed to fill the opening 30 and at least cover the inner peripheral surface 16 of the hole and the surface 17 of the second insulating layer 14 around the opening 13 of the hole. The second conductor layer 15 is formed by, for example, a plating method. The conductor layer 15 on the insulating layer 14 is formed into a predetermined pattern by a photolithography (etching) technique. The conductor layer 15 is connected to another conductor layer on the insulating layer 14. As a result, electrical connection between the upper and lower sides of the insulating layer is established via the conductor layer 15. The conductor 15 has a fringe region 21 that is joined to the surface 20 of the insulating layer 14 at the outer periphery 20 of the opening of the insulating layer 14 at the bottom of the hole 13. By the step (f), a via structure similar to that of FIG. 2 is obtained. The via structure shown in FIG. 3 can be obtained by filling the hole 13 up to the dotted line 32 with the conductor layer 15.
[0020]
【Example】
FIG. 5 is an enlarged view of a cross section of a via hole portion formed by the manufacturing method of the present invention. FIG. 5 is a diagram created based on a photomicrograph of an actual via cross section. The reference numerals in FIG. 5 correspond to those in FIGS. In FIG. 5, the diameter of the opening in the insulating layer 14 above the via is about 48 micrometers, and the diameter L1 of the opening in the insulating layer 14 at the bottom of the via is about 38 micrometers. The width (diameter) L2 of the conductor layer 12 is about 95 micrometers, and its thickness H1 is about 13 micrometers. The thickness H2 of the insulating layer 14 is about 35 micrometers. Further, the depth H5 of the conductor portion 22 of the conductor layer 12 is about 5 micrometers, and the diameter L is about 57 micrometers. Note that the conductor layers 12 and 15 are copper plating layers. The insulating layer 14 is a resin layer.
[0021]
The manufacturing process of the via of FIG. 5 using the pattern plate method is described below.
(A) A circuit pattern including the conductor layer 12 is formed by etching a land conductor or a pattern plate method.
(B) The insulating layer 14 is formed by pressing and curing the insulating layer film.
(C) A hole is formed by a laser. At this point, the opening including the flange region has not yet been formed.
(D) The surface of the insulating layer resin is roughened with permanganic acid in order to increase the adhesion strength of the plated copper in the subsequent step. At this point, no flange has yet been formed.
(E) The conductive layer 12 at the bottom of the via is etched using a mixed solution containing an acid such as sulfuric acid to form an opening.
(F) Electroless copper plating is applied to the entire surface of the insulating layer. At this time, the opening of the conductor layer 12 is also plated with electroless copper.
(G) A pattern resist is applied to the panel, and exposure and development are performed.
(H) Electroless copper plating is performed using the electroless copper formed in (f) as a seed layer to form a pattern. The formation is performed by a pattern plate method or a semi-additive method. At this time, the opening formed in (e) is plated with copper, and the opening is completely filled with copper. As a result, a flange region (conductor portion 22) is formed at the bottom of the via.
[0022]
The results of a temperature cycle test of the printed wiring board including the via of the present invention shown in FIG. 5 are shown below. For comparison, a test was also performed on a conventional substrate including the via of FIG. 1 at the same time.
(A) Test conditions:
The following two temperature cycle (1000 cycle) tests 1 and 2 were performed.
1. Test 1 conditions: -55 to 125 ° C, 1000 cycles at 2 cycles / hour,
2. Test 2 conditions: -55 to 125 ° C, 1000 cycles at 10 cycles / hour (b) Sample:
1. Substrate A including the conventional via of FIG. 1:
39 substrates for test 1 (including a total of 103,040 vias),
56 substrates for test 2 (including a total of 173360 vias)
2. Substrate B including via of the present invention in FIG. 2 (FIG. 5)
20 substrates for test 1 (including a total of 70000 vias),
41 boards for test 2 (including a total of 69216 vias)
(C) Test results:
1. Conventional substrate A:
Via conduction failure (breakage) occurred in 11 out of 95 substrates of 39 substrates for the temperature cycle test 1 and 56 substrates for the temperature cycle test 2 (rate of occurrence: about 12%).
2. Substrate B of the present invention:
Out of a total of 61 substrates, 20 substrates for the temperature cycle test 1 and 41 substrates for the temperature cycle test 2, none of the substrates had via conduction failure (disconnection). In other words, this means that the number of vias in which via conduction failure (disconnection) has occurred is zero for a total of 139216 vias (failure occurrence ratio: 0%).
[0023]
【The invention's effect】
The printed wiring board manufactured by the method for manufacturing a printed wiring board of the present invention has a large contact area between the first conductor and the second conductor at the bottom of the via, and the second conductor has a second insulating layer at the bottom of the via. Has a fringe (collar) region joined to the surface of the second insulating layer at the outer peripheral portion of the opening, so that it is stable against tensile stress generated due to a difference in thermal expansion between the insulating layer and the conductor layer, No electrical connection failure occurs between the via conductor layers. The printed wiring board of the present invention has high stability and reliability against thermal stress. The present invention significantly improves the reliability, especially in printed wiring boards having current and future fine via holes.
[Brief description of the drawings]
FIG. 1 is a diagram showing a cross section of a conventional via hole.
FIG. 2 is a diagram showing a cross section of one embodiment of a via hole portion of the printed wiring board of the present invention.
FIG. 3 is a diagram showing a cross section of another embodiment of the via hole portion of the printed wiring board of the present invention.
FIG. 4 is a diagram showing a flow of a method for manufacturing a printed wiring board of the present invention.
FIG. 5 is an enlarged view of a cross section of a via hole portion formed by the manufacturing method of the present invention.
[Explanation of symbols]
1, 4, 11, 14: insulating layers 2, 5, 12, 15: conductor layers 3, 13, 30: openings (holes)
16: inner peripheral surface 18: bonding surface 17: insulating layer surface 19: flat surface 20: outer peripheral portion 21: fringe region 22: conductor portion

Claims (8)

A first conductor formed on the first insulating layer;
A second insulating layer formed on the first insulating layer including the first conductor;
A hole provided in the second insulating layer on the first conductor and reaching the first conductor;
A second conductor that covers at least the inner peripheral surface of the hole and the surface of the second insulating layer around the opening of the hole, and that is connected to the first conductor;
The first conductor and the second conductor are joined below the contact surface between the first conductor and the second insulating layer at the bottom of the hole, and the diameter of the joint surface is the diameter at the bottom of the hole. A printed wiring board having a via hole, wherein the printed wiring board is larger than an opening diameter of the second insulating layer. A first conductor formed on the first insulating layer;
A second insulating layer formed on the first insulating layer including the first conductor;
A hole provided in the second insulating layer on the first conductor and reaching the first conductor;
A second conductor that covers at least the inner peripheral surface of the hole and the surface of the second insulating layer around the opening of the hole, and that is connected to the first conductor;
A print having a via hole, characterized in that the second conductor has a fringe region at the bottom of the hole at an outer peripheral portion of the opening of the second insulating layer, the fringe region being joined to a surface of the second insulating layer. Wiring board. 2. The printed wiring board according to claim 1, wherein a diameter of a joint surface between the first conductor and the second conductor is smaller than a width of the first conductor. 3. A first conductor formed on the first insulating layer;
A second insulating layer formed on the first insulating layer including the first conductor;
A hole provided in the second insulating layer on the first conductor and reaching the first conductor;
A second conductor that fills the hole and covers at least the surface of the second insulating layer around the opening of the hole and connects to the first conductor;
The first conductor and the second conductor are joined below the contact surface between the first conductor and the second insulating layer at the bottom of the hole, and the diameter of the joint surface is the diameter at the bottom of the hole. A printed wiring board having a via hole, wherein the printed wiring board is larger than an opening diameter of the second insulating layer. A method for manufacturing a printed wiring board,
(A) providing a first insulating layer;
(B) providing a first conductor layer on the first insulating layer;
(C) providing a second insulating layer on the first insulating layer including the first conductor layer;
(D) providing a hole to the first conductive layer in the second insulating layer on the first conductive layer;
(E) providing an opening having a diameter larger than the opening diameter at the bottom of the hole in the first conductor layer facing the hole;
(F) forming a second conductor layer that fills the opening and covers at least the inner peripheral surface of the hole and the surface of the second insulating layer around the opening of the hole;
A manufacturing method including: The second conductor layer filled in the opening has a fringe region joined to the surface of the second insulating layer at the bottom of the hole at the outer periphery of the opening of the second insulating layer. The manufacturing method according to claim 5, wherein The step (e) of providing the opening includes exposing a surface of the second insulating layer at an outer peripheral portion of the opening of the second insulating layer at a bottom of the hole. Item 5. The manufacturing method according to Item 5. 6. The method according to claim 5, wherein the step (e) of providing the opening includes a step of etching the first conductor layer by wet etching.

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