JPH11186346A - Substrate for semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid wiring failures due to expansion of bubbles between a polyimide film and Cu layer by laminating conductive layers made in desired shapes o both sides of a polyimide film, without placing adhesive layers between this film and any of the conductive layers. SOLUTION: A manufacturing method comprises the steps of forming Cu layers 11 on both sides of a polymide film 10 without inserting any adhesive, punching to form sprocket holes 12 at both ends of this material, coating a liq. resist 13 on both sides thereof, patterning, etching to form wirings 14 on both sides, forming semiconductor chip connecting lands 16 continuously from the wirings 14 with leaving the Cu layer on the surface with the formed lands 16, but the Cu layer from the other surface, forming vias 17, plating Cu to form a Cu layer 18 and Ni layer, mounting a semiconductor ship 20, and encapsulating with a resin and forming solder balls 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device substrate having a conductor layer made of a copper layer on both surfaces of a polyimide film and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as typified by personal computers and the like, electronic devices are required to have higher density, smaller size, and thinner. For this reason, even in a semiconductor device substrate in which a semiconductor chip is mounted thereon and mounted on a printed wiring board serving as a parent substrate, a semiconductor device substrate capable of higher-density wiring and capable of being reduced in size and thickness has been developed. It has been demanded. As an example of such a semiconductor device substrate, one shown in FIG. 3 is known. By applying a conventional TAB technique, conductive layers are formed on both sides, and the conductive layers on both sides are connected by vias.

[0003] This technique will be described. First, FIG.
As shown in (a), a material in which a copper foil 102 is formed on one surface of a polyimide film 101 is prepared. This is obtained by coating a copper foil with a polyimide varnish and curing. Then, the adhesive 103 is applied to the surface of the polyimide film on which the copper foil is not formed, and is temporarily dried (FIG. 3B). Next, the sprocket hole 104, the via hole 105, the device hole 10
6 is processed (FIG. 3C). The diameter of the via hole 105 is reduced due to the demand for high-density wiring, and a technique of forming the hole by laser processing or etching using hydrazine or the like is known. Subsequently, the copper foil 107 is bonded to the surface on the adhesive side (FIG. 3D).

Further, a copper layer 108 is formed by performing electroless plating on both sides and subsequently performing electrolytic plating. At this time, a copper layer is also formed in the via hole to form the via 109 (FIG. 3E). The vias electrically connect the copper layers on both sides. Thereafter, by forming a resist on both surfaces and etching the resist, the wiring 11 is formed.
0 is formed (FIG. 3F). At this time, the inner leads 111 and the like for connecting to the semiconductor chip are also formed. Then, a solder resist 112 is formed on both surfaces to obtain a semiconductor device substrate (FIG. 3G).

[0005]

However, a first problem with such a semiconductor device substrate is that the conduction reliability of vias is not sufficient. This is due to the fact that when forming holes for vias in the polyimide film, residues of the adhesive bonding the polyimide film and the conductive layer are generated in the holes and cannot be sufficiently removed. For example, in the step of forming a metal film in the via hole, it was considered that this would hinder film adhesion.

[0006] Taking the prior art described above as an example, FIG.
The device hole 106 and the sprocket hole 10
4. This is when the via hole 105 is processed. When punching is performed, if the die is punched out from the adhesive 103 side, the thread-pulled adhesive adheres into the hole and becomes a residue. Also, when punching from the opposite surface, the adhesive from which the thread has been drawn adheres to the adhesive surface near the hole, and when bonding the conductive layer later, it appears as irregularities in the conductive layer, lowering the precision of wiring formation. . In addition, even if laser processing is performed instead of punching, the adhesive is scattered and adheres to the inside of the hole to form a residue. When the etching is performed, the adhesive is not sufficiently removed by the etching liquid for the polyimide film, and the adhesive becomes a residue.

As described above, when a residue is formed in the via hole, the residue is removed by cleaning with a chemical solution. During processing, residues of the polyimide film are also generated, but it is more difficult to remove residues of the adhesive than residues of the polyimide film. In addition, as the diameter of the via is reduced, a phenomenon occurs in which bubbles in the hole cannot be completely removed at the time of cleaning with the chemical solution, and the chemical solution does not enter the hole. For this reason, there has been a problem that the residue is difficult to be removed, for example, when copper is sputtered or plated, a copper film is hardly adhered, and the conduction reliability is reduced.

A second problem is that a defect such as disconnection occurs in the conductive layer in a semiconductor chip mounting process or the like. The cause of this is the process of applying the adhesive bonding the polyimide film and the conductive layer, or sticking the foil to be the conductive layer, in order to entrap the air bubbles, the generated air bubbles are caused by the heat history in the mounting process etc. It was thought that the wiring expanded and directly caused the disconnection of the wiring, or a crack occurred in the adhesive, and as a result, a defect such as the disconnection of the wiring occurred. With the increase in wiring density, the width of the connection lands for wiring or semiconductor chips, and the connection lands for the parent board are becoming increasingly narrower, and the possibility of failure such as disconnection in such wiring is increasing. Is growing.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, eliminates via conduction failure due to adhesive residue, eliminates wiring failure due to expansion of bubbles between the polyimide film and the copper layer, and improves connection reliability. It is an object of the present invention to provide a semiconductor device substrate having high characteristics and a method for manufacturing the same.

[0010]

In order to solve the above problems, in the invention according to claim 1, a conductive layer processed into a desired shape is laminated on both surfaces of a polyimide film and formed on the polyimide film. In a semiconductor device substrate in which the conductive layers on both surfaces are electrically connected by vias, no adhesive layer is provided between the polyimide film and any of the conductive layers.

[0011] According to such a means, no adhesive residue is generated when the via hole is formed in the polyimide film, so that the adhesion failure of the metal film in the via due to the adhesive residue is prevented. In addition, via conduction failure can be eliminated. Also, since there is no adhesive layer, apply the adhesive bonding the polyimide film and the conductive layer,
Alternatively, in the step of adhering a foil to be a conductive layer, an adhesive layer such as bubbles are entrapped in the adhesive layer, between the adhesive layer and the polyimide film or between the adhesive layer and the foil to be the conductive layer. Does not cause a defect such as disconnection of the wiring due to the existence of the defect.

According to a second aspect of the present invention, in the semiconductor device substrate according to the first aspect, the connection reliability between the via and the conductive layer is further ensured. Item 2. The semiconductor device substrate according to Item 1, wherein the via is connected to the conductive layer in a state where the bottom of the via is closed by the conductive layer on one surface.

In the semiconductor device substrate according to the first aspect of the present invention, since there is no adhesive layer between the polyimide film and the conductive layer, a via hole is formed in the conductive layer on one side. When the polyimide film is removed when forming in a closed state, the adhesive layer does not remain and the conductive layer on the one surface is completely exposed. Therefore, in the via hole in that state, a conductive layer is formed by means such as sputtering or plating, and the bottom of the via is closed by the conductive layer on one surface,
When connected to the conductive layer, the portion of the formed conductive layer at the bottom of the via is reliably connected to the conductive layer on the one surface, so that excellent connection reliability can be obtained.
In the means described above, the residue of the adhesive which is difficult to remove does not occur, but the generation of the residue of the polyimide film when perforating the polyimide film cannot be avoided. For example, when punching by punching, chips are generated, and even when laser processing is performed, a residue of molten polyimide is generated on the wall surface. Also in the case of etching, the residue of the polyimide film in the etching solution adheres.

[0014] Such removal of the residue is conventionally performed by cleaning with a chemical solution. However, as the diameter of the via is reduced, the phenomenon that the bubbles in the holes cannot be completely removed at the time of cleaning with the chemical solution and the chemical solution does not enter the holes. And the residue is difficult to remove. In addition, when the holes are formed by etching, there is a problem that the etching liquid does not similarly enter the holes, resulting in poor etching. Further, there is also a problem that a plating solution for forming a via thereafter does not similarly enter the holes, resulting in poor plating or uniform plating. Also, during sputtering, a relatively thick film is formed near the opening of the via hole and at the bottom, and there is a problem that the other portions are slightly thinner.

The invention described in claim 3 has been made in view of such a problem. That is, the invention described in claim 3 is
The semiconductor device substrate according to claim 1 or 2, wherein the via has a tapered shape gradually expanding toward one opening.

In the case where the bottom of the via is connected to the conductive layer in a state where the bottom of the via is closed by the conductive layer on one surface, the via is not closed by the conductive layer. It is characterized by a tapered shape that gradually spreads toward the surface. By such means, chemicals,
An etching solution, a plating solution, a cleaning solution, and the like easily penetrate into the holes, so that there is no residue of the polyimide film, uniform etching and plating can be performed, and cleaning in each step can be sufficiently performed. . Even when sputtering is used, a uniform conductive film can be formed. Therefore, the conduction reliability of the via is improved.

In such a means, the angle of the taper is preferably about 5 ° to 45 °, more preferably 7 ° to 45 °, between the thickness direction of the polyimide film and the wall surface of the via.
About 20 ° is preferable. If the angle is smaller than 5 °, the above-mentioned effects cannot be sufficiently obtained. If the angle exceeds 45 °, the area of the opening increases, and the density of the wiring decreases.

The fourth aspect of the present invention has been made to improve the connection reliability of vias in a semiconductor device substrate in which the above-described high-density wiring is required and the vias are reduced in diameter.

According to a fourth aspect of the present invention, in the semiconductor device substrate according to any one of the first to third aspects,
The via is characterized in that a metal is sputtered into a hole formed in a polyimide film by laser processing, and the metal is electrolytically plated.

According to such a means, a metal film is formed with high reliability even in a small diameter via. Further, since electrolytic plating is used, a thick metal film can be formed in a short time and at low cost. Claim 5
The described invention is technically limited in consideration of mounting the above-described semiconductor device substrate on a parent substrate.

According to a fifth aspect of the present invention, in the semiconductor device substrate according to any one of the first to fourth aspects, the via is formed of a conductive ball for electrical connection with a parent substrate. It is characterized by being for insertion.

According to the present invention, since the via is used for inserting the conductive ball, the conductive ball can be easily inserted, and the reliability of conduction between the bottom side of the via and the mounting surface on the parent board is high. Also, the electric resistance can be reduced. The invention according to claim 6 is also technically limited in consideration of mounting the above-described semiconductor device substrate on the parent substrate.

That is, according to a sixth aspect of the present invention, in the semiconductor device substrate according to any one of the first to fourth aspects, the via is filled with a solder resist.

According to the present invention, since the via is filled with the solder resist, there is no fear that the metal film in the via is peeled off even when heat is applied in a mounting process to the parent substrate or the like. Greatly enhances the continuity reliability. The invention according to claim 7 provides a method for manufacturing a semiconductor device substrate for solving the above-mentioned problems.

That is, the present invention relates to a method of manufacturing a substrate for a semiconductor device, comprising: (1) a step of preparing a material in which a conductive layer is formed on substantially the entire surface of both surfaces of a polyimide film without interposing an adhesive layer; 2) a step of forming a photoresist on the conductive layers on both surfaces and etching the conductive layer; and (3) a step of perforating the polyimide tape from one surface.
(4) a step of removing the photoresist; and (5) a step of forming a via layer by forming a copper layer in at least the perforated hole.

According to such a method, a residue of an adhesive is not generated when a hole for a via is formed in a polyimide film, and therefore, a method of manufacturing a substrate for a semiconductor device, which can eliminate poor conduction of a via. Can be provided. Further, since air bubbles are not entrained between the polyimide film and the foil serving as the conductive layer, it is possible to provide a method for manufacturing a semiconductor device substrate which does not cause a defect such as disconnection in wiring. The invention of claim 8 is a technical limitation of the invention of claim 7.

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device substrate according to the seventh aspect, in the step (3),
It is characterized in that it is perforated in a tapered shape gradually expanding toward the surface to be perforated.

The use of laser light can be achieved, for example, by shaping the laser light while spiraling it. When drilling by etching, by changing the etching conditions,
Achievable. According to such means, a chemical solution, an etching solution, a plating solution, a cleaning solution, and the like easily enter the holes, and therefore, no residue of the polyimide film is generated, and uniform etching and plating can be performed. Cleaning in the process can be sufficiently performed. Further, even when sputtering is used, a uniform conductive film can be formed. Therefore, a via can be formed with high conduction reliability.

Next, the invention according to claim 9 is important in the means according to claim 7 described above. It is important that the via hole is drilled with high positional accuracy, and that the thickness of the via hole is reduced. The metal film is formed in a state where there is no unevenness or chipping, and in the means according to the eighth aspect, it is additionally important to appropriately control the angle of the taper.

The ninth aspect of the present invention is directed to simultaneously solving such a demand. That is, in the method of manufacturing a semiconductor device substrate according to the seventh or eighth aspect, (3) It is characterized in that a laser beam is used as the perforating means in the step, and sputtering is used as the copper layer forming means in the step (5).

By using a laser beam as the perforating means, it is possible to perforate the via hole with high positional accuracy without shifting the via hole, and in the case of forming a tapered shape, while shaking the laser beam, By controlling the incident angle, it is possible to perforate at a desired taper angle. Also, by using sputtering, it is possible to form a metal film in a state where there is no unevenness or chipping in the thickness of the via hole. For example, the plating solution does not enter the hole due to bubbles in the hole, and therefore, there is no defect such as plating not being performed and the metal film being chipped. Therefore, a via can be formed with high conduction reliability.

The invention according to claim 10 is the same as the invention according to claim 7.
10. After performing each of the steps (1) to (5) in the method for manufacturing a semiconductor device substrate according to any one of claims 9 to 9,
Further, a step of filling the via with a solder resist is performed. As a method of filling the holes,
Examples include a method of printing using a silk screen plate, a method of applying an entire surface and removing unnecessary portions in an exposure and development step, and a method of injecting a solder resist into a hole using a dispenser or the like. According to such means, the via can be reliably filled with the solder resist. Therefore, even if heat is applied in the mounting process to the parent board, there is no possibility that the metal film in the via is peeled off, and the via conduction reliability is greatly enhanced.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below based on examples.

[Embodiment 1] FIG. 1 shows a first embodiment of the present invention.
It will be described according to. First, as shown in FIG. 1A, a material was prepared in which a 18 μm thick copper layer 11 was formed on both sides of a 40 μm thick polyimide film 10 without using an adhesive. To form a copper layer without using an adhesive, a copper foil is coated with a polyimide varnish and cured, and on the other side of the obtained polyimide film, a thin copper layer is formed by electroless plating and sputtering. And thickening by electrolytic plating. A copper layer having a thickness of about 18 to 25 μm can be particularly preferably used.

At both ends of this material, sprocket holes 12 were formed by punching (FIG. 1B). Then, a liquid resist having a thickness of 15 μm was applied to both surfaces.
The coating thickness is preferably about 10 μm to 20 μm. Further, as shown in FIG. 1 (c), the resist 13 is patterned by exposing and developing, and by etching,
Wirings 14 were formed on both sides (FIG. 1D). On the copper layer on one side (the copper layer on the upper surface side in FIG. 1D), a semiconductor chip connection land 16 was formed simultaneously with the wiring and continuously from the wiring 14 by etching. Via forming part 1
In No. 5, the copper layer was left on the surface on which the semiconductor chip connection lands were formed, and the copper layer was removed on the other surface. After removing the resist, via holes 17 having a hole diameter of 100 μm were formed from the other surface by laser processing using a carbon dioxide laser (FIG. 1E). By drilling while oscillating the laser light in a spiral shape, a tapered processing gradually expanding toward the opening surface was performed. next,
The pores were cleaned using potassium permanganate.
The bottom of the via hole thus formed is closed by the copper layer on the one surface. The angle between the wall surface and the thickness direction of the polyimide film was 20 °.

In this embodiment, when the semiconductor device substrate is mounted on the parent substrate, a solder ball is inserted into the via,
The vias are mounted on the mother board, and the vias serve as holes for inserting solder balls in addition to the function of interconnecting the wiring layers on both surfaces. Subsequently, copper was sputtered on both sides to form a copper layer having a thickness of 0.3 μm. Further, electrolytic copper plating was performed to form a copper layer 18 having a thickness of 10 μm, and a nickel layer (not shown) formed by nickel plating having a thickness of 3 μm was formed thereon (FIG. 1F). Nickel plating may be either electrolytic plating or electroless plating. The thickness is preferably about 0.5 μm to 3 μm. When the semiconductor chip connection electrode and the semiconductor chip are connected by wire bonding, the thickness is preferably about 2 μm to 3 μm on the semiconductor chip connection electrode. It is preferable to apply thick nickel plating. Then, gold plating (not shown) was performed on the nickel layers on both surfaces.

Note that palladium or palladium alloy plating may be applied instead of gold plating, and tin plating may be applied directly to the copper layer by about 0.2 μm instead of applying nickel plating or gold plating. . Then, a solder resist 19 was formed on portions other than the semiconductor chip connection lands and via openings and the vicinity thereof. Thus, a semiconductor device substrate as shown in FIG. 1 (g) was manufactured. The result of the visual inspection showed no particular problem such as poor adhesion of the metal film in the via, and there was no problem.

As shown by the broken line in FIG.
After the semiconductor chip 20 is mounted and connected by the bonding wires 21, the semiconductor chip mounting portion is sealed with a resin (not shown) for protection, and a solder ball is inserted into the via and heat-treated. Then, solder balls 22 for connection to the parent substrate were formed. Visual inspection performed after such a process did not show any defect such as disconnection in the wiring.

[Example 2] The manufacturing method is almost the same as that of Example 1, except that a land 41 for connection with the parent substrate was formed at the time of forming the wiring at a position close to the opening of the via (Fig. 2 (a)). Then, by the same laser processing as in Example 1, the via hole 42 having a hole diameter of 80 μm was formed into a tapered shape gradually expanding toward the opening surface. Then, the inside of the hole was cleaned using potassium permanganate. As in the first embodiment, the bottom is closed by the copper layer. The angle between the wall surface and the thickness direction of the polyimide film was 7 ° (FIG. 2B).

The semiconductor device substrate of this embodiment is of a type in which a via is not used for inserting a solder ball, and a solder ball is formed on the land for connection with the parent substrate.
In such a case, the diameter of the via may be 50 μm to 100 μm.
The degree is preferred. Then, in the same manner as in Example 1, sputtering and electrolytic copper plating were performed to form a copper layer 43 as shown in FIG. 2C. Before the formation of the solder resist, the solder resist is filled and printed in the via using a silk screen plate. Thereafter, the solder resist 44 is removed from the lands for connecting the semiconductor chip and the lands for connecting to the parent substrate. Formed in parts. In this way,
A semiconductor device substrate as shown in FIG. 2D was manufactured.
As in Example 1, the result of the visual inspection showed no particular problem such as poor adhesion of the metal film in the via, and there was no problem.

As shown by the broken line in FIG.
After the semiconductor chip 45 is mounted and connected by the bonding wire 46, the semiconductor chip mounting portion is sealed with a resin (not shown) for protection, and a solder ball is mounted on a land for connection with the parent substrate. By heat treatment,
Solder balls 47 for connection with the parent substrate were formed. Visual inspection performed after such a process did not show any defect such as disconnection in the wiring.

[0042]

According to the first aspect of the present invention, it is possible to obtain a highly reliable semiconductor device substrate because a conduction failure of a via is eliminated and a failure such as a disconnection does not occur in a wiring. Can be. According to the second aspect of the present invention, the portion of the formed conductive layer at the bottom of the via is reliably connected to the conductive layer on the one surface, and excellent connection reliability can be obtained. A highly reliable semiconductor device substrate can be obtained. According to the third aspect of the present invention, since the reliability of via conduction is improved, a highly reliable semiconductor device substrate can be obtained. According to the fourth aspect of the present invention, a metal film is formed with high reliability even in a small-diameter via, and a thick metal film can be formed in a short time at low cost. A highly reliable semiconductor device substrate can be obtained at low cost. Furthermore, according to the fifth aspect of the present invention, since the via is used for inserting the conductive ball, the conductive ball can be easily inserted, and the conduction reliability between the bottom side of the via and the mounting surface on the parent board can be improved. Therefore, a semiconductor device substrate having high electrical reliability and easily forming conductive balls for connection can be obtained. Further, according to the invention of claim 6, there is no possibility that the metal film in the via is peeled off, and the conduction reliability of the via is increased, so that a semiconductor device substrate having high electrical reliability can be obtained.

According to the seventh aspect of the present invention, it is possible to eliminate the conduction failure of the via and to prevent the occurrence of the failure such as the disconnection of the wiring. A manufacturing method can be obtained. Claim 8
According to the ninth aspect, a via can be formed with high conduction reliability. A method for manufacturing a semiconductor device substrate having high electrical reliability can be obtained. According to the tenth aspect of the present invention, there is no possibility that the metal film in the via is peeled off, and thus the conduction reliability of the via is increased. Therefore, a method of manufacturing a semiconductor device substrate having high electrical reliability is obtained. be able to.

[0044]

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a semiconductor device substrate according to a first embodiment of the present invention.

FIG. 2 is an explanatory view of a semiconductor device substrate according to a second embodiment of the present invention.

FIG. 3 is an explanatory view of a semiconductor device substrate according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Polyimide film 11, 18, 43 Copper layer 12 Sprocket hole 13 Resist 14 Wiring 15 Via formation part 16 Land for semiconductor chip connection 17, 42 Via hole 19, 44 Solder resist 20, 45 Semiconductor chip 21, 46 Bonding wire 22 Solder Ball 41 Land for connection to parent board 101 Polyimide film 102 Copper foil 103 Adhesive 104 Sprocket hole 105 Via hole 106 Device hole 107 Copper foil 108 Copper layer 109 Via 110 Wiring 111 Inner lead 112 Solder resist

Claims (10)

[Claims] 1. A semiconductor device in which a conductive layer processed into a desired shape is laminated on both surfaces of a polyimide film, and the conductive layers on both surfaces are electrically connected by vias formed in the polyimide film. A substrate for a semiconductor device, wherein the substrate has no adhesive layer between the polyimide film and any of the conductive layers. 2. The semiconductor device substrate according to claim 1, wherein the via is connected to the conductive layer in a state where the bottom of the via is closed by the conductive layer on one surface. 3. The semiconductor device substrate according to claim 1, wherein said via has a tapered shape gradually expanding toward one opening. 4. The method according to claim 1, wherein the via is formed by sputtering a metal in a hole formed in a polyimide film by laser processing, and further by electroplating the metal. 4. The substrate for a semiconductor device according to claim 3. 5. The substrate for a semiconductor device according to claim 1, wherein said via is for inserting a conductive ball for electrical connection with a parent substrate. 6. The semiconductor device substrate according to claim 1, wherein the via is filled with a solder resist. 7. A step of preparing a material in which a conductive layer is formed on almost the entire surface of both surfaces of a polyimide film without interposing an adhesive layer. (2) A step of forming a photoresist on the conductive layers on both sides and etching the conductive layers. (3) a step of perforating the polyimide tape from one surface. (4) A step of removing the photoresist. (5) forming a copper layer in at least the perforated hole to form a via; A method for manufacturing a substrate for a semiconductor device, comprising: 8. The method of manufacturing a semiconductor device substrate according to claim 7, wherein in the step (3), the hole is formed in a tapered shape gradually expanding toward the surface to be holed. 9. The method according to claim 7, wherein a laser beam is used as the perforating means in the step (3), and sputtering is used as the copper layer forming means in the step (5).
The manufacturing method of the substrate for semiconductor devices as described in the above. 10. A method of manufacturing a substrate for a semiconductor device according to claim 7, wherein a step of filling a solder resist in said via is performed. A method for manufacturing a substrate for a semiconductor device.