JP2008235624A - Wiring circuit board and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring circuit board which has an insulating resin layer and a wiring conductor firmly bonded to each other and has superior connection reliability, among wiring conductors in a via hole with high wiring density and less warpage or deformation, and to provide a method of manufacturing the wiring circuit board. <P>SOLUTION: The wiring circuit board comprises a lower insulating resin layer and a lower wiring conductor, an upper insulating resin layer laminated on the lower insulating resin layer and the lower wiring conductor, while having a via hole 9 reaching the lower wiring conductor, and an upper wiring conductor as a metal-plated layer formed so as to cover from the lower wiring conductor within the via hole 9 to the upper insulating resin layer. The metal-plated layer includes a first metal-plated layer 5A, formed so as to fill a lower part in the interior of the via hole 9 and a second metal-plated layer 5B formed so as to cover from the first metal-plated layer 5A to the upper insulating resin layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a high-density multilayer wiring board suitable for mounting electronic components such as semiconductor integrated circuit elements and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, as a semiconductor integrated circuit element that is an electronic component, there is a so-called peripheral type semiconductor integrated circuit element in which a large number of electrode terminals are arranged along the outer periphery of one main surface thereof. As a method for mounting such a semiconductor integrated circuit element on a wiring board, there is a method of connecting by flip chip connection.

  The flip-chip connection means that a part of the wiring conductor for connecting the electronic component provided on the wiring board is exposed corresponding to the arrangement of the electrode terminals of the electronic component, and the exposed portion of the wiring conductor for connecting the electronic component and the above-mentioned In this method, the electrode terminals of the electronic component are opposed to each other, and these are electrically connected via conductive bumps made of solder, gold or the like.

  Recently, the first electronic component is mounted on the wiring board by such flip-chip connection, and another second electronic component is mounted thereon by solder ball connection or wire bond connection to the wiring board. Increasing the mounting density of electronic components.

  FIG. 8 shows a conventional wiring board in which a peripheral type semiconductor integrated circuit element as a first electronic component is mounted by flip-chip connection, and a semiconductor element mounting substrate as a second electronic component is further soldered to the substrate. FIG. 9 is a plan view showing the wiring board of FIG. 8.

  As shown in FIGS. 8 and 9, the conventional wiring board 110 has a plurality of build-up insulations on the upper and lower surfaces of the core insulating substrate 103 in which the core wiring conductors 102 are arranged from the upper surface to the lower surface. Resin layers 104 and build-up wiring conductors 105 are alternately stacked, and a protective solder resist layer 106 is deposited on the outermost surface.

  A plurality of through holes 107 are formed from the upper surface to the lower surface of the core insulating substrate 103, and the core wiring conductor 102 is attached to the upper and lower surfaces of the insulating substrate 103 and the inner surface of the through hole 107. An embedding resin 108 is filled in the inside 107. A plurality of via holes 109 are formed in each of the build-up insulating resin layers 104, and a build-up wiring conductor 105 is formed on the surface of each insulating resin layer 104 and the inner surface of the via holes 109. ing.

  A part of the wiring conductor 105 deposited on the outermost insulating resin layer 104 on the upper surface side of the wiring substrate 110 is electrically conductive bump B1 on the electrode terminal of the semiconductor integrated circuit element E1 as the first electronic component. A first wiring pattern portion 105A having a first connection portion 105a that is electrically connected via flip-chip connection, and a plurality of the first wiring pattern portions 105A are formed side by side. Further, the other part of the wiring conductor 105 deposited on the outermost insulating resin layer 104 on the upper surface side of the wiring substrate 110 is soldered to the electrode terminal of the semiconductor element mounting substrate E2 as the second electronic component. A second wiring pattern portion 105B having a second connection portion 105b electrically connected by solder ball connection via a ball B2, and a plurality of the second wiring pattern portions 105B are formed side by side.

  Of the first wiring pattern portion 105A and the second wiring pattern portion 105B, the first connection portion 105a and the second connection portion 105b are exposed from the solder resist layer 106, and the semiconductor integrated circuit element E1 is exposed to the first connection portion 105a. The electrode terminals of the semiconductor element mounting substrate E2 are electrically connected to the second connection portion 105b via the solder balls B2, and the electrode terminals are electrically connected via the conductive bumps B1 made of solder, gold, or the like.

  On the other hand, a part of the wiring conductor 105 deposited on the outermost insulating resin layer 104 on the lower surface side of the wiring board 110 is for external connection that is electrically connected to the wiring conductor of the external electric circuit board. A third wiring pattern portion 105C having a third connection portion 105c, and a plurality of the third wiring pattern portions 105C are formed side by side. Of the third wiring pattern portion 105C, the third connection portion 105c is exposed from the solder resist layer 106, and the wiring conductor of the external electric circuit board is electrically connected to the third connection portion 105c via the solder ball B3. Connected.

  Then, after electrically connecting the electrode terminal of the semiconductor integrated circuit element E1 and the first connection portion 105a via the conductive bump B1, the gap between the semiconductor integrated circuit element E1 and the wiring substrate 110 is made of epoxy resin or the like. Filling resin U <b> 1 called underfill made of thermosetting resin is filled, and semiconductor integrated circuit element E <b> 1 is mounted on wiring substrate 110. Furthermore, the semiconductor element mounting board E2 is mounted on the wiring board 110 by electrically connecting the electrode terminal of the semiconductor element mounting board E2 and the second connection portion 105b thereon via the solder ball B2. A plurality of electronic components are mounted on the wiring board 110 with high density. Such a wiring board 110 is manufactured by, for example, the following method.

  First, an insulating sheet for the insulating substrate 103 in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin is prepared. Next, copper foil is stuck on both sides of the insulating sheet, and the thermosetting resin in the insulating sheet is thermoset to obtain a double-sided copper-clad plate. A through-hole 107 penetrating the upper and lower surfaces of the double-sided copper-clad plate is drilled, and the inside of the through-hole 107 is desmeared with an aqueous permanganate solution. The desmear process means a process for removing unnecessary resin residues.

  After the desmear treatment as described above, a copper plating layer made of electroless copper plating and electrolytic copper plating is deposited on the inner wall of the through hole 107 and the surface of the copper foil, and the upper and lower copper foils are connected to each other through the through hole 107. It is electrically connected with the copper plating layer inside. Then, after filling the inside of the through hole 107 with the embedding resin 108, the copper foil and the copper plating layer on the upper and lower surfaces are etched into a predetermined pattern, whereby the copper foil is formed on the upper and lower surfaces of the core insulating substrate 103 and the inner wall of the through hole 107. A core wiring conductor 102 made of copper or a copper plating layer is formed.

  Next, a resin film for the insulating resin layer 104 in which an inorganic insulating filler is dispersed in a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin is stuck on the insulating substrate 103 for the core and the wiring conductor 102. The insulating resin layer 104 is formed by thermosetting the thermosetting resin in the resin film. A via hole 109 is drilled in the insulating resin layer 104 by laser processing, and the inside of the via hole 109 is desmeared with an alkali permanganate aqueous solution. Wiring conductors 105 made of plating and electrolytic copper plating are formed simultaneously on the upper and lower surfaces.

  At this time, if the surface of the insulating resin layer 104 is roughened in advance or is roughened by desmearing of the via holes 109, the fine irregularities on the surface of the insulating resin layer 104 subjected to the roughening treatment and over The insulating conductor layer 104 and the wiring conductor 105 are firmly attached to each other, so that the electroless copper plating and the wiring conductor 105 made of electrolytic copper plating are satisfactorily engaged with each other.

  Then, the build-up portion is formed by repeating the formation of the next insulating resin layer 104 and the wiring conductor 105 a plurality of times, and finally, the thermosetting resin paste or film having photosensitivity is formed on the wiring conductor 105. After being laminated on the outer insulating resin layer 104, exposure and development are performed so as to have openings that expose the first connection part 105a and second connection part 105b for connecting electronic components and the third connection part 105c for external connection. The solder resist layer 106 is formed by curing, whereby a plurality of build-up insulating resin layers 104 are formed on the upper and lower surfaces of the core insulating substrate 103 on which the core wiring conductors 102 are disposed from the upper surface to the lower surface. And build-up wiring conductors 105 are alternately laminated, and a protective solder resist layer 106 is deposited on the outermost surface. Build-up multilayer wiring board 110 made is manufactured.

  In recent years, such a build-up multilayer wiring board 110 has been increasingly required to have a thinner thickness and a higher wiring density, and the semiconductor integrated circuit element E1 and the semiconductor element mounting board E2 mounted thereon or an external electric circuit. In order to maintain good electrical connection reliability with the circuit board, it is required to suppress warping and deformation after mounting of the semiconductor integrated circuit element E1 and the semiconductor element mounting board E2.

  Warpage and deformation after mounting of the build-up wiring board 110 are mainly caused by thermal stress generated due to a difference in thermal expansion coefficient between the build-up wiring board 110 and the semiconductor integrated circuit element E1 mounted thereon. . The insulating substrate 103 and the insulating resin layer 104 constituting the general build-up wiring board 110 have a thermal expansion coefficient (XY direction) of about 20 to 100 ppm / ° C., whereas the thermal expansion of the semiconductor integrated circuit element E1. The coefficient is as small as about 3-7 ppm / ° C. Therefore, a large amount of an inorganic insulating filler of a low thermal expansion material such as fused silica (thermal expansion coefficient 0.5 ppm / ° C.) is filled in the thermosetting resin constituting the insulating substrate 103 and the insulating resin layer 104. The thermal expansion coefficient (XY direction) of the insulating substrate 103 and the insulating resin layer 104 is lowered to about 8 to 17 ppm / ° C.

  However, when the thermosetting resin filled with a large amount of the inorganic insulating filler is applied to the insulating resin layer 104 for build-up, there are the following problems. That is, when a via hole is formed in the insulating resin layer 104 obtained by curing the thermosetting resin, and the inside of the via hole is desmeared with an alkaline permanganate aqueous solution, an inorganic insulating filler filled in a large amount in the thermosetting resin is obtained. Grain from the surface of the insulating resin layer 104 breaks down the fine irregular shape on the surface of the insulating resin layer 104. As a result, the wiring conductor 102 formed on the surface and the minute irregularities on the surface of the insulating resin layer 104 are engaged. And the wiring conductor 102 easily peels off from the insulating resin layer 104.

  Therefore, in Patent Document 1, after forming a roughened resist layer made of, for example, electroless copper plating on the surface of the roughened insulating resin layer for buildup, the insulating resin layer on which the roughened resist layer is formed is formed. After forming the via hole and then desmearing the inside of the via hole, the roughened resist layer is removed by etching or left without being etched, and in the via hole and the insulating resin layer or the remaining roughened resist layer. Discloses a method of forming a wiring layer by a semi-additive method.

  According to this method, since the surface of the insulating resin layer for buildup is protected by the roughened resist layer when the desmear treatment is performed in the via hole, the surface of the insulating resin layer for buildup is damaged by the desmear treatment. And a good roughened surface is maintained. Therefore, a wiring board in which the insulating resin layer for buildup and the wiring layer for buildup are firmly adhered can be obtained.

  However, according to the method of Patent Document 1, when the wiring layer is formed by semi-additive method in the via hole and on the insulating resin layer after the roughened resist layer made of electroless copper plating is removed by etching, via hole formation When the roughened resist layer made of electroless copper plating is later removed by etching, the lower wiring layer exposed on the bottom surface of the via hole may be excessively etched. Such excessive etching is liable to deteriorate the connection reliability between the wiring layers in the via hole.

  In addition, when a wiring layer is formed by a semi-additive method in the via hole and on the roughened resist layer in a state where the roughened resist layer made of electroless copper plating is left without being etched away, the roughened resist layer on the insulating resin layer is formed. The electroless copper plating layer as the resist layer and the electroless copper plating layer as the semi-additive underlying conductive layer are overlapped, and the electroless copper plating layer on the insulating resin layer is thick. End up. Therefore, after the electrolytic copper plating layer is deposited on the electroless copper plating layer in a predetermined pattern, when the exposed electroless copper plating layer is removed by etching, the pattern of the electrolytic copper plating layer is also greatly etched at the same time. The pattern of the wiring layer tends to be thin, and the electroless copper plating is easier to etch than the electrolytic copper plating, so the electroless copper plating layer located under the electrolytic copper plating is greatly swept away, and the insulating resin layer As a result, the bonding strength between the wiring layer and the wiring layer is weakened.

  Furthermore, since the via hole is filled by a single semi-additive process, the via hole cannot be satisfactorily filled with the wiring layer when the aspect ratio of the via hole is large or the diameter of the via hole is large. A large dent is easily formed in the wiring conductor. If there is a large dent in the wiring conductor on the via hole in this way, when the upper via hole is provided on the lower via hole, the electrical connection reliability between the wiring conductors is greatly reduced between the upper and lower via holes. Become.

JP 2005-251894 A

  The problem of the present invention is that even when an insulating resin filled with a large amount of an inorganic insulating filler of a low thermal expansion material is used for the insulating resin layer of the build-up portion, the insulating resin layer and the wiring conductor are firmly adhered. In addition, it is to provide a thin wiring board with low warpage and deformation, and a method for manufacturing the same, with high density wiring excellent in connection reliability between wiring conductors in via holes.

  As a result of intensive studies to solve the above-mentioned problems, the present inventor has obtained the following knowledge. That is, a via hole is formed in the insulating resin layer with the metal foil remaining on the surface of the insulating resin layer for build-up, and then the first metal plating layer is deposited on the metal foil and in the via hole to a predetermined thickness. Then, the metal foil on the insulating resin layer and the first metal plating layer thereon are removed by etching so that a part of the first metal plating layer remains in the via hole, and then in the via hole and When forming a wiring conductor consisting of the second metal plating layer on the insulating resin layer, there is no risk that the lower wiring conductor in the via hole will be excessively etched, and the upper wiring conductor and the lower wiring in the via hole. The electrical connection reliability with the wiring conductor can be improved.

  In addition, when forming a wiring conductor composed of the second metal plating layer on the insulating resin layer, a thick electroless metal plating layer is not formed on the insulating resin layer, and therefore an accurate shape with a predetermined width is provided. These wiring conductors can be formed while maintaining sufficient bonding strength with the insulating resin layer. Further, the lower portion of the via hole is filled with the first metal plating layer, and the wiring conductor composed of the second metal plating layer is formed thereon, so that the first metal plating layer and the second metal plating layer thereon are formed in the via hole. The metal plating layer can be satisfactorily filled, so that no large recess is formed in the wiring conductor on the via hole, and even when the upper via hole is provided on the lower via hole, High-density wiring with excellent electrical connection reliability between the wiring conductors between the via holes can be obtained, and a thin wiring board with less warpage and deformation can be obtained.

That is, the wiring board and the manufacturing method thereof according to the present invention have the following configurations.
(1) A lower insulating resin layer, a lower wiring conductor formed on the surface of the lower insulating resin layer, and an upper layer having a via hole stacked on the lower insulating resin layer and the lower wiring conductor and reaching the lower wiring conductor A wiring board comprising: an insulating resin layer; and an upper wiring conductor composed of a metal plating layer deposited on the surface of the upper insulating resin layer from above the lower wiring conductor in the via hole, A first metal plating layer deposited on the lower wiring conductor in the via hole so as to fill a lower portion of the via hole; and the upper insulating resin layer from the first metal plating layer. And a second metal plating layer deposited on the surface of the wiring board.
(2) The wiring board according to (1), wherein the first metal plating layer includes an electroless metal plating layer and an electrolytic metal plating layer deposited on the electroless metal plating layer.
(3) The second metal plating layer according to (1) or (2), wherein the second metal plating layer includes an electroless metal plating layer and an electrolytic metal plating layer deposited on the electroless metal plating layer. Wiring board.

(4) A method of manufacturing a wiring board including a step of alternately laminating insulating resin layers and wiring conductors, the method including the following steps (a) to (e) in order: .
(A) A step of laminating an upper insulating resin layer having a metal foil on the surface thereof on a lower insulating resin layer having a lower wiring conductor on the surface (b) A part of the metal foil facing the lower wiring conductor (C) forming a via hole reaching the lower wiring conductor in the upper insulating resin layer in the removal portion (c) the metal foil, the upper insulating resin layer, and the lower wiring conductor exposed in the via hole On the surface, the first metal plating layer, the thickness of the first metal plating layer located on the lower wiring conductor is T1, the total thickness of the metal foil and the first metal plating layer located on the metal foil (2) The lower wiring conductor is formed by etching the first metal plating layer and the metal foil so that T1 and T2 satisfy the relationship of T1> T2. Up (E) removing the metal foil while leaving a part of the first metal plating layer remaining (e) the lower surface through the via hole on the exposed surface of the first metal plating layer and the upper insulating resin layer A process of depositing and forming an upper wiring conductor composed of a second metal plating layer electrically connected to the wiring conductor

(5) The wiring board according to (4), including a step of reducing the thickness of the metal foil by chemical etching or physical polishing after the step (a) and before the step (b). Production method.
(6) The method for manufacturing a wiring board according to (4) or (5), wherein in the step (b), a part of the metal foil facing the lower wiring conductor is removed by etching.
(7) The method for manufacturing a wiring board according to (4) or (5), wherein in the step (b), a part of the metal foil facing the lower wiring conductor is removed by laser processing.
(8) The method for manufacturing a wiring board according to any one of (4) to (7), wherein a desmear treatment in the via hole is performed after the step (b) and before the step (c).
(9) Any one of (4) to (8), wherein the first metal plating layer includes an electroless metal plating layer and an electrolytic metal plating layer deposited on the electroless metal plating layer. The manufacturing method of the wiring board as described in 2 ..
(10) Any one of (4) to (9), wherein the second metal plating layer includes an electroless metal plating layer and an electrolytic metal plating layer deposited on the electroless metal plating layer. The manufacturing method of the wiring board as described in 2 ..

  According to the present invention, even when an insulating resin filled with a large amount of an inorganic insulating filler of a low thermal expansion material is used for the insulating resin layer of the build-up portion, the insulating resin layer and the wiring conductor are firmly adhered. In addition, there is an effect that a thin wiring board with low warpage and deformation can be obtained with high-density wiring excellent in connection reliability between wiring conductors in via holes.

  Hereinafter, an embodiment of a wiring board and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment in which a peripheral type semiconductor integrated circuit element is mounted as a first electronic component by flip chip connection, and a semiconductor element mounting substrate as a second electronic component is mounted thereon by solder ball connection. It is a schematic sectional drawing which shows this wiring board. FIG. 2 is a plan view showing the wiring board of FIG. FIG. 3 is a partially enlarged sectional view showing the vicinity of the wiring conductor in the via hole according to the present embodiment.

  As shown in FIGS. 1 and 2, the wiring board 10 according to the present embodiment has a build-up structure on the upper and lower surfaces of the core insulating board 3 in which the core wiring conductors 2 are arranged from the upper surface to the lower surface. Insulating resin layers 4 and build-up wiring conductors 5 are alternately laminated, and a protective solder resist layer 6 is further deposited on the outermost surface.

  The core insulating substrate 3 has a thickness of about 0.05 to 1.5 mm. For example, a glass cloth in which a glass fiber bundle is woven vertically and horizontally is impregnated with a thermosetting resin such as a bismaleimide triazine resin or an epoxy resin. Made of electrically insulating material. The insulating substrate 3 functions as a core member of the wiring substrate 10. The thermosetting resin constituting the insulating substrate 3 is preferably filled with an inorganic insulating filler having a low thermal expansion coefficient such as fused silica at a high density of about 50 to 70% by mass. Thereby, the thermal expansion coefficient (XY direction) of the insulating substrate 3 can be lowered to about 8 to 17 ppm / ° C., and the wiring substrate 10 is caused by the difference in thermal expansion coefficient from the semiconductor integrated circuit element E1. Large warping can be effectively prevented.

  A plurality of through holes 7 having a diameter of about 0.05 to 0.3 mm are formed in the core insulating substrate 3 from the upper surface to the lower surface, and the upper and lower surfaces of the insulating substrate 3 and the inner surface of the through hole 7 are formed on the inner surface of the through hole 7. The wiring conductor 2 is attached. The core wiring conductor 2 is mainly formed of copper foil or electroless copper plating and electrolytic copper plating thereon on the upper and lower surfaces of the insulating substrate 3, and the electroless copper plating and its inner surface on the inner surface of the through hole 7. It is formed from the above electrolytic copper plating.

  The through hole 7 is filled with an embedded resin 8 made of a thermosetting resin such as an epoxy resin, and the wiring conductors 2 formed on the upper and lower surfaces of the insulating substrate 3 are connected to each other in the through hole 7. It is electrically connected through the conductor 2. The thermosetting resin constituting the embedded resin 8 is also made of about 40 to 60% by mass of a low thermal expansion coefficient inorganic insulating filler such as fused silica as in the thermosetting resin constituting the insulating substrate 3 described above. It is preferable to fill with high density. As a result, the thermal expansion coefficient (Z direction) of the embedded resin 8 can be as low as about 30 to 40 ppm / ° C., and the embedded resin is caused by the difference in thermal expansion coefficient (Z direction) from the insulating substrate 3. It is possible to effectively prevent peeling, cracking, deformation and the like from occurring.

  Such an insulating substrate 3 is formed by attaching a copper foil for the wiring conductor 2 on the upper and lower surfaces of a sheet of glass fabric impregnated with an uncured thermosetting resin, and then thermally curing the sheet, It is produced by performing drilling for the through hole 7 from the bottom to the bottom.

  In the wiring conductor 2, copper foil having a thickness of about 3 to 18 μm is stuck on the entire upper and lower surfaces of the sheet for the insulating substrate 3 as described above, and through holes 7 are formed in these copper foil and the insulating substrate 3. Then, electroless copper plating and electrolytic copper plating are sequentially applied to the inner surface of the through hole 7 and the surface of the copper foil, and then the inside of the through hole 7 is filled with the embedded resin 8. The copper plating is etched into a predetermined pattern using a photolithography technique, so that the upper and lower surfaces of the insulating substrate 3 and the inner surface of the through hole 7 are formed. Alternatively, copper foil having a thickness of about 3 to 18 μm is stuck on the entire upper and lower surfaces of the sheet for the insulating substrate 3 as described above, and through holes 7 are drilled in the copper foil and the insulating substrate 3. Thereafter, the copper foil is once peeled off, and then an electroless copper plating and an electrolytic copper plating are deposited on the inner surface of the through hole 7 and the upper and lower surfaces of the insulating substrate 3 in a predetermined pattern by a semi-additive method. 3 and the inner surface of the through hole 7. In this case, the fine wiring conductor 2 can be formed by a semi-additive method.

  The embedding resin 8 is for making it possible to form the insulating resin layer 4 for buildup directly above and below the through-hole 7 by closing the through-hole 7, and an uncured paste-like thermosetting resin is used. The through-holes 7 subjected to electroless copper plating and electrolytic copper plating are filled by screen printing, thermally cured, and then the upper and lower surfaces thereof are polished substantially flatly. Alternatively, after forming the wiring conductor 2 having a predetermined pattern on the inner surface of the through hole 7 and the upper and lower surfaces of the insulating substrate 3, a part of the resin for the insulating resin layer 4 is formed when the insulating resin layer 4 is formed on the insulating substrate 3. Is made to flow into the through hole 7.

  The insulating resin layers 4 for buildup laminated on the upper and lower surfaces of the insulating substrate 3 each have a thickness of about 20 to 60 μm. Similarly to the insulating substrate 3, electrical insulation in which a glass cloth is impregnated with a thermosetting resin. It consists of an electrically insulating material in which an inorganic insulating filler is filled in a material or a thermosetting resin such as an epoxy resin. The thermosetting resin constituting the insulating resin layer 4 is also made of 50% of an inorganic insulating filler having a low thermal expansion coefficient such as fused silica as in the case of the thermosetting resins constituting the insulating substrate 3 and the embedded resin 8 described above. It is preferable to fill with a high density of about 70% by mass. Thereby, the thermal expansion coefficient (XY direction) of the insulating resin layer 4 can be made as low as about 8 to 17 ppm / ° C., and the wiring board 10 is caused by the difference in thermal expansion coefficient from the semiconductor integrated circuit element E1. Can be effectively prevented. The insulating resin layer 4 and the insulating substrate 3 do not necessarily have to have a low coefficient of thermal expansion (XY direction) of 8 to 17 ppm / ° C. for all layers. For example, only the insulating resin layer 4 has a thermal expansion coefficient. A low (XY direction) of about 8-17 ppm / ° C. may be used. Alternatively, only a part of the insulating resin layer 4 having a low thermal expansion coefficient (XY direction) of about 8 to 17 ppm / ° C. may be used. However, in these cases, it is preferable to arrange the layers having different thermal expansion coefficients in the wiring substrate 10 so as to be vertically symmetrical.

  Each insulating resin layer 4 is formed with a plurality of via holes 9 having a diameter of about 30 to 100 μm. The via hole 9 is formed by laser processing, photolithography processing or the like as will be described later.

  A build-up wiring conductor 5 made of electroless copper plating and electrolytic copper plating thereon is deposited on the surface of each insulating resin layer 4 and the inner surface of the via hole 9. Then, the wiring conductor 5 located in the upper layer and the wiring conductor 5 located in the lower layer are electrically connected via the wiring conductor 5 in the via hole 9 with the insulating resin layer 4 interposed therebetween, so that the high-density wiring is three-dimensional. Formed.

  Here, among the wiring conductors 5 for buildup, the wiring conductor 5 in the via hole 9 has a two-layer structure of a first metal plating layer and a second metal plating layer. Specifically, as shown in FIG. 3, the wiring conductor 5 in the via hole 9 is deposited on the lower wiring conductor 2 (5) in the via hole 9 so as to fill the lower portion of the via hole 9. From the first copper plating layer 5A and the second copper plating layer 5B formed so as to fill the upper portion of the via hole 9 from the top of the first copper plating layer 5A to the surface of the insulating resin layer 4 Become. Thereby, for example, even when the aspect ratio of the via hole 9 is large or the diameter of the via hole 9 is large, the lower portion of the via hole 9 is covered with the first copper plating layer 5A and the second copper plating layer 5B thereon. The upper part of the via hole 9 can be filled well. Therefore, a large depression is not formed in the wiring conductor 5 on the via hole 9, and even when the upper via hole 9 is provided on the lower via hole 9, the wiring conductors 5 are arranged between the upper and lower via holes 9. Are electrically connected with high reliability. When the upper via hole 9 is provided on the lower via hole 9, the wiring of the wiring conductor 5 is compared with the case where the lower via hole 9 and the upper via hole 9 are shifted from each other and the upper and lower wiring conductors 5 are connected to each other. The density can be higher.

  In order to confirm whether or not the wiring conductor 5 in the via hole 9 is composed of the first copper plating layer 5A and the second copper plating layer 5B, for example, the cross section of the via hole 9 is scanned with a scanning electron. It can confirm by observing using a microscope (SEM).

  Each of the first copper plating layer 5A and the second copper plating layer 5B preferably comprises an electroless copper plating layer and an electrolytic copper plating layer deposited thereon. With such a configuration, the via hole 9 can be efficiently filled in a short time.

  A part of the build-up wiring conductor 5 deposited on the outermost insulating resin layer 4 on the upper surface side of the wiring substrate 10 is connected to the electrode of the semiconductor integrated circuit element E1 via a conductive bump B1 such as solder. First part 5a to be electrically connected is formed, and another part is electrically connected to the electrode terminal of semiconductor element mounting substrate E2 by solder ball connection via solder ball B2. Two connecting portions 5b are formed. Further, a part of the lower surface of the wiring board 10 deposited on the outermost insulating resin layer 4 is electrically connected to the wiring conductor of the external electric circuit board via the solder balls B3. A third connection portion 5c is formed.

  Such a build-up wiring conductor 5 is formed by a method unique to the present invention using a semi-additive method described later. In the semi-additive method, for example, a base metal layer for electrolytic plating is formed on the surface of the build-up insulating resin layer 4 in which the via holes 9 are formed by electroless copper plating, and openings corresponding to the wiring conductors 5 are formed thereon. After forming a wiring resist 5 by performing electrolytic copper plating on the base metal layer exposed from the opening using the base metal layer as an electrode for power feeding, and then peeling off the plating resist This is a method in which each wiring conductor 5 is electrically independent by etching away the exposed base metal layer.

  Furthermore, a solder resist layer 6 is deposited on the wiring conductor 5 and on the outermost insulating resin layer 4 other than the portion where the wiring conductor 5 is formed. The solder resist layer 6 is a protective film for protecting the outermost wiring conductor 5 from heat and the external environment. The solder resist layer 6 on the upper surface side includes the upper surface of the first connection portion 5a and the second connection portion 5b. It is applied so that the upper surface is exposed. Further, the solder resist layer 6 on the lower surface side is applied so as to expose the third connection portion 5c for external connection.

  The solder resist layer 6 is preferably a thermosetting resin made of an insulating material in which an inorganic powder filler such as fused silica or talc is dispersed in an epoxy resin or the like in an amount of about 30 to 70% by mass. On the outermost insulating resin layer 4 on which the wiring conductor 5 having the first wiring connection portion 5a and the second connection portion 5b is formed with the photosensitive thermosetting resin paste or film to be the solder resist 6 After being laminated, the first connection portion 5a and the second connection portion 5b or the third connection portion 5c may be exposed, developed and cured so as to have an opening for exposing.

  The upper surface of the first connection portion 5a and the upper surface of the second connection portion 5b exposed from the solder resist layer 6 prevent the first connection portion 5a and the second connection portion 5b from being oxidatively corroded, and conductive bumps. In order to improve the connection with B1 and solder ball B2, nickel plating and gold plating may be sequentially applied by an electroless plating method or an electrolytic plating method, or a solder layer may be attached. .

  Next, regarding a method of forming the buildup wiring conductor 5 by the semi-additive method, the first buildup insulating layer 4 and the first layer are formed on the core insulating substrate 3 and the core wiring conductor 2. An example of forming the buildup wiring conductor 5 will be described in detail with reference to the drawings.

  4 to 7 are schematic cross-sectional views of the relevant part for explaining the process of forming the build-up wiring conductor according to the present embodiment. Among these drawings, FIGS. 4A to 4C show a process of laminating an insulating resin layer for build-up having a copper foil deposited on the surface of the core insulating substrate and the core wiring conductor. FIGS. 5D to 5F are views showing a process of forming a via hole in the laminated insulating resin layer with copper foil and depositing a first copper plating layer in the via hole. 6 (g) to (i) and FIGS. 7 (j) to (l), the first copper plating layer and the copper foil are etched to form the first copper plating layer on the core wiring conductor. The figure which shows the process of forming the wiring conductor for buildup which consists of a 2nd copper plating layer by a semi-additive method, after removing copper foil of the insulating resin layer for buildup completely, leaving a part remaining is there.

[Step (a)]
First, as shown in FIG. 4A, a build-up insulating resin layer 4 having a copper foil 11 deposited on the surface thereof is laminated on the core insulating substrate 3 and the core wiring conductor 2. As the insulating resin layer 4, for example, an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin, a bismaleimide triazine resin, or an allyl-modified polyphenylene ether resin is preferable. It is preferable that about 50 to 70% by mass of an inorganic insulator filler having a low thermal expansion coefficient such as fused silica is filled therein and the thermal expansion coefficient (XY direction) is about 8 to 17 ppm / ° C. In addition, this invention is not limited to this, The electric insulation material which does not contain a glass cloth and consists of a thermosetting resin and an inorganic insulating filler may be sufficient. The thickness of the insulating resin layer 4 is preferably about 20 to 50 μm.

  The copper foil 11 is preferably an electrolytic copper foil having minute irregularities on the insulating resin layer 4 side. The electrolytic copper foil has a mat surface that is a rough surface having minute irregularities and a shiny surface that is a smooth surface in the manufacturing process, and the mat surface side is bonded to the insulating resin layer 4 side. It is preferable. Since the copper foil 11 has minute irregularities on the insulating resin layer 4 side, minute irregularities corresponding to the irregularities of the copper foil 11 are also formed on the surface of the insulating resin layer 4 on the copper foil 11 side. The thickness of the copper foil 11 is preferably about 3 to 18 μm.

  In order to laminate the insulating resin layer 4 for buildup having the copper foil 11 deposited on the surface thereof on the core insulating substrate 3 and the core wiring conductor 2, the copper foil 11 is deposited in advance. The insulating resin layer 4 in a semi-cured state is stacked on the insulating substrate 3 on which the core wiring conductor 2 is formed and pressed while being heated, so that the insulating resin layer 4 is completely thermoset.

[Step (b)]
Next, as shown in FIG. 4B, the copper foil 11 deposited on the surface of the insulating resin layer 4 is mechanically polished or chemically etched so that the thickness of the copper foil 11 is about 2 to 8 μm. make it thin. Thereby, it becomes easy to form an opening for forming a via hole formed in the copper foil 11 with an accurate shape and size in a process shown in FIG. Note that the step of reducing the thickness of the copper foil 11 to about 2 to 8 μm is not always necessary, and a thin copper foil 11 having a thickness of 2 to 8 μm may be deposited from the beginning.

  Next, as shown in FIG. 4C, an opening 11 a for forming a via hole is formed in the copper foil 11. The opening 11a may be formed using a well-known photolithography technique. At this time, since the thickness of the copper foil 11 is as thin as 2 to 8 μm, the opening 11a having an accurate shape and size can be easily formed by a photolithography technique. The opening 11a is not necessarily formed, and the opening 11a may not be provided.

  Next, as shown in FIG. 5D, via holes 9 are formed in the insulating resin layer 4 exposed in the openings 11a formed in the copper foil 11 by laser processing, photolithography processing, or the like. At this time, the formation of the via hole 9 in the insulating resin layer 4 is facilitated by providing the opening 11 a in the copper foil 11. The via hole 9 may be formed in the insulating resin layer 4 together with the copper foil 11 in a state where the opening 11 a is not provided in the copper foil 11.

  After forming the via hole 9 in the insulating resin layer 4, it is preferable to subject the inside of the via hole 9 to desmear treatment using, for example, an aqueous manganese peroxide solution. Undesirable resin residues adhering to the via holes 9 can be removed by the desmear process. In this case, since the surface of the insulating resin layer 4 is covered with the copper foil 11, the surface of the insulating resin layer 4 is not damaged by the desmear process. Therefore, the minute unevenness formed on the surface of the insulating resin layer 4 is maintained as it is.

[Step (c)]
Next, as shown in FIG. 5E, the first electroless copper plating layer 5A1 is well known from the surface of the core wiring conductor 2 exposed in the via hole 9 to the inner wall of the via hole 9 and the surface of the copper foil 11. Then, the first electroless copper plating layer 5A1 is coated on the surface of the first electroless copper plating layer 5A1, as shown in FIG. 5 (f). The total thickness T1 of the first electroless copper plating layer 5A1 and the first electrolytic copper plating layer 5A2 positioned on the wiring conductor 2 for the core is placed on the copper foil 11 and on the copper foil 11A. The first electroless copper plating layer 5A1 and the first electrolytic copper plating layer 5A2 are deposited so as to be thicker than the total thickness T2, that is, satisfying the relationship of T1> T2. In order to deposit the first electrolytic copper plating layer 5A2 having such a thickness, for example, a commercially available electrolytic copper plating solution for filled via plating may be used.

[Step (d)]
Next, as shown in FIG. 6 (g), the first electrolytic copper plating layer 5A2, the first electroless copper plating layer 5A1 and the copper foil 11 are etched with a well-known copper etching solution, so that the core The metal foil 11 is completely removed while leaving a part of the first electroless copper plating layer 5A1 and the first electrolytic copper plating 5A2 on the wiring conductor 2. At this time, as described above, the total thickness T1 of the first electroless copper plating layer 5A1 and the first electrolytic copper plating layer 5A2 located on the wiring conductor 2 is the copper foil 11 and the first thickness located thereon. Since it is formed so as to be thicker than the total thickness T2 of the one electroless copper plating layer 5A1 and the first electrolytic copper plating layer 5A2, the first electrolytic copper plating layer 5A2, the first electroless copper When the plating layer 5A1 and the copper foil 11 are etched substantially evenly, the metal foil 11 is completely left on the wiring conductor 2 while leaving a part of the first electroless copper plating layer 5A1 and the first electrolytic copper plating 5A2. Can be removed. As a result, a first copper plating layer 5A composed of the first electroless copper plating layer 5A1 and the first electrolytic copper plating layer 5A2 is formed in the via hole 9 so as to fill the lower portion of the via hole 9. At this time, since the first copper plating layer 5A remains on the core wiring conductor 2, the wiring conductor 2 is not likely to be excessively etched.

  Here, when the metal foil 11 is removed, the first electroless copper plating layer 5A1 and part of the first electrolytic copper plating 5A2 are reliably left on the wiring conductor 2 exposed in the via hole 9. Therefore, the ratio of T1 and T2 (T1 / T2) is 1.1 or more, preferably 1.1 to 1.7. The thickness of the first copper plating layer 5A composed of the first electroless copper plating layer 5A1 and the first electrolytic copper plating 5A2 remaining on the wiring conductor 2 is preferably 10 to 20 μm. Thereby, the 2nd copper plating layer 5B which consists of 2nd electroless copper plating layer 5B1 and 2nd electrolytic copper plating layer 5B2 demonstrated below can be reliably adhere | attached and formed in a predetermined position.

[Step (e)]
Next, as shown in FIG. 6 (h), the second electroless copper plating layer 5 </ b> B <b> 1 is well known on the surface of the first copper plating layer 5 </ b> A filled in the via hole 9 and the exposed surface of the insulating resin layer 4. The second electroless copper plating layer deposited on the insulating resin 4 as shown in FIG. 6 (i) after being deposited to a thickness of 0.3 to 1.0 μm by the electroless copper plating method. A plating resist layer 12 is formed on 5B1.

  Next, as shown in FIG. 7 (j), a second electrolytic copper plating layer 5B2 is formed on the second electroless copper plating layer 5B1 exposed from the plating resist layer 12 by a known electrolytic copper plating method. After depositing to a thickness of 20 μm, the plating resist layer 12 is peeled off as shown in FIG. Then, as shown in FIG. 7 (l), the second electroless copper plating layer 5B1 and the second electrolysis are removed until the second electroless copper plating layer 5B1 exposed from the second electrolytic copper plating layer 5B2 disappears. By etching the copper plating layer 5B2 with a well-known copper etchant, the first copper plating layer 5A deposited on the lower wiring conductor 2 in the via hole 9 so as to fill the lower portion of the via hole 9 and A wiring conductor 5 is formed comprising the second copper plating layer 5B formed so as to fill the upper portion of the via hole 9 from the top of the first copper plating layer 5A to the surface of the insulating resin layer 4. . When the wiring conductor for buildup is formed in this way, a large recess is not formed in the wiring conductor on the via hole, and even when the upper via hole is provided on the lower via hole, High-density wiring with excellent electrical connection reliability between the wiring conductors between the via holes can be obtained, and a thin wiring board with less warpage and deformation can be obtained.

  For example, the wiring substrate 10 described above is formed by electrically connecting the electrode terminal of the semiconductor integrated circuit element E1 and the first connection portion 5a via the conductive bump B1, and then connecting the semiconductor integrated circuit element E1 and the wiring substrate 10 to each other. A gap between them is filled with a filling resin U <b> 1 called an underfill made of a thermosetting resin such as an epoxy resin, and the semiconductor integrated circuit element E <b> 1 is mounted on the wiring substrate 10. Furthermore, the semiconductor element mounting board E2 is mounted on the wiring board 10 by electrically connecting the electrode terminal of the semiconductor element mounting board E2 and the second connection portion 5b via the solder ball B2 thereon, thereby A plurality of electronic components are mounted on the wiring board 10 with high density. After mounting, each thermosetting resin constituting the insulating substrate 3, the embedded resin 8, and the insulating resin layer 4 is filled with an inorganic insulating filler having a low thermal expansion coefficient at a high density in a predetermined ratio, so that the wiring substrate 10 is It is possible to effectively prevent warping due to a difference in thermal expansion coefficient from that of the semiconductor integrated circuit element E1.

It is a schematic sectional drawing which shows the wiring board concerning one Embodiment of this invention. FIG. 2 is a plan view showing the wiring board of FIG. It is a partial expanded sectional view which shows the wiring conductor vicinity in the via hole concerning one embodiment of this invention. (A)-(c) is a principal part schematic sectional drawing explaining the process of forming the wiring conductor for buildup concerning one embodiment of this invention by a semi-additive method. (D)-(f) is principal part schematic sectional drawing explaining the process of forming the wiring conductor for buildup concerning one embodiment of this invention by a semi-additive method. (G)-(i) is a principal part schematic sectional drawing explaining the process of forming the wiring conductor for buildup concerning one embodiment of this invention by a semi-additive method. (J)-(l) is a principal part schematic sectional drawing explaining the process of forming the wiring conductor for buildup concerning one embodiment of this invention by a semi-additive method. It is a schematic sectional drawing which shows an example of the conventional wiring board. It is a top view which shows the wiring board of FIG.

Explanation of symbols

2 Wiring conductor for core 3 Insulating substrate for core 4 Insulating resin layer for buildup 5 Wiring conductor for buildup 5A First copper plating layer 5A1 First electroless copper plating layer 5A2 First electrolytic copper plating Layer 5B Second copper plating layer 5B1 Second electroless copper plating layer 5B2 Second electrolytic copper plating layer 5a First connection portion 5b Second connection portion 5c Third connection portion 6 Solder resist layer 7 Through hole 8 Embedded resin 9 Via hole 10 Wiring board 11 Copper foil 11a Opening 12 Plating resist layer

Claims (10)

A lower insulating resin layer;
A lower wiring conductor formed on the surface of the lower insulating resin layer;
An upper insulating resin layer laminated on the lower insulating resin layer and the lower wiring conductor, and having a via hole reaching the lower wiring conductor;
An upper wiring conductor comprising a metal plating layer deposited on the surface of the upper insulating resin layer from above the lower wiring conductor in the via hole, and a wiring board comprising:
The metal plating layer is
A first metal plating layer deposited on the lower wiring conductor in the via hole so as to fill a lower portion of the via hole;
A wiring board comprising: a second metal plating layer deposited from the first metal plating layer to a surface of the upper insulating resin layer.   The wiring board according to claim 1, wherein the first metal plating layer includes an electroless metal plating layer and an electrolytic metal plating layer deposited on the electroless metal plating layer.   The wiring board according to claim 1 or 2, wherein the second metal plating layer includes an electroless metal plating layer and an electrolytic metal plating layer deposited on the electroless metal plating layer. A method of manufacturing a wiring board including a step of alternately laminating insulating resin layers and wiring conductors, the method including the following steps (a) to (e) in order:
(A) A step of laminating an upper insulating resin layer having a metal foil on the surface thereof on a lower insulating resin layer having a lower wiring conductor on the surface (b) A part of the metal foil facing the lower wiring conductor (C) forming a via hole reaching the lower wiring conductor in the upper insulating resin layer in the removal portion (c) the metal foil, the upper insulating resin layer, and the lower wiring conductor exposed in the via hole On the surface, the first metal plating layer, the thickness of the first metal plating layer located on the lower wiring conductor is T1, the total thickness of the metal foil and the first metal plating layer located on the metal foil (2) The lower wiring conductor is formed by etching the first metal plating layer and the metal foil so that T1 and T2 satisfy the relationship of T1> T2. Up (E) removing the metal foil while leaving a part of the first metal plating layer remaining (e) the lower surface through the via hole on the exposed surface of the first metal plating layer and the upper insulating resin layer A process of depositing and forming an upper wiring conductor composed of a second metal plating layer electrically connected to the wiring conductor   The method for manufacturing a wiring board according to claim 4, comprising a step of reducing the thickness of the metal foil by chemical etching or physical polishing after the step (a) and before the step (b).   The method for manufacturing a wiring board according to claim 4 or 5, wherein, in the step (b), a part of the metal foil facing the lower wiring conductor is removed by etching.   The method for manufacturing a wiring board according to claim 4 or 5, wherein in the step (b), a part of the metal foil facing the lower wiring conductor is removed by laser processing.   The method for manufacturing a wiring board according to claim 4, wherein a desmear treatment in the via hole is performed after the step (b) and before the step (c).   The wiring board according to any one of claims 4 to 8, wherein the first metal plating layer includes an electroless metal plating layer and an electrolytic metal plating layer formed on the electroless metal plating layer. Production method.   The wiring board according to any one of claims 4 to 9, wherein the second metal plating layer includes an electroless metal plating layer and an electrolytic metal plating layer deposited on the electroless metal plating layer. Production method.

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