JP2008124124A - Core board manufacturing method, and wiring board manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a core board manufacturing method and a wiring board manufacturing method which suppress the unevenness of the thickness of a conductive layer on the surface of a core board and reduce the conductive layer into a thin film to enable the formation of microwiring. <P>SOLUTION: First conductive layers 59 and 61 are formed on the surface of a copper-coating board 57, and a through-hole conductive layer 23 is formed on the inner peripheral surface of a through-hole 21. A through-hole 25 inside the through-hole conductive layer 23 is filled with a resin hole-filling material 27. A projecting portion of the resin hole-filling material 27 and the surface side of the first conductive layers 59 and 61 are eliminated by first polishing. The surface side of first laminated conductive layers 63 and 65 is also eliminated by etching. The end of the resin hole-filling material 27 that projects as a result of etching is then eliminated by second polishing (buff polishing). Subsequently, the surface of the first laminated conductive layers 63 and 65 and that of the resin hole-filling material 27 are covered with second conductive layers 75 and 77. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a core substrate manufacturing method and a wiring substrate manufacturing method.

Conventionally, a multilayer wiring board in which a plurality of wiring boards are stacked is used as a printed board (wiring board) used for an MPU package.
For this multilayer wiring board, a wiring board (core board) serving as a single core is used, and wiring boards are formed in multiple layers on this core board (see cited documents 1 and 2).

The core substrate described above is manufactured, for example, by the following procedures (1) to (8).
(1) First, as shown in FIG. 5A, uniform etching is performed on a substrate (CCL) 105 in which the surface of a resinous plate-like core 101 is coated with a copper foil (Cu layer 103) to obtain a Cu layer. The film thickness of 103 is processed to 5 μm.

(2) Next, as shown in FIG. 5B, the etched substrate 105 is drilled to form a through hole 107.
(3) Next, as shown in FIG. 5C, a Cu plating layer 109 is formed on the surface of the substrate 105 and the inner peripheral surface of the through hole 107 by plating (electroless Cu plating + electrolytic Cu plating). The through hole 107 plated on the inner peripheral surface is a PTH (Plated Through Hole).

(4) Next, the surface of the Cu plating layer 109 in the through hole 107 is roughened by etching.
(5) Next, as shown in FIG. 5D, after filling the through hole 107 with the resin 111 by hole filling printing, the resin 111 is cured to form a via 113.

(6) Next, as shown in FIG. 5E, the substrate surface is polished to remove excess resin 111 at the end of the via 113.
(7) Next, as shown in FIG. 5F, lid plating (electroless Cu plating + electrolytic Cu plating) is performed so as to cover the substrate surface including the surface of the via 113.

(8) Next, after forming a resist with a dry film, subtractive etching is performed to form a wiring pattern.
JP 2001-144435 A JP 2003-142824 A

However, when fine wiring is formed on the core substrate by the subtractive method, there is a problem in that etching residue occurs with the copper thickness of the conventional substrate surface.
As a countermeasure, it is conceivable to reduce the copper thickness, but in this case, another problem such as the following (1) to (3) occurs, which is not always sufficient.

(1) In CCL, the copper foil on the surface is originally about 5 μm, and usually cannot be made thinner than this.
(2) If the PTH plating is thinner than this, there is a risk of barrel cracking, so it cannot be made thinner.

(3) If the cover plating is made too thin, there is a problem in connection reliability with vias (build-up) formed on the cover plating.
That is, there is a problem that the thickness of the original copper foil or plating (to be formed later) cannot be made sufficiently thin so as not to cause etching residue.

  Therefore, I would like to reduce the thickness of the Cu layer on the substrate surface in the process before lid plating, that is, the polishing process after filling the hole, but the thinning in the conventional polishing process has a large variation in polishing. On the contrary, the problem of underexposure due to excessive polishing may occur, which is not preferable.

  The present invention has been made to solve the above-described problems, and its purpose is to form a fine wiring by reducing the thickness of the conductive layer on the surface of the core substrate and reducing the thickness of the conductive layer. Another object of the present invention is to provide a core substrate manufacturing method and a wiring substrate manufacturing method using the core substrate.

  (1) The invention of claim 1 (core substrate manufacturing method) includes a step of forming a surface conductive layer on the surface of the substrate body and forming a through-hole conductive layer on the inner peripheral surface of the through-hole; A step of filling the through hole provided with a layer with a filler, a step of removing the protruding portion on the surface side of the filler and the surface side of the surface conductive layer by first polishing, and a surface side of the surface conductive layer. The step of further removing by etching, the step of removing the end of the filler protruding to the surface by etching, the second polishing, and the surface of the surface conductive layer and the surface of the filler are covered with the coated conductive layer by plating And a process.

  In the present invention, after the first polishing, etching is performed to thin the surface conductive layer, the filler protruding by the etching is removed by the second polishing, and then the substrate surface is covered with the covering conductive layer by plating. In comparison, the surface conductive layer can be uniformly thin without variation.

  In other words, since the surface conductive layer can be thinned while suppressing variations in the thickness of the surface conductive layer, there is no etching residue when the wiring is formed by etching. There is a remarkable effect that can be formed.

  As will be described later, when a conductive layer (base conductive layer) is provided in advance on the surface of the substrate body, “to form a surface conductive layer” means that the base conductive layer is included in the lower layer and integrated. Forming a conductive layer.

(2) In the invention of claim 2, the substrate body is provided with an insulating plate-like core or a base conductive layer on the surface of the insulating plate-like core.
The present invention exemplifies a substrate body. Of these, the required thickness of the surface conductive layer can be easily ensured by employing a substrate body in which a plate-like core is covered with a base conductive layer.

  In the case where a base conductive layer is provided on the surface of the plate-shaped core, the surface conductive layer includes a base conductive layer and a conductive layer (for example, a first conductive layer formed by plating) formed on the surface. However, when there is no base conductive layer, the first conductive layer formed by plating, for example, becomes the surface conductive layer as it is.

(3) In invention of Claim 3, buffing is employ | adopted as 2nd grinding | polishing.
This buffing is polishing with a cloth, whereby only the filler can be easily removed without scraping the surface of the surface conductive layer almost (or not at all).

(4) In invention of Claim 4, the thickness of the whole conductive layer on a board | substrate body shall be 5 micrometers or more and 15 micrometers or less by an etching.
With this thickness, the underlying layer is not exposed, and the thickness of the conductive layer can be sufficiently reduced even when a coated conductive layer is formed later.

The entire conductive layer on the substrate body indicates the entire conductive layer formed on the plate-like core regardless of the presence or absence of the base conductive layer.
(5) In invention of Claim 5, the thickness of the whole conductive layer on the board | substrate body after forming a covering conductive layer shall be 15 micrometers or more and 20 micrometers or less.

  In the present invention, since the thickness of the conductive layer can be sufficiently reduced, even when wiring is formed later by etching, it is difficult for etching residue to occur, so that fine wiring can be easily formed.

The entire conductive layer on the substrate body indicates the entire conductive layer formed on the plate-like core regardless of the presence or absence of the base conductive layer.
(6) In the invention of claim 6, a build-up layer is formed on the surface of the core substrate manufactured by the above-described core substrate manufacturing method to manufacture a multilayer wiring substrate.

  Thereby, a wiring board provided with fine wiring can be easily manufactured.

Next, the best mode (embodiment) of the present invention will be described based on the drawings.
[Embodiment]
a) First, the wiring board manufactured by the manufacturing method of the wiring board of this embodiment will be described. FIG. 1 schematically shows a cross-sectional structure of the wiring board.

As shown in FIG. 1, the wiring substrate 1 is formed by laminating a plurality of buildup layers 5 to 11 on both upper and lower surfaces of a core substrate 3.
The core substrate 3 serves as a core for securing the mechanical strength of the wiring substrate 1, and mainly includes a plate-like core 13 having insulating properties and core conductor layers 15 and 17 formed on both surfaces thereof. And vias 19 that electrically connect the core conductor layers 15 and 17 on both surfaces.

  Among these, the plate-like core 13 is a plate material composed of a heat-resistant resin plate (for example, a bismaleimide-triazine resin plate), a fiber reinforced resin plate (for example, a glass fiber reinforced epoxy resin), or the like.

  The core conductor layers 15 and 17 are wiring metal layers made of copper formed on the upper and lower surfaces of the plate-like core 13 as surface conductor patterns covering most of the surfaces, and are used as a power supply layer or a ground layer. It is what

  In the via 19, a through-hole conductive layer 23 made of copper is formed on the inner peripheral surface of the through-hole 21 formed in the plate-like core 13, and a resin such as an epoxy resin is formed in the through-hole 25 inside the through-hole conductive layer 23. The hole filling material (filling material) 27 is filled. The core conductor layers 15 and 17 on both surfaces of the plate core 13 are electrically connected by the through-hole conductor layer 23.

  The build-up layers 5 to 11 are resin insulating layers made of a thermosetting resin composition, and the first build-up layers 5 and 7 are the upper layers of the core conductor layers 15 and 17 (that is, the plate-like core 13). On both surfaces).

  On the surfaces of the first build-up layers 5 and 7, first conductor layers 29 and 31 which are wiring metal layers are formed by Cu plating, respectively. The core conductor layers 15 and 17 and the first conductor layers 29 and 31 are interconnected by vias 33 and 35, respectively.

  Similarly, second buildup layers 9 and 11 are formed on the upper layers of the first conductor layers 29 and 31 (that is, both surfaces of the first buildup layers 5 and 7), respectively. 11 are formed with second conductor layers 41 and 43, respectively. The second conductor layers 41 and 43 have metal terminal pads 37 and 39. The first conductor layers 29 and 31 and the second conductor layers 41 and 43 are connected to each other through vias 45 and 47, respectively.

  Further, of the metal terminal pads 37 and 39, solder bumps 49 for flip-chip connection of integrated circuit chips or the like are formed on the metal terminal pads 37 on the upper side (first main surface side) in FIG. .

  That is, the metal terminal pads 37 are arranged in a lattice pattern at the central portion of the first main surface of the wiring board 1, and chip mounting portions are formed together with the solder bumps 49 formed thereon. Note that the solder bumps 49 can be composed of solder that does not substantially contain Pb, such as Sn—Ag, Sn—Cu, Sn—Ag—Cu, Sn—Sb.

  On the other hand, the metal terminal pad 39 on the lower side (second main surface side) of FIG. , BGA pad). The metal terminal pads 39 on the second main surface side are also arranged in a grid pattern.

  Solder resist layers 51 and 52 made of a photosensitive or thermosetting resin composition are formed on the second conductor layers 41 and 43 (that is, the second buildup layers 9 and 11), respectively. The solder resist layers 51 and 52 are formed so that the solder bumps 49 and the land portions of the metal terminal pads 39 are exposed.

b) Next, a method for manufacturing a wiring board (including a method for manufacturing a core substrate) of this embodiment will be described. 2 and 3 are explanatory views showing a manufacturing procedure of the wiring board.
The wiring board 1 can be manufactured by sequentially forming buildup layers 5 to 11 and the like on both main surfaces of the plate-like core 13 using a known buildup method or the like. This will be specifically described below.

  First, as shown in FIG. 2A, in order to manufacture the core substrate 3, Cu foils (base conductive layers) 53 and 55 are coated on both sides of the plate-like core 13 such as a fiber reinforced resin plate. A substrate body (copper-coated substrate: CCL) 57 is prepared.

The plate-like core 13 has a thickness of 600 μm (possible in the range of 100 to 2000 μm), and the base conductive layers 53 and 55 have a thickness of 12 μm (or 18 μm).
Here, the copper-coated substrate 57 is used as the substrate body, but a substrate body (that is, only the plate-like core 13) that does not include the base conductive layers 53 and 55 can also be employed.

  Next, as shown in FIG. 2 (b), the surface of the base conductive layers 53 and 55 using a hydrogen peroxide / sulfuric acid based chemical polishing liquid (clean etch SE-07: manufactured by Mitsubishi Gas Chemical Co., Ltd.). Is etched to a thickness of 5 μm.

  Next, as shown in FIG. 2 (c), a diameter of about 250 μm (possible in the range of 50 to 550 μm) penetrating the etched copper-coated substrate 57 in the thickness direction of the substrate by a method such as drilling. A plurality of through holes 21 are perforated.

  Next, as shown in FIG. 2D, the electroless plating of Cu is performed on the inner peripheral surface of the through-hole 21 and the upper and lower surfaces of the copper-coated substrate 57, and the electrolytic plating of Cu is performed thereon. As a result, the through-hole conductive layer 23 and the first conductive layers 59 and 61 are formed. The base conductive layers 53 and 55 after etching and the first conductive layers 59 and 61 constitute first laminated conductive layers (surface conductive layers) 63 and 65.

  Here, since the formation rate of the Cu film by plating is different between the inside of the through hole 21 and the surface of the copper-coated substrate 57, the first conductive layer 59 is obtained from the thickness t1 of the through hole conductive layer 23 as shown in FIG. , 61 is increased in thickness t2. The ratio of plating thickness (slowing power) t1 / t2 is normally about 0.9.

  In addition, since the thickness t1 of the through-hole conductive layer 23 is considered to be 15 μm or more from the viewpoint of preventing barrel cracks, the thickness t1 = 16 μm of the through-hole conductive layer 23 and the first conductive layers 59 and 61 Thickness t2 = 23 μm. In addition, since the thickness t3 of the base conductive layers 53 and 55 after etching is 5 μm, the thickness t4 of the first laminated conductive layers 63 and 65 is 28 μm.

  Next, as shown in FIG. 2E, with the plated copper-coated substrate 57 kept horizontal, a printing mask 67 is superimposed on one main surface (the upper side in this embodiment). . The printing mask 67 is provided with an opening 69 corresponding to the formation position of the through hole 21.

  Then, a resin paste 73 (made of epoxy resin or the like) is placed on the surface of the printing mask 67, and a printing instrument such as a squeegee 71 is moved on the printing mask 67, so that the resin paste 73 passes through the opening 69. Then, it is press-fitted into the through hole 21 (specifically, in the through hole 25 inside the through hole conductive layer 23) at a time.

  As a result, the resin paste 57 is printed on the surface of the copper-coated substrate 57 by being raised by the thickness of the printing mask 67 on the surface side of the through hole 25, and outward from the periphery of the through hole 25. It is also raised and printed at the overhanging position.

Next, as shown in FIG. 3A, the printing mask 67 is separated from the surface of the copper-coated substrate 57 filled with the resin paste 73, and the filled resin paste 73 is dried and cured.
As a result, the resin paste 73 is cured (resin filling material 27) so as to rise on the surface of the copper-coated substrate 57.

  Next, as shown in FIG. 3B, the surface of the copper-coated substrate 57 is polished (first polishing) to flatten the surface. That is, the end portion of the resin filling material 27 raised on the surface of the copper-coated substrate 57 is removed, and polishing is performed so that the surface of the resin filling material 27 in the through hole 25 and the surface of the copper-coated substrate 57 are flush with each other. Process.

At this time, since the entire surfaces of the first conductive layers 59 and 61 (and thus the entire surfaces of the first stacked conductive layers 63 and 65) are also polished, the thickness t4 of the first conductor stacked portions 63 and 65 is as thin as 23 μm.
In addition, this 1st grinding | polishing is specifically performed using a belt sander machine.

  Next, as shown in FIG. 3 (c), the surface of the polished copper-coated substrate 57 is entirely treated with a hydrogen peroxide / sulfuric acid based chemical polishing solution in the same manner as in the step shown in FIG. 2 (b). Etching is performed to further reduce the thickness t4 of the first stacked conductive layers 63 and 65 to 13 μm. The thickness t4 of the first laminated conductive layers 63 and 65 is preferably in the range of 10 to 15 μm.

  By this etching, the first laminated conductive layers 63 and 65 around the resin filling material 27 become thin, so that the upper and lower ends of the resin filling material 27 protrude from the surface of the copper-coated substrate 57, respectively.

  Next, as shown in FIG. 3 (d), the upper and lower ends of the resin hole filling material 27 protruding from the surface of the copper-coated substrate 57 by buffing (second polishing) the surface of the etched copper-coated substrate 57. The surface of the resin hole filling material 27 and the surface of the copper-coated substrate 57 are processed so as to be flush with each other.

  In addition, since this buffing is specifically performed by roll polishing using a flap brush or the like, the thickness of the first laminated conductive layers 63 and 65 is slightly polished to 10 μm, but hardly changes.

  Next, as shown in FIG. 3 (e), the batter-polished copper-coated substrate 57 is covered with a lid so as to cover the entire substrate surface including the surface of the resin hole filling material 27 (and hence the surface of the via 19). I do.

In this lid plating, electroless Cu plating is performed after electroless Cu plating to form second conductive layers (covering conductive layers) 75 and 77 having a thickness of 10 μm.
Thus, the substrate surface is covered with the second laminated conductive layers 79 and 81 having a thickness of 20 μm, in which the first laminated conductive layers 63 and 65 having a thickness t4 of 10 μm and the second conductive layers 75 and 77 having a thickness of 10 μm are laminated. It will be. The thickness of the second laminated conductive layers 79 and 81 is preferably in the range of 15 to 20 μm.

  Thereafter, although not shown, an etching resist layer having a predetermined pattern is formed on the second laminated conductive layers 79 and 81, and the conductor layer exposed from the resist layer is removed by etching, so that both surfaces of the plate-like core 13 are formed. Core conductor layers 15 and 17 having a predetermined pattern are formed.

  Further, as described above, the build-up layers 5 to 11 are sequentially formed on both main surfaces of the flat plate-like core 13 (that is, both main surfaces of the core substrate 3) by a known build-up method or the like. By doing so, the wiring board 1 can be manufactured.

c) Effects of this embodiment In this embodiment, the core substrate 3 and the wiring substrate 1 are manufactured by the above-described manufacturing method. That is, after the first polishing, uniform etching is performed to perform the first laminated conductive layer. 63 and 65 are thinned, and the resin hole filling material 27 protruding by the etching is removed by second polishing (buff polishing), and then lid plating is performed, so that the second laminated conductive layers 79 and 81 (according to the above) The core conductors 15 and 17) can be made thin uniformly without variation.

  That is, since the core conductors 15 and 17 can be thinned while suppressing variations in the thickness of the core conductors 15 and 17 on the surface of the core substrate 3, the etching residue remains when the wiring is formed by etching. Therefore, there is a remarkable effect that a fine wiring can be suitably formed.

In addition, this invention is not limited to the said embodiment at all, and it cannot be overemphasized that it can implement with a various aspect in the range which does not deviate from this invention.
For example, as the above-described resin paste, any resin paste can be used as long as the through hole can be filled and filled, but in order to reduce the occurrence of thermal stress, a resin having a thermal expansion coefficient similar to that of the substrate to be filled is preferable. Moreover, a thing with little sclerosing | shrinkage shrinkage is easy to handle. For example, an epoxy resin, a polyimide resin, a BT resin, etc. are mentioned. Furthermore, these resins may be mixed with inorganic powders such as silica and alumina, or may contain metal powders such as Cu powder and Ag powder to make it possible to deposit a plating layer by electroplating, May be provided.

It is explanatory drawing which shows an example of the cross-section of a wiring board. It is explanatory drawing which shows a part of manufacturing process of a wiring board. FIG. 3 is an explanatory diagram illustrating a part of the manufacturing process of the wiring board subsequent to FIG. 2. It is explanatory drawing which shows the thickness of the conductive layer by plating etc. It is explanatory drawing which shows a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Wiring board 3 ... Core board | substrate 5, 7, 9, 11 ... Build-up layer 13 ... Plate-shaped core (plate-shaped core)
DESCRIPTION OF SYMBOLS 21 ... Through-hole 23 ... Through-hole conductive layer 27 ... Resin hole-filling material 53, 55 ... Base conductive layer 57 ... Copper covering board (board body)
59, 61 ... first conductive layer 63, 65 ... first laminated conductive layer (surface conductive layer)
75, 77 ... second conductive layer (covered conductive layer)
79, 81 ... Second laminated conductive layer

Claims (6)

Forming a surface conductive layer on the surface of the substrate body and forming a through-hole conductive layer on the inner peripheral surface of the through-hole;
Filling the through hole with the through hole conductive layer with a filler;
Removing the protruding portion on the surface side of the filler and the surface side of the surface conductive layer by first polishing;
A step of further removing the surface side of the surface conductive layer by etching;
Removing the end of the filler protruding to the surface by the etching by second polishing;
Covering the surface of the surface conductive layer and the surface of the filler with a coated conductive layer by plating;
A method for manufacturing a core substrate, comprising:   2. The method of manufacturing a core substrate according to claim 1, wherein the substrate body includes an insulating plate-shaped core or a base conductive layer on a surface of the insulating plate-shaped core.   The method for manufacturing a core substrate according to claim 1, wherein the second polishing is buff polishing.   4. The core substrate manufacturing method according to claim 1, wherein a thickness of the entire conductive layer on the substrate body is set to 5 μm to 15 μm by the etching. 5.   5. The manufacturing of a core substrate according to claim 1, wherein a thickness of the entire conductive layer on the substrate body after forming the coated conductive layer is 15 μm or more and 20 μm or less. Method.   A multilayer wiring board is manufactured by stacking a buildup layer on the surface of the core board manufactured by the core board manufacturing method according to any one of claims 1 to 5. A method for manufacturing a wiring board.

Images