JP5058929B2 - Wiring board and manufacturing method thereof - Google Patents

Wiring board and manufacturing method thereof Download PDF

Info

Publication number
JP5058929B2
JP5058929B2 JP2008251293A JP2008251293A JP5058929B2 JP 5058929 B2 JP5058929 B2 JP 5058929B2 JP 2008251293 A JP2008251293 A JP 2008251293A JP 2008251293 A JP2008251293 A JP 2008251293A JP 5058929 B2 JP5058929 B2 JP 5058929B2
Authority
JP
Japan
Prior art keywords
semiconductor element
connection pad
solder resist
wiring board
mounting portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008251293A
Other languages
Japanese (ja)
Other versions
JP2010087018A (en
Inventor
孝一 大隅
Original Assignee
京セラＳｌｃテクノロジー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京セラＳｌｃテクノロジー株式会社 filed Critical 京セラＳｌｃテクノロジー株式会社
Priority to JP2008251293A priority Critical patent/JP5058929B2/en
Priority to KR1020090087691A priority patent/KR101627574B1/en
Priority to US12/562,956 priority patent/US8319115B2/en
Priority to TW98131878A priority patent/TWI470758B/en
Publication of JP2010087018A publication Critical patent/JP2010087018A/en
Application granted granted Critical
Publication of JP5058929B2 publication Critical patent/JP5058929B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board such that electrode terminals of a semiconductor element and semiconductor element connection pads can be connected tightly and excellently through conductive bumps. <P>SOLUTION: The wiring board 10 is composed of: an insulation substrate 1 having a mounting portion 1A where the semiconductor element E1 is mounted on an upper surface; a plurality of circular semiconductor element connection pads 2A made of plating layers and deposited in a lattice form onto the mounting portion 1A of the insulation substrate 1, their upper surfaces being connected to electrodes of the semiconductor element E1 through conductive bumps B1; and a solder resist layer 3 deposited onto the insulation substrate 1, which covers the side surfaces of these pads 2A and exposes the upper surfaces of these pads 2A. The solder resist layer 3 has a concave part 2A whose bottom surface corresponds to at least all the upper surfaces of these semiconductor element connection pads 2A. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は配線基板およびその製造方法に関し、より詳細には、例えばエリアアレイ型の半導体素子をフリップチップ接続により搭載するのに好適な配線基板およびその製造方法に関する。   The present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a wiring board suitable for mounting, for example, an area array type semiconductor element by flip chip connection and a manufacturing method thereof.

従来から、半導体素子である半導体集積回路素子として、多数の電極端子を、その一方の主面の略全面に亘って格子状の並びに配設した、いわゆるエリアアレイ型の半導体集積回路素子がある。
このような半導体集積回路素子を配線基板に搭載する方法として、フリップチップ接続により接続する方法が採用されている。フリップチップ接続とは、配線基板上に設けた半導体素子接続パッドの上面を半導体集積回路素子の電極端子の配置に対応した並びに露出させ、この半導体素子接続パッドの露出する上面と前記電子部品の電極端子とを対向させ、これらの間を半田や金等からなる導電バンプを介して電気的に接続する方法である。
また、近時はこのようなフリップチップ接続により半導体素子を配線基板上に搭載し、さらにその上に別の電子部品を半田ボール接続またはワイヤボンド接続により搭載して、配線基板への半導体素子や電子部品の搭載密度を高めることが行われている。 2. Description of the Related Art Conventionally, as a semiconductor integrated circuit element that is a semiconductor element, there is a so-called area array type semiconductor integrated circuit element in which a large number of electrode terminals are arranged in a lattice pattern over substantially the entire main surface.
As a method of mounting such a semiconductor integrated circuit element on a wiring board, a method of connecting by flip chip connection is employed. In flip chip connection, the upper surface of the semiconductor element connection pad provided on the wiring board is exposed corresponding to the arrangement of the electrode terminals of the semiconductor integrated circuit element, and the exposed upper surface of the semiconductor element connection pad and the electrode of the electronic component are exposed. This is a method in which terminals are opposed to each other and electrically connected via conductive bumps made of solder, gold, or the like.
Recently, a semiconductor element is mounted on a wiring board by such flip-chip connection, and another electronic component is mounted on the wiring board by solder ball connection or wire bond connection. Increasing the mounting density of electronic components is being carried out.

図１７は、半導体素子としてのエリアアレイ型の半導体集積回路素子をフリップチップ接続により搭載し、さらにその上に別の電子部品としての半導体素子搭載基板を半田ボール接続した従来の配線基板の一例を示す概略断面図であり、図１８は、図１７の配線基板を示す平面図である。   FIG. 17 shows an example of a conventional wiring board in which an area array type semiconductor integrated circuit element as a semiconductor element is mounted by flip-chip connection, and a semiconductor element mounting board as another electronic component is further connected by solder balls. FIG. 18 is a plan view showing the wiring board of FIG.

図１７に示すように、従来の配線基板１１０は、コア用の絶縁基板１０１ａの上下面に複数のビルドアップ用の絶縁層１０１ｂが積層されて成る絶縁基体１０１の内部および表面にコア用の配線導体１０２ａおよびビルドアップ用の配線導体１０２ｂが被着されているとともに、その最表面には保護用のソルダーレジスト層１０３が被着されている。また、絶縁基体１０１の上面中央部には半導体集積回路素子Ｅ１が搭載される半導体素子搭載部１０１Ａおよび上面外周部には半導体素子搭載基板Ｅ２が搭載される電子部品搭載部１０１Ｂを有している。   As shown in FIG. 17, a conventional wiring board 110 includes a core wiring on the inside and surface of an insulating base 101 in which a plurality of build-up insulating layers 101b are laminated on the upper and lower surfaces of a core insulating board 101a. A conductor 102a and a build-up wiring conductor 102b are deposited, and a protective solder resist layer 103 is deposited on the outermost surface thereof. The insulating base 101 has a semiconductor element mounting portion 101A on which the semiconductor integrated circuit element E1 is mounted at the center of the upper surface, and an electronic component mounting portion 101B on which the semiconductor element mounting substrate E2 is mounted on the outer periphery of the upper surface. .

コア用の絶縁基板１０１ａの上面から下面にかけては複数のスルーホール１０４が形成されており、絶縁基板１０１ａの上下面およびスルーホール１０４の内面にはコア用の配線導体１０２ａが被着され、スルーホール１０４の内部には埋め込み樹脂１０５が充填されている。ビルドアップ用の絶縁層１０１ｂには、それぞれに複数のビアホール１０６が形成されており、各絶縁層１０１ｂの表面およびビアホール１０６の内面には、ビルドアップ用の配線導体１０２ｂが被着形成されている。   A plurality of through holes 104 are formed from the upper surface to the lower surface of the core insulating substrate 101a, and the core wiring conductor 102a is attached to the upper and lower surfaces of the insulating substrate 101a and the inner surface of the through hole 104. The interior of 104 is filled with an embedded resin 105. A plurality of via holes 106 are formed in each of the build-up insulating layers 101b, and a build-up wiring conductor 102b is formed on the surface of each insulating layer 101b and the inner surfaces of the via holes 106. .

この配線導体１０２ｂのうち、配線基板１１０の上面側における最外層の絶縁層１０１ｂ上に被着された一部は、半導体素子搭載部１０１Ａにおいて半導体集積回路素子Ｅ１の電極端子に導電バンプＢ１を介してフリップチップ接続により電気的に接続される円形の半導体素子接続パッド１０２Ａを形成しており、これらの半導体素子接続パッド１０２Ａは格子状の並びに複数並んで形成されている。さらに、配線導体１０２ｂのうち、配線基板１１０の上面側における最外層の絶縁層１０１ｂ上に被着された他の一部は、電子部品搭載部１０１Ｂにおいて電子部品としての半導体素子搭載基板Ｅ２の電極端子に半田ボールＢ２を介して半田ボール接続により電気的に接続される円形の電子部品接続パッド１０２Ｂを形成しており、この電子部品接続パッド１０２Ｂは複数並んで形成されている。そして、これらの半導体素子接続パッド１０２Ａおよび電子部品接続パッド１０２Ｂはその外周部がソルダーレジスト層１０３により覆われているとともに上面の中央部がソルダーレジスト層１０３から露出しており、半導体素子接続パッド１０２Ａの露出部に半導体集積回路素子Ｅ１の電極端子が半田や金等から成る導電バンプＢ１を介して電気的に接続され、電子部品接続パッド１０２Ｂの露出部に半導体素子搭載基板Ｅ２の電極端子が半田ボールＢ２を介して電気的に接続される。   A part of the wiring conductor 102b deposited on the outermost insulating layer 101b on the upper surface side of the wiring substrate 110 is connected to the electrode terminal of the semiconductor integrated circuit element E1 in the semiconductor element mounting portion 101A via the conductive bump B1. Thus, a circular semiconductor element connection pad 102A to be electrically connected by flip chip connection is formed, and a plurality of these semiconductor element connection pads 102A are formed in a lattice pattern. Furthermore, the other part of the wiring conductor 102b deposited on the outermost insulating layer 101b on the upper surface side of the wiring substrate 110 is an electrode of the semiconductor element mounting substrate E2 as an electronic component in the electronic component mounting portion 101B. A circular electronic component connection pad 102B that is electrically connected to the terminal by solder ball connection via the solder ball B2 is formed, and a plurality of the electronic component connection pads 102B are formed side by side. The semiconductor element connection pad 102A and the electronic component connection pad 102B are covered with the solder resist layer 103 at the outer periphery thereof, and the center part of the upper surface is exposed from the solder resist layer 103. The semiconductor element connection pad 102A The electrode terminal of the semiconductor integrated circuit element E1 is electrically connected to the exposed part of the semiconductor element via the conductive bump B1 made of solder, gold or the like, and the electrode terminal of the semiconductor element mounting substrate E2 is soldered to the exposed part of the electronic component connection pad 102B. Electrical connection is made via the ball B2.

さらに、配線基板１１０の下面側における最外層の絶縁層１０１ｂ上に被着された一部は、外部電気回路基板の配線導体に電気的に接続される円形の外部接続パッド１０２Ｃであり、この外部接続パッド１０２Ｃは格子状の並びに複数並んで形成されている。この外部接続パッド１０２Ｃはその外周部がソルダーレジスト層１０３により覆われているとともに、その上面中央部がソルダーレジスト層１０３から露出しており、外部接続パッド１０２Ｃの露出部に、外部電気回路基板の配線導体が半田ボールＢ３を介して電気的に接続される。   Furthermore, a part of the lower surface side of the wiring board 110 that is deposited on the outermost insulating layer 101b is a circular external connection pad 102C that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of connection pads 102C are formed in a grid and arranged side by side. The external connection pad 102C is covered with a solder resist layer 103 at the outer periphery thereof, and the central portion of the upper surface is exposed from the solder resist layer 103. The external connection pad 102C is exposed to the exposed portion of the external electric circuit board. The wiring conductor is electrically connected via the solder ball B3.

ソルダーレジスト層１０３は、最外層の配線導体１０２ｂを保護するとともに、半導体素子接続パッド１０２Ａおよび電子部品接続パッド１０２Ｂや外部接続パッド１０２Ｃの露出部を画定する。このようなソルダーレジスト層１０３は、感光性を有する熱硬化性樹脂ペーストまたはフィルムを配線導体１０２ｂが形成された最外層の絶縁層１０１ｂ上に積層した後、半導体素子接続パッド１０２Ａおよび電子部品接続パッド１０２Ｂや外部接続パッド１０２Ｃの外周部を覆うとともに中央部を露出させる開口を有するように露光および現像し、硬化させることにより形成される。このため、半導体素子接続パッド１０２Ａおよび電子部品接続パッド１０２Ｂの露出部は、ソルダーレジスト層１０３の表面から凹んで位置することになるとともに外周部がソルダーレジスト層１０３の下に所定の幅で埋設されることになる。   The solder resist layer 103 protects the outermost wiring conductor 102b and defines exposed portions of the semiconductor element connection pads 102A, the electronic component connection pads 102B, and the external connection pads 102C. Such a solder resist layer 103 is formed by laminating a photosensitive thermosetting resin paste or film on the outermost insulating layer 101b on which the wiring conductor 102b is formed, and then connecting the semiconductor element connection pad 102A and the electronic component connection pad. It is formed by exposing, developing, and curing so as to have an opening that covers the outer peripheral portion of 102B and external connection pad 102C and exposes the central portion. Therefore, the exposed portions of the semiconductor element connection pads 102A and the electronic component connection pads 102B are recessed from the surface of the solder resist layer 103, and the outer peripheral portion is buried under the solder resist layer 103 with a predetermined width. Will be.

そして、半導体集積回路素子Ｅ１の電極端子と半導体素子接続パッド１０２Ａとを導電バンプＢ１を介して電気的に接続した後、半導体集積回路素子Ｅ１と配線基板１１０との間の隙間にエポキシ樹脂等の熱硬化性樹脂から成るアンダーフィルと呼ばれる充填樹脂Ｕ１を充填し、半導体集積回路素子Ｅ１が配線基板１１０上に実装される。さらに、その上に半導体素子搭載基板Ｅ２の電極端子と電子部品接続パッド１０２Ｂとを半田ボールＢ２を介して電気的に接続することにより半導体素子搭載基板Ｅ２が配線基板１１０上に実装され、これにより配線基板１１０上に半導体素子および電子部品が高密度に実装されることとなる。   Then, after electrically connecting the electrode terminal of the semiconductor integrated circuit element E1 and the semiconductor element connection pad 102A via the conductive bump B1, the gap between the semiconductor integrated circuit element E1 and the wiring substrate 110 is made of epoxy resin or the like. Filling resin U <b> 1 called underfill made of thermosetting resin is filled, and semiconductor integrated circuit element E <b> 1 is mounted on wiring substrate 110. Furthermore, the semiconductor element mounting board E2 is mounted on the wiring board 110 by electrically connecting the electrode terminals of the semiconductor element mounting board E2 and the electronic component connection pads 102B via the solder balls B2 thereon. Semiconductor elements and electronic components are mounted on the wiring board 110 with high density.

ところが近時、半導体集積回路素子Ｅ１は、その高集積度化が急激に進み、半導体集積回路素子Ｅ１における電極端子の配列ピッチが１５０μｍ未満と狭ピッチになってきている。これに伴い、この半導体集積回路素子Ｅ１の電極端子がフリップチップ接続される半導体素子接続パッド１０２Ａの配列ピッチも１５０μｍ未満と狭くなってきている。半導体素子接続パッド１０２Ａのピッチを狭くするためには、半導体素子接続パッド１０２Ａの径および隣接する半導体素子接続パッド１０２Ａ同士の間の少なくとも一方を小さいものとせざるを得ない。半導体素子接続パッド１０２Ａの径を小さくした場合、半導体素子接続パッド１０２Ａにおけるソルダーレジスト層１０３からの露出部の径も小さいものとなる。半導体素子接続パッド１０２Ａの露出部の径が小さい場合、ソルダーレジスト層１０３を形成する際に現像が不十分となり半導体素子接続パッド１０２Ａの露出部にソルダーレジスト層１０３の樹脂残渣が残り易くなるとともに、半導体素子接続パッド１０２Ａと導電バンプＢ１との接合面積が小さくなるので、半導体集積回路素子Ｅ１の電極端子と半導体素子接続パッド１０２Ａとを導電バンプＢ１を介して強固かつ良好に接続することが困難となる。
特開２０００−２４４０８８号公報 Recently, however, the degree of integration of the semiconductor integrated circuit element E1 has rapidly increased, and the arrangement pitch of the electrode terminals in the semiconductor integrated circuit element E1 has become a narrow pitch of less than 150 μm. Along with this, the arrangement pitch of the semiconductor element connection pads 102A to which the electrode terminals of the semiconductor integrated circuit element E1 are flip-chip connected is also narrowed to less than 150 μm. In order to reduce the pitch of the semiconductor element connection pads 102A, at least one of the diameters of the semiconductor element connection pads 102A and the adjacent semiconductor element connection pads 102A must be reduced. When the diameter of the semiconductor element connection pad 102A is reduced, the diameter of the exposed portion from the solder resist layer 103 in the semiconductor element connection pad 102A is also reduced. When the diameter of the exposed portion of the semiconductor element connection pad 102A is small, development is insufficient when forming the solder resist layer 103, and the resin residue of the solder resist layer 103 is likely to remain in the exposed portion of the semiconductor element connection pad 102A. Since the bonding area between the semiconductor element connection pad 102A and the conductive bump B1 is reduced, it is difficult to connect the electrode terminal of the semiconductor integrated circuit element E1 and the semiconductor element connection pad 102A firmly and well via the conductive bump B1. Become.
JP 2000-244088 A

本発明の課題は、エリアアレイ型の半導体素子をフリップチップ接続により搭載する配線基板において、半導体素子の電極端子が接続される半導体素子接続パッドの配列ピッチが１５０μｍ未満の狭いものであったとしても、半導体素子接続パッドにおけるソルダーレジスト層からの露出部の面積を十分に広いものとして、半導体素子の電極端子と半導体素子接続パッドとを導電バンプを介して強固かつ良好に接続することが可能な配線基板を提供することにある。   An object of the present invention is to provide a wiring board on which an area array type semiconductor element is mounted by flip chip connection, even if the arrangement pitch of the semiconductor element connection pads to which the electrode terminals of the semiconductor element are connected is less than 150 μm. Wiring that can connect the electrode terminal of the semiconductor element and the semiconductor element connection pad firmly and satisfactorily through the conductive bump, with a sufficiently wide area of the exposed portion from the solder resist layer in the semiconductor element connection pad It is to provide a substrate.

本発明の配線基板は、上面に半導体素子が搭載される搭載部を有する絶縁基体と、該絶縁基体の前記搭載部に、前記絶縁基体上から上端までが同じ径をして格子状の並びに被着されており、上面に前記半導体素子の電極が導電バンプを介して接続されるめっき層から成る円形の複数の半導体素子接続パッドと、前記絶縁基体上に被着されており、前記半導体素子接続パッドの側面を覆うとともに前記半導体素子接続パッドの上面を露出させるソルダーレジスト層とを具備して成る配線基板であって、前記ソルダーレジスト層は、少なくとも前記半導体素子接続パッドの上面全面を底面とする凹部を有することを特徴とするものである。 The wiring board according to the present invention includes an insulating base having a mounting portion on which a semiconductor element is mounted on the upper surface, and the mounting portion of the insulating base having the same diameter from the top to the upper end of the insulating base. A plurality of circular semiconductor element connection pads made of a plating layer to which the electrodes of the semiconductor element are connected via conductive bumps on the upper surface; and the semiconductor element connection And a solder resist layer that covers a side surface of the pad and exposes an upper surface of the semiconductor element connection pad, wherein the solder resist layer has at least the entire upper surface of the semiconductor element connection pad as a bottom surface. It has a recessed part, It is characterized by the above-mentioned.

本発明の配線基板の製造方法は、上面に半導体素子が搭載される搭載部を有する絶縁基体の前記搭載部にめっき層から成る円形の半導体素子接続パッドを格子状の並びに形成する工程と、前記絶縁基体上に前記半導体素子接続パッドを完全に埋めるソルダーレジスト層用の樹脂層を被着するとともに該樹脂層を部分的に除去して前記半導体素子接続パッドの側面を覆うとともに少なくとも該半導体素子接続パッドの上面全面を底面とする凹部を有するソルダーレジスト層を形成する工程とを行なうことを特徴とするものである。   The method of manufacturing a wiring board according to the present invention includes a step of forming circular semiconductor element connection pads made of a plating layer on the mounting portion of the insulating base having a mounting portion on which a semiconductor element is mounted on an upper surface, A resin layer for a solder resist layer that completely fills the semiconductor element connection pad is deposited on an insulating substrate, the resin layer is partially removed to cover the side surface of the semiconductor element connection pad, and at least the semiconductor element connection And a step of forming a solder resist layer having a recess having the entire upper surface of the pad as a bottom surface.

また、本発明の配線基板の製造方法は、上面に半導体素子が搭載される搭載部を有する絶縁基体の前記搭載部にめっき層から成る円形の半導体素子接続パッドを格子状の並びに形成するとともに前記搭載部の外側の上面にめっき層から成る電子部品接続パッドを形成する工程と、前記絶縁基体上に前記半導体素子接続パッドおよび前記電子部品接続パッドを完全に埋めるソルダーレジスト層用の樹脂層を被着するとともに該樹脂層を部分的に除去して前記半導体素子接続パッドの側面および前記電子部品接続パッドの側面を覆うとともに少なくとも前記半導体素子接続パッドの上面全面を底面とする凹部および前記電子部品接続パッドの上面中央部を露出させる開口部を有するソルダーレジスト層を形成する工程とを行なうことを特徴とするものである。   In the method for manufacturing a wiring board according to the present invention, circular semiconductor element connection pads made of a plating layer are formed in a grid pattern on the mounting portion of the insulating base having a mounting portion on which a semiconductor element is mounted on the upper surface. A step of forming an electronic component connection pad comprising a plating layer on the upper surface outside the mounting portion; and a resin layer for a solder resist layer that completely fills the semiconductor element connection pad and the electronic component connection pad on the insulating substrate. And the resin layer is partially removed to cover the side surface of the semiconductor element connection pad and the side surface of the electronic component connection pad, and at least the recess having the entire upper surface of the semiconductor element connection pad as the bottom surface and the electronic component connection And a step of forming a solder resist layer having an opening exposing the center of the upper surface of the pad. Than is.

本発明の配線基板によれば、前記半導体素子接続パッドの側面を覆うとともに上面を露出させるソルダーレジスト層は、少なくとも前記半導体素子接続パッドの上面全面を底面とする凹部を有することから、半導体素子接続パッドの上面におけるソルダーレジスト層からの露出面積を十分確保したままで、半導体素子接続パッドの径を小さいものとすることができる。したがって、半導体素子接続パッドの配列ピッチが例えば１５０μｍ未満の狭ピッチであったとしても、半導体素子接続パッドの上面におけるソルダーレジスト層からの露出部の面積を十分に広いものとして、半導体素子の電極と半導体素子接続パッドとを導電バンプを介して強固かつ良好に接続することが可能な配線基板を提供することができる。
さらに、前記凹部が前記半導体素子の搭載される前記搭載部に対応する領域全体を前記底面とし、側壁が前記搭載部を取り囲むように形成されている場合には、配線基板と半導体素子との間に充填樹脂を充填する際に凹部の側壁が充填樹脂の外部流出を防止するダムとして機能するので、それにより充填樹脂の絶縁基体外周部への不要な流出を防止することができる。
さらにまた、前記凹部が前記半導体素子接続パッドの各々に対応して個別に形成されている場合には、半導体素子の電極端子を半導体素子接続パッドに導電バンプを介して接続する際に、前記凹部を導電バンプと半導体素子接続パッドとの位置決め用のガイドとして利用することができ、それにより配線基板への半導体素子の実装を容易なものとすることができる。
また、前記絶縁基体の上面における前記半導体素子が搭載される前記搭載部の外側に前記半導体素子以外の電子部品が接続されるめっき層から成る電子部品接続パッドが形成されているとともに前記電子部品接続パッドの上面中央部が前記ソルダーレジスト層から露出している場合には、狭ピッチ電極の半導体素子およびそれ以外の電子部品を配線基板上に高密度に実装することができる。 According to the wiring board of the present invention, the solder resist layer that covers the side surface of the semiconductor element connection pad and exposes the upper surface has a recess having at least the entire upper surface of the semiconductor element connection pad as a bottom surface. The diameter of the semiconductor element connection pad can be made small while ensuring a sufficient exposed area from the solder resist layer on the upper surface of the pad. Therefore, even if the arrangement pitch of the semiconductor element connection pads is a narrow pitch of, for example, less than 150 μm, the area of the exposed portion from the solder resist layer on the upper surface of the semiconductor element connection pad is sufficiently wide, It is possible to provide a wiring board that can be firmly and satisfactorily connected to the semiconductor element connection pads via the conductive bumps.
Further, when the concave portion is formed so that the entire region corresponding to the mounting portion on which the semiconductor element is mounted is the bottom surface, and the side wall surrounds the mounting portion, the wiring substrate and the semiconductor element are interposed. Since the side wall of the recess functions as a dam that prevents the filled resin from flowing out to the outside when the filled resin is filled, unnecessary leakage of the filled resin to the outer peripheral portion of the insulating base can be prevented.
Furthermore, when the recess is individually formed corresponding to each of the semiconductor element connection pads, when the electrode terminal of the semiconductor element is connected to the semiconductor element connection pad via the conductive bump, the recess Can be used as a guide for positioning the conductive bumps and the semiconductor element connection pads, whereby the semiconductor elements can be easily mounted on the wiring board.
In addition, an electronic component connection pad made of a plating layer to which an electronic component other than the semiconductor element is connected is formed outside the mounting portion on which the semiconductor element is mounted on the upper surface of the insulating base, and the electronic component connection When the center part of the upper surface of the pad is exposed from the solder resist layer, the semiconductor element of the narrow pitch electrode and the other electronic components can be mounted on the wiring board with high density.

本発明の配線基板の製造方法によれば、上面に半導体素子が搭載される搭載部を有する絶縁基体の前記搭載部にめっき層から成る円形の半導体素子接続パッドを格子状の並びに形成し、次に前記絶縁基体上に前記半導体素子接続パッドを完全に埋めるソルダーレジスト層用の樹脂層を被着するとともに該樹脂層を部分的に除去して前記半導体素子接続パッドの側面を覆うとともに少なくとも該半導体素子接続パッドの上面全面を底面とする凹部を有するソルダーレジスト層を形成することから、半導体素子接続パッドの上面の露出面積を十分確保したままで半導体素子接続パッドの径を小さいものとすることができ、したがって、半導体素子接続パッドの配列ピッチが例えば１５０μｍ未満の狭ピッチであったとしても、半導体素子接続パッド上面におけるソルダーレジスト層からの露出部の面積を十分に広いものとして、半導体素子の電極と半導体素子接続パッドとを導電バンプを介して強固かつ良好に接続することが可能な配線基板を提供することができる。   According to the method for manufacturing a wiring board of the present invention, circular semiconductor element connection pads made of a plating layer are formed in a grid pattern on the mounting portion of the insulating substrate having a mounting portion on which a semiconductor element is mounted on the upper surface. A resin layer for a solder resist layer that completely fills the semiconductor element connection pad is deposited on the insulating substrate, and the resin layer is partially removed to cover the side surface of the semiconductor element connection pad and at least the semiconductor Since the solder resist layer having a recess having the entire upper surface of the element connection pad as a bottom surface is formed, the diameter of the semiconductor element connection pad may be reduced while ensuring a sufficient exposed area of the upper surface of the semiconductor element connection pad. Therefore, even if the arrangement pitch of the semiconductor element connection pads is a narrow pitch of less than 150 μm, for example, the semiconductor element connection pads To provide a wiring board capable of firmly and satisfactorily connecting a semiconductor element electrode and a semiconductor element connection pad via a conductive bump, with an area of the exposed portion from the solder resist layer on the upper surface being sufficiently wide. Can do.

また、本発明の配線基板の製造方法によれば、上面に半導体素子が搭載される搭載部を有する絶縁基体の前記搭載部にめっき層から成る円形の半導体素子接続パッドを格子状の並びに形成するとともに前記搭載部の外側の上面にめっき層から成る電子部品接続パッドを形成し、次に前記絶縁基体上に前記半導体素子接続パッドおよび前記電子部品接続パッドを完全に埋めるソルダーレジスト層用の樹脂層を被着するとともに該樹脂層を部分的に除去して前記半導体素子接続パッドの側面および前記電子部品接続パッドの側面を覆うとともに少なくとも前記半導体素子接続パッドの上面全面を底面とする凹部および前記電子部品接続パッドの上面中央部を露出させる開口部を有するソルダーレジスト層を形成することから、上記に加え、狭ピッチ電極の半導体素子およびそれ以外の電子部品を高密度実装することが可能な配線基板を提供することができる。
さらに、本発明の配線基板の製造方法において、前記凹部を、前記半導体素子が搭載される前記搭載部に対応する領域全体を前記底面とし、側壁が前記搭載部を取り囲むように形成する場合には、配線基板と半導体素子との間に充填樹脂を充填する際に凹部の側壁を充填樹脂が外部に流出するのを防止するダムとして機能させることができるので、それにより充填樹脂の絶縁基体外周部への不要な流出を防止することが可能な配線基板を提供することができる。
さらにまた、本発明の配線基板の製造方法において、前記凹部を、前記半導体素子接続パッドの各々に対応して個別に形成する場合には、半導体素子の電極端子を半導体素子接続パッドに導電バンプを介して接続する際に、前記凹部を導電バンプと半導体素子接続パッドとの位置決め用のガイドとして利用することができ、それにより配線基板への半導体素子の実装を容易なものとした配線基板を提供することができる。 Further, according to the method for manufacturing a wiring board of the present invention, circular semiconductor element connection pads made of a plating layer are formed in a grid pattern on the mounting portion of the insulating base having a mounting portion on which a semiconductor element is mounted on the upper surface. And a resin layer for a solder resist layer that forms an electronic component connection pad made of a plating layer on the outer upper surface of the mounting portion, and then completely fills the semiconductor element connection pad and the electronic component connection pad on the insulating substrate. And the resin layer is partially removed to cover the side surface of the semiconductor element connection pad and the side surface of the electronic component connection pad, and at least the recess having the entire upper surface of the semiconductor element connection pad as the bottom surface and the electrons Since a solder resist layer having an opening exposing the central portion of the upper surface of the component connection pad is formed, in addition to the above, a narrow pipe is formed. A semiconductor element and other electronic components of the electrodes may provide a wiring board capable of high density mounting.
Furthermore, in the method for manufacturing a wiring board according to the present invention, when the concave portion is formed so that the entire region corresponding to the mounting portion on which the semiconductor element is mounted is the bottom surface and a side wall surrounds the mounting portion. When filling the filling resin between the wiring board and the semiconductor element, the side wall of the recess can function as a dam that prevents the filling resin from flowing out, so that the outer peripheral portion of the insulating base of the filling resin It is possible to provide a wiring board capable of preventing unnecessary outflow to the substrate.
Furthermore, in the method for manufacturing a wiring board according to the present invention, when the recess is formed individually corresponding to each of the semiconductor element connection pads, conductive bumps are formed on the semiconductor element connection pads. The wiring board can be used as a guide for positioning the conductive bump and the semiconductor element connection pad so that the semiconductor element can be easily mounted on the wiring board. can do.

以下、本発明にかかる配線基板およびその製造方法について図面を参照して詳細に説明する。
図１は、半導体素子としてのエリアアレイ型の半導体集積回路素子をフリップチップ接続により搭載し、さらにその上に別の電子部品としての半導体素子搭載基板を半田ボール接続により搭載した本発明にかかる配線基板の一例を示す概略断面図であり、図２は、図１の配線基板を示す平面図である。 Hereinafter, a wiring board and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a wiring according to the present invention in which an area array type semiconductor integrated circuit element as a semiconductor element is mounted by flip chip connection, and a semiconductor element mounting substrate as another electronic component is mounted thereon by solder ball connection. FIG. 2 is a schematic cross-sectional view showing an example of a substrate, and FIG. 2 is a plan view showing the wiring substrate of FIG.

図１および図２に示すように、本発明にかかる配線基板１０はコア用の絶縁基板１ａの上下面にビルドアップ用の絶縁層１ｂが積層されて成る絶縁基体１の内部および表面にコア用の配線導体２ａとビルドアップ用の配線導体２ｂとが被着されているとともに、その最表面に保護用のソルダーレジスト層３が被着されて成る。また、絶縁基体１の上面中央部には半導体集積回路素子Ｅ１が搭載される半導体素子搭載部１Ａおよび上面外周部には半導体素子搭載基板Ｅ２が搭載される電子部品搭載部１Ｂを有している。   As shown in FIG. 1 and FIG. 2, the wiring board 10 according to the present invention is used for the core inside and on the surface of the insulating base 1 in which the insulating layer 1b for buildup is laminated on the upper and lower surfaces of the insulating board 1a for the core. The wiring conductor 2a and the build-up wiring conductor 2b are deposited, and the protective solder resist layer 3 is deposited on the outermost surface thereof. The insulating base 1 has a semiconductor element mounting portion 1A on which the semiconductor integrated circuit element E1 is mounted at the center of the upper surface and an electronic component mounting portion 1B on which the semiconductor element mounting substrate E2 is mounted on the outer periphery of the upper surface. .

コア用の絶縁基板１ａは、厚みが０．０５〜１．５ｍｍ程度であり、例えばガラス繊維束を縦横に織ったガラスクロスにビスマレイミドトリアジン樹脂やエポキシ樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成る。絶縁基板１ａは、絶縁基体１のコア部材として機能する。   The core insulating substrate 1a has a thickness of about 0.05 to 1.5 mm. For example, a glass cloth in which glass fiber bundles are woven vertically and horizontally is impregnated with a thermosetting resin such as a bismaleimide triazine resin or an epoxy resin. Made of electrically insulating material. The insulating substrate 1 a functions as a core member of the insulating base 1.

コア用の絶縁基板１ａには、その上面から下面にかけて直径が０．０５〜０．３ｍｍ程度の複数のスルーホール４が形成されており、絶縁基板１ａの上下面およびスルーホール４の内面には、コア用の配線導体２ａが被着されている。コア用の配線導体２ａは、絶縁基板１ａの上下面では、主として銅箔または無電解銅めっきおよびその上の電解銅めっきから形成されており、スルーホール４の内面では、無電解銅めっきおよびその上の電解銅めっきから形成されている。   A plurality of through holes 4 having a diameter of about 0.05 to 0.3 mm are formed in the core insulating substrate 1a from the upper surface to the lower surface, and the upper and lower surfaces of the insulating substrate 1a and the inner surface of the through hole 4 are formed on the inner surface of the through hole 4. The core wiring conductor 2a is attached. The core wiring conductor 2a is mainly formed of copper foil or electroless copper plating and electrolytic copper plating thereon on the upper and lower surfaces of the insulating substrate 1a, and the electroless copper plating and its inner surface on the through hole 4 It is formed from the above electrolytic copper plating.

また、スルーホール４の内部には、エポキシ樹脂等の熱硬化性樹脂から成る埋め込み樹脂５が充填されており、絶縁基板１ａの上下面に形成された配線導体２ａ同士がスルーホール４内の配線導体２ａを介して電気的に接続されている。   The through hole 4 is filled with an embedded resin 5 made of a thermosetting resin such as an epoxy resin, and the wiring conductors 2a formed on the upper and lower surfaces of the insulating substrate 1a are connected to each other in the through hole 4. It is electrically connected via the conductor 2a.

このような絶縁基板１ａは、ガラス織物に未硬化の熱硬化性樹脂を含浸させたシートの上下面に配線導体２ａ用の銅箔を貼着した後、そのシートを熱硬化させ、これに上面から下面にかけてスルーホール４用のドリル加工を施すことにより作製される。   Such an insulating substrate 1a is obtained by sticking a copper foil for the wiring conductor 2a on the upper and lower surfaces of a sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then thermally curing the sheet, It is produced by drilling for the through hole 4 from the bottom to the bottom.

コア用の配線導体２ａは、絶縁基板１ａ用の前記シートの上下全面に、厚みが２〜１８μｍ程度の銅箔を上述のように貼着しておくとともに、これらの銅箔および絶縁基板１ａにスルーホール４を穿孔した後、このスルーホール４の内面および銅箔表面に無電解銅めっきおよび電解銅めっきを順次施し、次いで、スルーホール４内を埋め込み樹脂５で充填した後、この上下面の銅箔および銅めっきをフォトリソグラフィ技術を用いて所定のパターンにエッチング加工することにより、絶縁基板１ａの上下面およびスルーホール４の内面に形成される。   The core wiring conductor 2a has a copper foil having a thickness of about 2 to 18 μm adhered to the entire upper and lower surfaces of the sheet for the insulating substrate 1a as described above, and the copper foil and the insulating substrate 1a are attached to the copper foil and the insulating substrate 1a. After the through hole 4 is drilled, electroless copper plating and electrolytic copper plating are sequentially applied to the inner surface of the through hole 4 and the copper foil surface, and then the inside of the through hole 4 is filled with the embedded resin 5. The copper foil and the copper plating are etched into a predetermined pattern using a photolithography technique, so that the upper and lower surfaces of the insulating substrate 1a and the inner surface of the through hole 4 are formed.

埋め込み樹脂５は、スルーホール４を塞ぐことによりスルーホール４の直上および直下にビルドアップ用の絶縁層１ｂを形成可能とするためのものであり、未硬化のペースト状の熱硬化性樹脂をスルーホール４内にスクリーン印刷法により充填し、これを熱硬化させた後、その上下面を略平坦に研磨することにより形成される。   The embedding resin 5 is for allowing the build-up insulating layer 1b to be formed immediately above and immediately below the through-hole 4 by closing the through-hole 4, and through the uncured paste-like thermosetting resin. The hole 4 is formed by filling the hole 4 by screen printing, thermally curing it, and then polishing the upper and lower surfaces thereof to be substantially flat.

絶縁基板１ａの上下面に積層されたビルドアップ用の絶縁層１ｂは、それぞれの厚みが２０〜６０μｍ程度であり、絶縁基板１ａと同様にガラスクロスに熱硬化性樹脂を含浸させた電気絶縁材料や、あるいはエポキシ樹脂等の熱硬化性樹脂に酸化珪素等の無機フィラーを分散させた電気絶縁材料から成る。各絶縁層１ｂには、直径が３０〜１００μｍ程度の複数のビアホール６が形成されており、各絶縁層１ｂの表面およびビアホール６内にはビルドアップ用の配線導体２ｂが被着されている。   The insulating layers 1b for buildup laminated on the upper and lower surfaces of the insulating substrate 1a each have a thickness of about 20 to 60 μm. Similarly to the insulating substrate 1a, an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin Or, it is made of an electrically insulating material in which an inorganic filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin. A plurality of via holes 6 having a diameter of about 30 to 100 μm are formed in each insulating layer 1 b, and a buildup wiring conductor 2 b is attached to the surface of each insulating layer 1 b and the via hole 6.

これらの絶縁層１ｂは、配線導体２ａが形成された絶縁基板１ａの表面や配線導体２ｂが形成された絶縁層１ｂの表面に未硬化の熱硬化性樹脂組成物を含有する樹脂シートを貼着するとともに熱硬化させた後、その所定の位置にレーザ加工を施してビアホール６を穿孔することにより形成される。   These insulating layers 1b are bonded with a resin sheet containing an uncured thermosetting resin composition on the surface of the insulating substrate 1a on which the wiring conductor 2a is formed or on the surface of the insulating layer 1b on which the wiring conductor 2b is formed. Then, after thermosetting, the via hole 6 is formed by laser processing at a predetermined position.

ビルドアップ用の配線導体２ｂは、無電解銅めっきおよびその上の電解銅めっきから成り、絶縁層１ｂを挟んで上層に位置する配線導体２ｂと下層に位置する配線導体２ａまたは２ｂとをビアホール６内の配線導体２ｂを介して電気的に接続することにより、高密度配線を立体的に形成可能としている。   The build-up wiring conductor 2b is composed of electroless copper plating and electrolytic copper plating thereon, and the wiring conductor 2b located in the upper layer and the wiring conductor 2a or 2b located in the lower layer across the insulating layer 1b are connected to the via hole 6. High density wiring can be formed three-dimensionally by being electrically connected via the inner wiring conductor 2b.

このようなビルドアップ用の配線導体２ｂは、厚みが５〜２０μｍ程度であり、セミアディティブ法といわれる方法により形成される。セミアディティブ法は、例えば、ビアホール６が形成されたビルドアップ用の絶縁層１ｂの表面に、電解めっき用の下地めっき層を無電解銅めっきにより形成し、その上に配線導体２ｂに対応した開口を有するめっきレジスト層を形成し、次に、開口から露出する下地めっき層上に下地めっき層を給電用の電極として電解銅めっきを施すことで配線導体２ｂを形成し、めっきレジスト層を剥離した後、露出する下地めっき層をエッチング除去することによって、各配線導体２ｂを電気的に独立させる方法である。   Such a build-up wiring conductor 2b has a thickness of about 5 to 20 μm and is formed by a method called a semi-additive method. In the semi-additive method, for example, a base plating layer for electrolytic plating is formed by electroless copper plating on the surface of the build-up insulating layer 1b in which the via hole 6 is formed, and an opening corresponding to the wiring conductor 2b is formed thereon. Next, the copper conductor plating 2b was formed on the base plating layer exposed from the opening by using the base plating layer as an electrode for power feeding to form the wiring conductor 2b, and the plating resist layer was peeled off. Thereafter, each wiring conductor 2b is electrically independent by etching away the exposed base plating layer.

ビルドアップ用の配線導体２ｂのうち、配線基板１０の上面側における最外層の絶縁層１ｂ上に被着された一部は、半導体素子搭載部１Ａにおいて半導体集積回路素子Ｅ１の電極端子に半田等の導電バンプＢ１を介して電気的に接続される円形の半導体素子接続パッド２Ａを形成しており、これらの半導体素子接続パッド２Ａは格子状の並びに複数並んで形成されている。さらに、ビルドアップ用の配線導体２ｂのうち、配線基板１０の上面側における最外層の絶縁層１ｂ上に被着された他の一部は、電子部品搭載部１Ｂにおいて半導体素子搭載基板Ｅ２の電極端子に半田ボールＢ２を介して半田ボール接続により電気的に接続される円形の電子部品接続パッド２Ｂを形成しており、複数並んで形成されている。また、配線基板１０の下面側における最外層の絶縁層１ｂ上に被着された一部は、外部電気回路基板の配線導体に半田ボールＢ３を介して電気的に接続される外部接続用の外部接続パッド２Ｃを形成しており、複数並んで形成されている。   A part of the build-up wiring conductor 2b deposited on the outermost insulating layer 1b on the upper surface side of the wiring substrate 10 is soldered to the electrode terminal of the semiconductor integrated circuit element E1 in the semiconductor element mounting portion 1A. Circular semiconductor element connection pads 2A that are electrically connected via the conductive bumps B1 are formed, and a plurality of these semiconductor element connection pads 2A are formed in a lattice pattern. Further, of the build-up wiring conductor 2b, another part of the wiring conductor 2b deposited on the outermost insulating layer 1b on the upper surface side of the wiring substrate 10 is an electrode of the semiconductor element mounting substrate E2 in the electronic component mounting portion 1B. Circular electronic component connection pads 2B that are electrically connected to terminals by solder ball connection via solder balls B2 are formed, and a plurality of pads are formed side by side. In addition, a portion of the lower surface side of the wiring board 10 deposited on the outermost insulating layer 1b is electrically connected to the wiring conductor of the external electric circuit board via the solder balls B3. A connection pad 2C is formed, and a plurality of connection pads are formed side by side.

半導体素子接続パッド２Ａは、厚みが１０〜３０μｍ程度であり、その側面がソルダーレジスト層３で覆われているとともにその上面全面がソルダーレジスト層３から露出している。これらの半導体素子接続パッド２Ａは、その配列ピッチが１５０μｍ未満の狭ピッチであり、隣接する半導体素子接続パッド２Ａ間に十分な間隔を保ったままでその上面に半導体集積回路素子Ｅ１の電極端子との導電バンプＢ１を介した強固かつ良好な電気的接続のために十分な上面積を有するようにその直径が設定されており、例えばその配列ピッチが１４０μｍの場合であれば、その直径は８０〜１００μｍ程度、その配列ピッチが１３０μｍであれば、その直径は７０〜９０μｍ程度、その配列ピッチが１２０μｍであれば、その直径は６０〜８０μｍ程度に設定される。また、電子部品接続パッド２Ｂは、厚みが１０〜２０μｍ程度であり、その側面および上面外周部がソルダーレジスト層３で覆われており、その上面中央部がソルダーレジスト層３から露出している。電子部品接続パッド２Ｂは、直径が２００〜４５０μｍ程度であり、絶縁基体１の上面外周部に枠状の並びに４００〜６５０μｍの配列ピッチで形成されている。   The semiconductor element connection pad 2 </ b> A has a thickness of about 10 to 30 μm, its side surface is covered with the solder resist layer 3, and its entire upper surface is exposed from the solder resist layer 3. These semiconductor element connection pads 2A have a narrow pitch of less than 150 μm, and the upper surface of the semiconductor element connection pads 2A is connected to the electrode terminals of the semiconductor integrated circuit element E1 while maintaining a sufficient interval between the adjacent semiconductor element connection pads 2A. The diameter is set so as to have a sufficient upper area for strong and good electrical connection via the conductive bump B1, and for example, when the arrangement pitch is 140 μm, the diameter is 80 to 100 μm. If the arrangement pitch is 130 μm, the diameter is set to about 70 to 90 μm, and if the arrangement pitch is 120 μm, the diameter is set to about 60 to 80 μm. The electronic component connection pad 2 </ b> B has a thickness of about 10 to 20 μm, its side surface and upper surface outer peripheral portion are covered with the solder resist layer 3, and its upper surface central portion is exposed from the solder resist layer 3. The electronic component connection pads 2B have a diameter of about 200 to 450 μm, and are formed on the outer periphery of the upper surface of the insulating base 1 with a frame shape and an array pitch of 400 to 650 μm.

さらに、最外層の絶縁層１ｂ上には、ソルダーレジスト層３が被着されている。ソルダーレジスト層３は、最外層の配線導体２ｂを熱や外部環境から保護するための保護膜であり、上面側のソルダーレジスト層３は半導体素子接続パッド２Ａの側面および電子部品接続パッド２Ｂの側面を覆うとともに半導体素子接続パッド２Ａの上面全面および電子部品接続パッド２Ｂの上面中央部を露出させるようにして被着されている。また、下面側のソルダーレジスト層３は、外部接続パッド２Ｃの側面を覆うとともに外部接続パッド２Ｃの中央部を露出させるようにして被着されている。   Further, a solder resist layer 3 is deposited on the outermost insulating layer 1b. The solder resist layer 3 is a protective film for protecting the outermost wiring conductor 2b from heat and the external environment. The solder resist layer 3 on the upper surface side is a side surface of the semiconductor element connection pad 2A and a side surface of the electronic component connection pad 2B. And the entire upper surface of the semiconductor element connection pad 2A and the center of the upper surface of the electronic component connection pad 2B are exposed. Further, the solder resist layer 3 on the lower surface side is attached so as to cover the side surface of the external connection pad 2C and to expose the central portion of the external connection pad 2C.

上面側のソルダーレジスト層３は、少なくとも半導体素子接続パッド２Ａの上面全面を底面とする凹部３Ａを有している。なお本実施形態例における凹部３Ａは、半導体素子搭載部１Ａに対応する領域全体およびその周囲を底面とし、その側壁が半導体素子搭載部１Ａを取り囲むように形成されている。また、上面側のソルダーレジスト層３は、電子部品接続パッド２Ｂの上面中央部を露出させる円形の開口部３Ｂを有している。これにより電子部品接続パッド２Ｂの外周部がソルダーレジスト層３により覆われるとともに電子部品接続パッド２Ｂの中央部がソルダーレジスト層３より露出することとなる。また、下面側のソルダーレジスト層３は、外部接続パッド２Ｃの下面中央部を露出させる円形の開口部３Ｃを有している。これにより外部接続パッド２Ｃの外周部がソルダーレジスト層３により覆われるとともに外部接続パッド２Ｃの中央部がソルダーレジスト層３より露出することとなる。   The solder resist layer 3 on the upper surface side has a recess 3A having at least the entire upper surface of the semiconductor element connection pad 2A as the bottom surface. The recess 3A in the present embodiment is formed so that the entire region corresponding to the semiconductor element mounting portion 1A and the periphery thereof are the bottom surface, and the side wall surrounds the semiconductor element mounting portion 1A. The solder resist layer 3 on the upper surface side has a circular opening 3B that exposes the center of the upper surface of the electronic component connection pad 2B. As a result, the outer peripheral portion of the electronic component connection pad 2B is covered with the solder resist layer 3, and the central portion of the electronic component connection pad 2B is exposed from the solder resist layer 3. Further, the solder resist layer 3 on the lower surface side has a circular opening 3C that exposes the center of the lower surface of the external connection pad 2C. As a result, the outer peripheral portion of the external connection pad 2C is covered with the solder resist layer 3, and the central portion of the external connection pad 2C is exposed from the solder resist layer 3.

そして、本発明の配線基板１０においては、半導体素子接続パッド２Ａの側面がソルダーレジスト層３で覆われているとともに半導体素子接続パッド２Ａの上面全面がソルダーレジスト層３から露出していることから、半導体素子接続パッド２Ａの配列ピッチが１５０μｍ未満の狭ピッチであったとしても、隣接する半導体素子接続パッド２Ａ間の電気的な絶縁性を良好に保ったままで半導体素子接続パッド２Ａの上面に半導体集積回路素子Ｅ１の電極端子との導電バンプＢ１を介した強固かつ良好な電気的接続のために必要な面積を確保することができる。したがって、半導体素子接続パッド２Ａの上面におけるソルダーレジスト層３からの露出部の面積を十分に広いものとして、半導体集積回路素子Ｅ１の電極と半導体素子接続パッド２Ａとを導電バンプＢ１を介して強固かつ良好に接続することが可能な配線基板を提供することができる。また、本実施形態例では上面側のソルダーレジスト層３に形成された凹部３Ａは、半導体素子搭載部１Ａに対応する領域全体を底面とし、その側壁が半導体素子搭載部１Ａを取り囲むようにして形成されているので、配線基板１０と半導体集積回路素子Ｅ１との間に充填樹脂Ｕ１を充填する際に凹部３Ａの側壁が充填樹脂Ｕ１の外部流出を防止するダムとして機能するので、それにより充填樹脂Ｕ１の絶縁基体１外周部への不要な流出を防止することができる。   In the wiring board 10 of the present invention, the side surface of the semiconductor element connection pad 2A is covered with the solder resist layer 3 and the entire upper surface of the semiconductor element connection pad 2A is exposed from the solder resist layer 3. Even if the arrangement pitch of the semiconductor element connection pads 2A is a narrow pitch of less than 150 μm, the semiconductor integration on the upper surface of the semiconductor element connection pads 2A while maintaining good electrical insulation between the adjacent semiconductor element connection pads 2A. An area necessary for strong and good electrical connection with the electrode terminal of the circuit element E1 through the conductive bump B1 can be secured. Therefore, the area of the exposed portion from the solder resist layer 3 on the upper surface of the semiconductor element connection pad 2A is made sufficiently wide so that the electrode of the semiconductor integrated circuit element E1 and the semiconductor element connection pad 2A are firmly and electrically connected via the conductive bump B1. It is possible to provide a wiring board that can be satisfactorily connected. In this embodiment, the recess 3A formed in the solder resist layer 3 on the upper surface side is formed so that the entire region corresponding to the semiconductor element mounting portion 1A is the bottom surface and the side wall surrounds the semiconductor element mounting portion 1A. Therefore, when the filling resin U1 is filled between the wiring substrate 10 and the semiconductor integrated circuit element E1, the sidewall of the recess 3A functions as a dam for preventing the filling resin U1 from flowing out. Unnecessary outflow of U1 to the outer periphery of the insulating substrate 1 can be prevented.

なお、上面側のソルダーレジスト層３に形成された凹部３Ａはその側壁が半導体素子搭載部１Ａよりも４００〜１３００μｍ程度外側に位置することが好ましい。凹部３Ａの側壁の位置が半導体素子搭載部１Ａよりも３００μｍ未満外側に位置する場合には、配線基板１０と半導体集積回路素子Ｅ１との間に充填樹脂Ｕ１を充填する際の作業性が低下する恐れがあり、逆に１３００μｍを超えて外側に位置する場合、充填樹脂Ｕ１が不要に広がりすぎてしまう危険がある。また、凹部３Ａの深さは５〜１５μｍ程度が好ましい。凹部３Ａの深さが５μｍ未満であると、配線基板１０と半導体集積回路素子Ｅ１との間に充填樹脂Ｕ１を充填する際に凹部３Ａの側壁が充填樹脂Ｕ１の外部流出を防止するダムとして十分に機能せずに充填樹脂Ｕ１の一部が絶縁基体１の外周部へ流出するのを有効に防止することが困難となる危険性があり、１５μｍを超えると、ソルダーレジスト層３の加工性が低下してしまう。   In addition, it is preferable that the side wall of the recess 3A formed in the solder resist layer 3 on the upper surface side is located on the outside of the semiconductor element mounting portion 1A by about 400 to 1300 μm. When the position of the side wall of the recess 3A is located less than 300 μm outside of the semiconductor element mounting portion 1A, the workability when filling the filling resin U1 between the wiring substrate 10 and the semiconductor integrated circuit element E1 is lowered. On the contrary, when it is located outside beyond 1300 μm, there is a risk that the filling resin U1 is unnecessarily spread too much. The depth of the recess 3A is preferably about 5 to 15 μm. When the depth of the recess 3A is less than 5 μm, the side wall of the recess 3A is sufficient as a dam for preventing the filling resin U1 from flowing out when the filling resin U1 is filled between the wiring substrate 10 and the semiconductor integrated circuit element E1. There is a risk that it is difficult to effectively prevent a part of the filling resin U1 from flowing out to the outer peripheral portion of the insulating base 1 without functioning, and if it exceeds 15 μm, the workability of the solder resist layer 3 is increased. It will decline.

また、電子部品接続パッド２Ｂの上面中央部は、ソルダーレジスト層３に設けた開口３Ｂ内に露出しており、この開口３Ｂとで形成される凹部の底面を形成している。これにより、半導体素子搭載基板Ｅ２を配線基板１０上に実装する際に、半導体素子搭載基板Ｅ２の電極端子と電子部品接続パッド２Ｂとを接続する半田ボールＢ２が電子部品接続パッド２Ｂ上に良好に位置決めされ、半導体素子搭載基板Ｅ２を配線基板１０上に良好に搭載することが可能になる。   Further, the central portion of the upper surface of the electronic component connection pad 2B is exposed in the opening 3B provided in the solder resist layer 3, and forms the bottom surface of the recess formed by the opening 3B. As a result, when the semiconductor element mounting board E2 is mounted on the wiring board 10, the solder balls B2 that connect the electrode terminals of the semiconductor element mounting board E2 and the electronic component connection pads 2B are satisfactorily formed on the electronic component connection pads 2B. Thus, the semiconductor element mounting substrate E2 can be satisfactorily mounted on the wiring substrate 10.

なお、ソルダーレジスト層３から露出する半導体素子接続パッド２Ａの上面および電子部品接続パッド２Ｂの上面には、半導体素子接続パッド２Ａおよび電子部品接続パッド２Ｂが酸化腐食するのを防止するとともに、導電バンプＢ１や半田ボールＢ２との接続を良好とするために、ニッケルめっきおよび金めっきを無電解めっき法や電解めっき法により順次被着させておくか、あるいは錫やインジウム等を含む半田層を被着させておいてもよい。
そして、半導体集積回路素子Ｅ１の電極端子と半導体素子接続パッド２Ａとを導電バンプＢ１を介して電気的に接続した後、半導体集積回路素子Ｅ１と配線基板１０との間の隙間にエポキシ樹脂等の熱硬化性樹脂から成るアンダーフィルと呼ばれる充填樹脂Ｕ１を充填し、半導体集積回路素子Ｅ１が配線基板１０上に実装される。さらに、その上に半導体素子搭載基板Ｅ２の電極端子と電子部品接続パッド２Ｂとを半田ボールＢ２を介して電気的に接続することにより半導体素子搭載基板Ｅ２が配線基板１０上に実装され、これにより配線基板１０上に半導体素子および電子部品が高密度に実装されることとなる。 The upper surface of the semiconductor element connection pad 2A and the upper surface of the electronic component connection pad 2B exposed from the solder resist layer 3 prevent the semiconductor element connection pad 2A and the electronic component connection pad 2B from being oxidatively corroded and conductive bumps. In order to improve the connection with B1 and solder ball B2, nickel plating and gold plating are sequentially applied by electroless plating or electrolytic plating, or a solder layer containing tin, indium, or the like is applied. You may leave it.
Then, after electrically connecting the electrode terminal of the semiconductor integrated circuit element E1 and the semiconductor element connection pad 2A via the conductive bump B1, the gap between the semiconductor integrated circuit element E1 and the wiring substrate 10 is made of epoxy resin or the like. Filling resin U <b> 1 called an underfill made of thermosetting resin is filled, and semiconductor integrated circuit element E <b> 1 is mounted on wiring substrate 10. Furthermore, the semiconductor element mounting board E2 is mounted on the wiring board 10 by electrically connecting the electrode terminals of the semiconductor element mounting board E2 and the electronic component connection pads 2B via the solder balls B2 thereon. Semiconductor elements and electronic components are mounted on the wiring board 10 with high density.

次に、本発明の配線基板の製造方法を、上述の半導体素子接続パッド２Ａ、電子部品接続パッド２Ｂおよびソルダーレジスト層３の形成を例にして、図３〜図９を基に説明する。   Next, a method for manufacturing a wiring board according to the present invention will be described with reference to FIGS. 3 to 9 by taking as an example the formation of the semiconductor element connection pad 2A, the electronic component connection pad 2B, and the solder resist layer 3.

まず、図３（ａ）に示すように、上面側における最外層の絶縁層１ｂにビアホール６を形成する。ビアホール６の形成には、例えば炭酸ガスレーザやＹＡＧレーザが用いられる。次に、図３（ｂ）に示すように、前記絶縁層１ｂの表面およびビアホー６内の全面にわたって、電解めっき用の下地めっき層５１を無電解めっきにより被着形成する。下地めっき層５１を形成する無電解めっきとしては、無電解銅めっきが好ましい。
次いで、図４（ｃ）に示すように、下地めっき層５１の表面に、感光性アルカリ現像型ドライフィルムレジストＤＦＲ１を貼着するとともに、これをフォトリソグラフィ技術を用いて露光および現像を行なうことにより、図４（ｄ）に示すように、半導体素子接続パッド２Ａに対応する形状の半導体素子接続パッド形成用開口Ｍ１Ａおよび電子部品接続パッド２Ｂに対応する形状の電子部品接続パッド形成用開口Ｍ１Ｂを有するめっきマスクＭ１を形成する。なお、めっきマスクＭ１の厚みは、後に形成する半導体素子接続パッド２Ａおよび電子部品接続パッド２Ｂの厚みよりも若干厚い厚みであるのがよい。 First, as shown in FIG. 3A, a via hole 6 is formed in the outermost insulating layer 1b on the upper surface side. For example, a carbon dioxide laser or a YAG laser is used to form the via hole 6. Next, as shown in FIG. 3B, a base plating layer 51 for electrolytic plating is deposited on the surface of the insulating layer 1b and the entire surface of the via-ho 6 by electroless plating. As the electroless plating for forming the base plating layer 51, electroless copper plating is preferable.
Next, as shown in FIG. 4 (c), a photosensitive alkaline development type dry film resist DFR1 is adhered to the surface of the base plating layer 51, and this is exposed and developed using a photolithography technique. 4D, a semiconductor element connection pad forming opening M1A having a shape corresponding to the semiconductor element connection pad 2A and an electronic component connection pad forming opening M1B having a shape corresponding to the electronic component connection pad 2B are provided. A plating mask M1 is formed. The thickness of the plating mask M1 is preferably slightly thicker than the thickness of the semiconductor element connection pad 2A and the electronic component connection pad 2B to be formed later.

次いで、図５（ｅ）に示すように、めっきマスクＭ１の半導体素子接続パッド形成用開口Ｍ１Ａおよび電子部品接続パッド形成用開口Ｍ１Ｂ内に露出する下地めっき層５１上に、半導体素子接続パッド２Ａおよび電子部品接続パッド２Ｂに対応した形状のめっき層５２を電解めっき法により被着形成する。めっき層５２を形成するための電解めっきとしては、電解銅めっきが好ましい。ここで、めっき層５２の厚みは、めっきマスクＭ１より薄くなっている。具体的には、めっき層５２の厚みは、８〜２０μｍ、好ましくは１０〜１５μｍであるのがよい。   Next, as shown in FIG. 5 (e), the semiconductor element connection pad 2A and the semiconductor element connection pad 2A are formed on the underlying plating layer 51 exposed in the semiconductor element connection pad formation opening M1A and the electronic component connection pad formation opening M1B of the plating mask M1. A plating layer 52 having a shape corresponding to the electronic component connection pad 2B is formed by electrolytic plating. As the electrolytic plating for forming the plating layer 52, electrolytic copper plating is preferable. Here, the thickness of the plating layer 52 is thinner than the plating mask M1. Specifically, the thickness of the plating layer 52 is 8 to 20 μm, preferably 10 to 15 μm.

次いで、図５（ｆ）に示すように、めっきマスクＭ１を除去する。めっきマスクＭ１の除去は、例えば、水酸化ナトリウム水溶液への浸漬により行なうことができる。
次に、図６（ｇ）に示すように、めっき層５２で覆われた部分以外の下地めっき層５１を除去する。これにより、下地めっき層５１およびめっき層５２から成る半導体素子接続パッド２Ａと電子部品接続パッド２Ｂとが形成される。なお、めっき層５２で覆われた部分以外の下地めっき層５１を除去するには、前記めっきマスクＭ１を除去した後に露出する下地めっき層５１を、例えば、過酸化水素水や過硫酸ナトリウム等を含有するエッチング液によりエッチング除去する方法を採用すればよい。 Next, as shown in FIG. 5F, the plating mask M1 is removed. The plating mask M1 can be removed, for example, by immersion in an aqueous sodium hydroxide solution.
Next, as shown in FIG. 6G, the base plating layer 51 other than the portion covered with the plating layer 52 is removed. Thereby, the semiconductor element connection pad 2A and the electronic component connection pad 2B composed of the base plating layer 51 and the plating layer 52 are formed. In order to remove the base plating layer 51 other than the portion covered with the plating layer 52, the base plating layer 51 exposed after the removal of the plating mask M1, for example, hydrogen peroxide water or sodium persulfate is used. What is necessary is just to employ | adopt the method of carrying out the etching removal with the etching liquid containing.

次いで、図６（ｈ）に示すように、上面側における最外層の絶縁層１ｂ上の全面に半導体素子接続パッド２Ａおよび電子部品接続パッド２Ｂを覆うソルダーレジスト層用の樹脂層３Ｐを被着するとともに、これをフォトリソグラフィ技術を用いて露光および現像を行なうことにより、図７（ｉ）に示すように、電子部品接続パッド２Ｂの上面中央部を露出させる開口３Ｂを形成する。ソルダーレジスト層用の樹脂３Ｐとしては、配線基板の表面を保護するソルダーレジスト層として機能する各種の公知の樹脂が採用可能であり、具体的には、例えば、アクリル変性エポキシ樹脂等に酸化珪素やタルク等の無機物粉末フィラーを３０〜７０質量％程度分散させた感光性を有する熱硬化性樹脂が好ましい。   Next, as shown in FIG. 6H, a resin layer 3P for a solder resist layer covering the semiconductor element connection pad 2A and the electronic component connection pad 2B is deposited on the entire surface on the outermost insulating layer 1b on the upper surface side. At the same time, exposure and development are performed using a photolithography technique, thereby forming an opening 3B that exposes the center of the upper surface of the electronic component connection pad 2B, as shown in FIG. 7 (i). As the resin 3P for the solder resist layer, various known resins that function as a solder resist layer for protecting the surface of the wiring board can be employed. Specifically, for example, silicon oxide or acryl-modified epoxy resin or the like can be used. A photosensitive thermosetting resin in which about 30 to 70% by mass of an inorganic powder filler such as talc is dispersed is preferable.

次に、図７（ｊ）に示すように、ソルダーレジスト層３上の全面に開口３Ｂを覆う第２の感光性アルカリ現像型ドライフィルムレジストＤＦＲ２を貼着するとともに、これをフォトリソグラフィ技術を用いて露光および現像を行なうことにより、図８（ｋ）に示すように、ソルダーレジスト層３の上面における少なくとも半導体素子接続パッド２Ａに対応する部分およびその周囲を露出させる開口Ｍ２Ａを有する研磨マスクＭ２を形成する。なお、この例では半導体素子搭載部１Ａに対応する領域全体およびその周囲を一括して露出させる開口Ｍ２Ａを形成している。研磨マスクＭ２の開口Ｍ２Ａの大きさは半導体素子搭載部１Ａよりも４００〜１３００μｍ程度外側まで露出させる大きさが好ましい。また厚みは、ソルダーレジスト層３上で１５μｍ以上あることが好ましい。   Next, as shown in FIG. 7 (j), a second photosensitive alkaline development type dry film resist DFR2 covering the opening 3B is attached to the entire surface of the solder resist layer 3, and this is applied using a photolithography technique. By performing exposure and development, a polishing mask M2 having an opening M2A exposing at least a portion corresponding to the semiconductor element connection pad 2A on the upper surface of the solder resist layer 3 and its periphery is formed as shown in FIG. Form. In this example, an opening M2A that exposes the entire region corresponding to the semiconductor element mounting portion 1A and the periphery thereof is formed. The size of the opening M2A of the polishing mask M2 is preferably such that it is exposed to the outside by about 400 to 1300 μm from the semiconductor element mounting portion 1A. The thickness is preferably 15 μm or more on the solder resist layer 3.

次に、図８（ｌ）に示すように、ソルダーレジスト層３における研磨マスクＭ２の開口Ｍ２Ａから露出した部位を、半導体素子接続パッド２Ａの上面全面が露出するまで研磨した後、研磨マスクＭ２を除去することによって、図９（ｍ）に示すように、前記研磨によりソルダーレジスト層３に形成された凹部３Ａ内に半導体素子接続パッド２Ａの上面全面が露出するとともにソルダーレジスト層３に形成された開口３Ｂ内に電子部品接続パッド２Ｂの上面中央部が露出した配線基板１０が得られる。このようにして本発明の配線基板の製造方法によれば、半導体素子接続パッド２Ａの上面の露出面積を十分確保したままで半導体素子接続パッド２Ａの径を小さいものとすることができ、したがって、半導体素子接続パッド２Ａの配列ピッチが例えば１５０μｍ未満の狭ピッチであったとしても、半導体素子接続パッド２Ａ上面におけるソルダーレジスト層３からの露出部の面積を十分に広いものとして、半導体集積回路素子Ｅ１の電極端子と半導体素子接続パッド２Ａとを導電バンプＢ１を介して強固かつ良好に接続することが可能な配線基板を提供することができる。さらに、本例のように凹部３Ａが半導体素子搭載部１Ａに対応する領域全体を底面とし、側壁が半導体素子搭載部１Ａを取り囲むように形成される場合には、配線基板１０と半導体集積回路素子Ｅ１との間に充填樹脂Ｕ１を充填する際に凹部３Ａの側壁を充填樹脂Ｕ１が外部に流出するのを防止するダムとして機能させることができるので、それにより充填樹脂Ｕ１の絶縁基体１外周部への不要な流出を防止することが可能な配線基板１０を提供することができる。なお、前記研磨には、ウエットブラスト法を含む各種の公知の機械的研磨方法やレーザスクライブ法を採用すればよい。   Next, as shown in FIG. 8L, after polishing the portion of the solder resist layer 3 exposed from the opening M2A of the polishing mask M2 until the entire upper surface of the semiconductor element connection pad 2A is exposed, the polishing mask M2 is removed. By removing, the entire upper surface of the semiconductor element connection pad 2A is exposed and formed in the solder resist layer 3 in the recess 3A formed in the solder resist layer 3 by the polishing, as shown in FIG. 9 (m). A wiring substrate 10 is obtained in which the center of the upper surface of the electronic component connection pad 2B is exposed in the opening 3B. Thus, according to the method for manufacturing a wiring board of the present invention, the diameter of the semiconductor element connection pad 2A can be reduced while sufficiently securing the exposed area of the upper surface of the semiconductor element connection pad 2A. Even if the arrangement pitch of the semiconductor element connection pads 2A is, for example, a narrow pitch of less than 150 μm, the area of the exposed portion from the solder resist layer 3 on the upper surface of the semiconductor element connection pad 2A is made sufficiently wide, so that the semiconductor integrated circuit element E1 It is possible to provide a wiring board capable of firmly and satisfactorily connecting the electrode terminal and the semiconductor element connection pad 2A via the conductive bump B1. Further, when the recess 3A is formed so that the entire region corresponding to the semiconductor element mounting portion 1A is the bottom surface and the side wall surrounds the semiconductor element mounting portion 1A as in this example, the wiring substrate 10 and the semiconductor integrated circuit element are formed. When the filling resin U1 is filled with E1, the side wall of the recess 3A can function as a dam that prevents the filling resin U1 from flowing out, so that the outer peripheral portion of the insulating substrate 1 of the filling resin U1 It is possible to provide the wiring substrate 10 that can prevent unnecessary outflow to the substrate. In addition, what is necessary is just to employ | adopt the various well-known mechanical grinding | polishing methods and the laser scribing method including the wet blasting method for the said grinding | polishing.

上記のようにしてソルダーレジスト層３が被着形成された配線基板１０においては、図１に示すように、エリアアレイ型の半導体集積回路素子Ｅ１の電極端子（ピッチが１５０μｍ未満）と半導体素子接続パッド２Ａとを導電バンプＢ１を介して電気的に接続（フリップチップ接続）することによって、半導体集積回路素子Ｅ１の電極端子と配線導体２ｂとが電気的に接続される。   In the wiring substrate 10 on which the solder resist layer 3 is deposited as described above, as shown in FIG. 1, the electrode terminals (pitch is less than 150 μm) of the area array type semiconductor integrated circuit element E1 are connected to the semiconductor element. By electrically connecting the pad 2A via the conductive bump B1 (flip chip connection), the electrode terminal of the semiconductor integrated circuit element E1 and the wiring conductor 2b are electrically connected.

半導体集積回路素子Ｅ１の電極端子と配線導体２ｂとを電気的に接続した後、半導体集積回路素子Ｅ１と配線基板１０との間の隙間に充填樹脂Ｕ１を充填することにより、半導体集積回路素子Ｅ１は配線基板１０上に実装される。   After electrically connecting the electrode terminal of the semiconductor integrated circuit element E1 and the wiring conductor 2b, the gap between the semiconductor integrated circuit element E1 and the wiring substrate 10 is filled with the filling resin U1, thereby the semiconductor integrated circuit element E1. Is mounted on the wiring board 10.

そして、さらにその上に、電子部品としての半導体素子搭載基板Ｅ２の電極端子と電子部品接続パッド２Ｂとを半田ボールＢ２を介して接続することにより、半導体素子搭載基板Ｅ２と配線基板１０の配線導体２ｂとが電気的に接続され、半導体素子搭載基板Ｅ２が配線基板１０上に半田ボール接続により実装される。このようにして、本発明の配線基板上に半導体素子と電子部品とが高密度実装される。ここで、電子部品接続パッド２Ｂの上面は、ソルダーレジスト層３の開口３Ｂとで形成される凹部の底面を形成しているので、この凹部内に半田ボールＢ２が良好に位置決めされ、半導体素子搭載基板Ｅ２を配線基板１０上に良好に接続することが可能となる。   Further, by further connecting the electrode terminal of the semiconductor element mounting board E2 as an electronic component and the electronic component connection pad 2B via the solder ball B2, the wiring conductor of the semiconductor element mounting board E2 and the wiring board 10 is further provided. The semiconductor element mounting board E2 is mounted on the wiring board 10 by solder ball connection. In this way, the semiconductor element and the electronic component are mounted with high density on the wiring board of the present invention. Here, since the upper surface of the electronic component connection pad 2B forms the bottom surface of the recess formed by the opening 3B of the solder resist layer 3, the solder ball B2 is well positioned in the recess and the semiconductor element mounting It becomes possible to connect the board | substrate E2 on the wiring board 10 favorably.

なお、上述した実施形態例では、上面側のソルダーレジスト層３を１層の樹脂層３Ｐにより形成した例を示したが、図１０に示すように、上面側のソルダーレジスト層３を下層のソルダーレジスト層３ａおよび上層のソルダーレジスト層３ｂの２層構造としてもよい。ソルダーレジスト層３をこのような２層構造とする場合、上述の図９（ｍ）を基に説明した工程において形成したソルダーレジスト層３を下層のソルダーレジスト層３ａとし、次に図１１（ａ）に示すように、下層のソルダーレジスト３ａの上に半導体素子接続パッド２Ａおよび電子部品接続パッド２Ｂを覆うソルダーレジスト層用の樹脂層３Ｑを被着するとともに、これをフォトリソグラフィ技術を用いて露光および現像を行なうことにより、図１１（ｂ）に示すように、下層のソルダーレジスト層３ａにおける凹部３Ａより若干大きな凹部３Ａおよび下層のソルダーレジスト層３ａにおける開口部３Ｂよりも若干大きな開口部３Ｂを上層のソルダーレジスト層３ｂに形成すればよい。この場合、下層のソルダーレジスト層３ａの厚みを薄いものとすることにより、下層のソルダーレジスト３ａに凹部３Ａを形成する際の研磨の作業性を高めることができる。また、搭載部１Ａの外側を覆うソルダーレジスト層３の厚みを厚くすることが容易であり、それにより電子部品接続パッド２Ｂ間の電気的絶縁信頼性を高くすることができるとともに、配線基板２０と半導体集積回路素子Ｅ１との間に充填樹脂Ｕ１を充填する際に充填樹脂Ｕ１が外部に流出するのを防止するダムとしての凹部３Ａの側壁の機能を高めることができる。   In the above-described embodiment, the example in which the solder resist layer 3 on the upper surface side is formed by the single resin layer 3P has been shown. However, as shown in FIG. A two-layer structure of a resist layer 3a and an upper solder resist layer 3b may be used. When the solder resist layer 3 has such a two-layer structure, the solder resist layer 3 formed in the process described based on FIG. 9 (m) is used as the lower solder resist layer 3a, and then FIG. ), A solder resist layer resin layer 3Q covering the semiconductor element connection pad 2A and the electronic component connection pad 2B is deposited on the lower layer solder resist 3a, and this is exposed using a photolithography technique. By performing the development, as shown in FIG. 11B, a recess 3A slightly larger than the recess 3A in the lower solder resist layer 3a and an opening 3B slightly larger than the opening 3B in the lower solder resist layer 3a are formed. What is necessary is just to form in the solder resist layer 3b of an upper layer. In this case, by reducing the thickness of the lower solder resist layer 3a, it is possible to improve the workability of polishing when the recess 3A is formed in the lower solder resist 3a. In addition, it is easy to increase the thickness of the solder resist layer 3 that covers the outside of the mounting portion 1A, whereby the electrical insulation reliability between the electronic component connection pads 2B can be increased, and the wiring board 20 and When the filling resin U1 is filled with the semiconductor integrated circuit element E1, the function of the side wall of the recess 3A as a dam that prevents the filling resin U1 from flowing out can be enhanced.

さらに、上述した実施形態例では、半導体素子接続パッド２Ａと電子部品接続パッド２Ｂはともに下地めっき層５１とめっき層５２とから成り、実質的に同じ厚みである例を示したが、図１２に示すように、半導体素子接続パッド２Ａの厚みが電子部品接続パッド２Ｂの厚みよりも厚いものであってもよい。このように半導体素子接続パッド２Ａの厚みを電子部品接続パッド２Ｂの厚みよりも厚くするには、上述の図５（ｅ）を基に説明した工程の後、図１３（ａ）に示すように、マスクＭ１の上に、開口Ｍ１Ａを露出させるとともに開口Ｍ１Ｂを覆う第２のマスクＭ２を被着形成した後、図１３（ｂ）に示すようにマスクＭ１の開口Ｍ１Ａ内に露出するめっき層５２の上に電解めっきにより第２のめっき層５３を被着させればよい。その後、マスクＭ１およびＭ２を除去し、露出する下地めっき層５１をエッチング除去すれば、図１４に示すように、下地めっき層５１およびめっき層５２および第２のめっき層５３からなる半導体素子接続パッド２Ａと下地めっき層５１およびめっき層５２からなる電子部品接続パッド２Ｂを形成することができる。その後は、上述した図６（ｈ）〜図９（ｍ）を基に説明した工程に準じてソルダーレジスト層３を形成すればよい。この場合、半導体素子接続パッド２Ａの上面は電子部品接続パッド２Ｂの上面よりも第２のめっき層５３の厚み分だけ上方に突出しているので、半導体集積回路素子Ｅ１と配線基板１０との間に十分な高さの隙間を確保できるようになり、充填樹脂Ｕ１の充填性に優れた配線基板を提供することができる。   Furthermore, in the above-described embodiment example, the semiconductor element connection pad 2A and the electronic component connection pad 2B are both composed of the base plating layer 51 and the plating layer 52, and an example having substantially the same thickness is shown in FIG. As shown, the thickness of the semiconductor element connection pad 2A may be thicker than the thickness of the electronic component connection pad 2B. Thus, in order to make the thickness of the semiconductor element connection pad 2A thicker than the thickness of the electronic component connection pad 2B, as shown in FIG. Then, after depositing and forming a second mask M2 that exposes the opening M1A and covers the opening M1B on the mask M1, the plating layer 52 exposed in the opening M1A of the mask M1 as shown in FIG. 13B. The second plating layer 53 may be deposited on the substrate by electrolytic plating. Thereafter, the masks M1 and M2 are removed, and the exposed underlying plating layer 51 is removed by etching. As shown in FIG. 14, the semiconductor element connection pad comprising the underlying plating layer 51, the plating layer 52, and the second plating layer 53 An electronic component connection pad 2B composed of 2A, the base plating layer 51 and the plating layer 52 can be formed. Thereafter, the solder resist layer 3 may be formed according to the steps described based on FIGS. 6 (h) to 9 (m) described above. In this case, the upper surface of the semiconductor element connection pad 2A protrudes above the upper surface of the electronic component connection pad 2B by the thickness of the second plating layer 53, so that the gap between the semiconductor integrated circuit element E1 and the wiring board 10 is increased. A sufficiently high gap can be secured, and a wiring board excellent in filling property of the filling resin U1 can be provided.

さらに、上述した例では上面側のソルダーレジスト３に、半導体素子搭載部１Ａに対応する領域全体を底面とし、側壁が半導体素子搭載部１Ａを取り囲む凹部１Ａを形成した例を示したが、図１５および図１６に示すように各半導体素子接続パッド２Ａをそれぞれ個別に露出させる凹部３ＡＡを設けることにより、この凹部３ＡＡの底面に半導体素子接続パッド２Ａの上面全面を露出させるようにしてもよい。半導体素子接続パッド２Ａに半導体集積回路素子Ｅ１の電極端子を導電バンプＢ１を介して接続する際に、凹部３ＡＡを導電バンプＢ１と半導体素子接続パッド２Ａとの位置決め用のガイドとして利用することができ、それにより配線基板１０への半導体集積回路素子Ｅ１の実装を容易なものとすることができる。   Further, in the above-described example, the solder resist 3 on the upper surface side is shown with the recess 1A in which the entire region corresponding to the semiconductor element mounting portion 1A is the bottom surface and the side wall surrounds the semiconductor element mounting portion 1A. Also, as shown in FIG. 16, by providing a recess 3AA for individually exposing each semiconductor element connection pad 2A, the entire upper surface of the semiconductor element connection pad 2A may be exposed on the bottom surface of this recess 3AA. When connecting the electrode terminal of the semiconductor integrated circuit element E1 to the semiconductor element connection pad 2A via the conductive bump B1, the recess 3AA can be used as a guide for positioning the conductive bump B1 and the semiconductor element connection pad 2A. As a result, the semiconductor integrated circuit element E1 can be easily mounted on the wiring board 10.

本発明の配線基板における一実施形態例を示す概略断面図である。It is a schematic sectional drawing which shows one example of embodiment in the wiring board of this invention. 図１の配線基板を示す平面図である。It is a top view which shows the wiring board of FIG. （ａ）〜（ｂ）は、本発明にかかる配線基板の製造方法を示す概略説明図である。(A)-(b) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. （ｃ）〜（ｄ）は、本発明にかかる配線基板の製造方法を示す概略説明図である。(C)-(d) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. （ｅ）〜（ｆ）は、本発明にかかる配線基板の製造方法を示す概略説明図である。(E)-(f) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. （ｇ）〜（ｈ）は、本発明にかかる配線基板の製造方法を示す概略説明図である。(G)-(h) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. （ｉ）〜（ｊ）は、本発明にかかる配線基板の製造方法を示す概略説明図である。(I)-(j) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. （ｋ）〜（ｌ）は、本発明にかかる配線基板の製造方法を示す概略説明図である。(K)-(l) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. （ｍ）は、本発明にかかる配線基板の製造方法を示す概略説明図である。(M) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning this invention. 本発明の配線基板における他の実施形態例を示す概略断面図である。It is a schematic sectional drawing which shows the other embodiment example in the wiring board of this invention. （ａ），（ｂ）は、図１０に示す配線基板の製造方法を示す概略説明図である。(A), (b) is a schematic explanatory drawing which shows the manufacturing method of the wiring board shown in FIG. 本発明の配線基板における更に他の実施形態例を示す概略断面図である。It is a schematic sectional drawing which shows other example of embodiment in the wiring board of this invention. （ａ），（ｂ）は、図１２に示す配線基板の製造方法を示す概略説明図である。(A), (b) is a schematic explanatory drawing which shows the manufacturing method of the wiring board shown in FIG. 図１２に示す配線基板の製造方法を示す概略説明図である。It is a schematic explanatory drawing which shows the manufacturing method of the wiring board shown in FIG. 本発明の配線基板における更に他の実施形態例を示す概略断面図である。It is a schematic sectional drawing which shows other example of embodiment in the wiring board of this invention. 図１５の配線基板を示す平面図である。It is a top view which shows the wiring board of FIG. 従来の配線基板を示す概略断面図である。It is a schematic sectional drawing which shows the conventional wiring board. 図１７の配線基板を示す平面図である。It is a top view which shows the wiring board of FIG.

符号の説明Explanation of symbols

１ 絶縁基体
１Ａ 搭載部
２Ａ 半導体素子接続パッド
２Ｂ 電子部品接続パッド
３ ソルダーレジスト層
３Ａ，３ＡＡ 凹部
５１ 下地めっき層
５２ めっき層
Ｍ１ めっきマスク
Ｍ１Ａ 半導体素子接続パッド形成用開口
Ｍ１Ｂ 電子部品接続パッド形成用開口 DESCRIPTION OF SYMBOLS 1 Insulation base | substrate 1A Mounting part 2A Semiconductor element connection pad 2B Electronic component connection pad 3 Solder resist layer 3A, 3AA Concave part 51 Base plating layer 52 Plating layer M1 Plating mask M1A Opening for semiconductor element connection pad formation M1B Opening for electronic component connection pad formation

Claims (8)

上面に半導体素子が搭載される搭載部を有する絶縁基体と、該絶縁基体の前記搭載部に、前記絶縁基体上から上端までが同じ径をして格子状の並びに被着されており、上面に前記半導体素子の電極が導電バンプを介して接続されるめっき層から成る円形の複数の半導体素子接続パッドと、前記絶縁基体上に被着されており、前記半導体素子接続パッドの側面を覆うとともに前記半導体素子接続パッドの上面を露出させるソルダーレジスト層とを具備して成る配線基板であって、前記ソルダーレジスト層は、少なくとも前記半導体素子接続パッドの上面全面を底面とする凹部を有することを特徴とする配線基板。 An insulating base having a mounting portion on which a semiconductor element is mounted on the upper surface, and the mounting portion of the insulating base are attached in a lattice pattern with the same diameter from the top to the upper end of the insulating base. A plurality of circular semiconductor element connection pads made of a plating layer to which the electrodes of the semiconductor element are connected via conductive bumps, are deposited on the insulating base, cover side surfaces of the semiconductor element connection pads, and A wiring board comprising a solder resist layer that exposes an upper surface of a semiconductor element connection pad, wherein the solder resist layer has a recess having at least the entire upper surface of the semiconductor element connection pad as a bottom surface. Wiring board to be used. 前記凹部は、少なくとも前記搭載部に対応する領域全体を前記底面とし、側壁が前記搭載部を取り囲むように形成されていることを特徴とする請求項１記載の配線基板。   The wiring substrate according to claim 1, wherein the concave portion is formed so that at least the entire region corresponding to the mounting portion is the bottom surface, and a side wall surrounds the mounting portion. 前記凹部は、前記半導体素子接続パッドの各々に対応して個別に形成されていることを特徴とする請求項１記載の配線基板。   2. The wiring board according to claim 1, wherein the recess is individually formed corresponding to each of the semiconductor element connection pads. 前記絶縁基体の上面における前記搭載部の外側に前記半導体素子以外の電子部品が接続されるめっき層から成る電子部品接続パッドが形成されているとともに前記電子部品接続パッドの上面中央部が前記ソルダーレジスト層から露出していることを特徴とする請求項１〜３のいずれかに記載の配線基板。   An electronic component connection pad made of a plating layer to which an electronic component other than the semiconductor element is connected is formed outside the mounting portion on the upper surface of the insulating base, and the central portion of the upper surface of the electronic component connection pad is the solder resist. The wiring board according to claim 1, wherein the wiring board is exposed from the layer. 上面に半導体素子が搭載される搭載部を有する絶縁基体の前記搭載部にめっき層から成る円形の半導体素子接続パッドを格子状の並びに形成する工程と、前記絶縁基体上に前記半導体素子接続パッドを完全に埋めるソルダーレジスト層用の樹脂層を被着するとともに該樹脂層を部分的に除去して前記半導体素子接続パッドの側面を覆うとともに少なくとも該半導体素子接続パッドの上面全面を底面とする凹部を有するソルダーレジスト層を形成する工程とを行なうことを特徴とする配線基板の製造方法。   Forming a circular semiconductor element connection pad made of a plating layer on the mounting portion of the insulating substrate having a mounting portion on which a semiconductor element is mounted on the upper surface; and forming the semiconductor element connection pad on the insulating substrate. A resin layer for a solder resist layer to be completely filled is deposited, and the resin layer is partially removed to cover the side surface of the semiconductor element connection pad, and at least a recess having the entire upper surface of the semiconductor element connection pad as a bottom surface And a step of forming a solder resist layer. 上面に半導体素子が搭載される搭載部を有する絶縁基体の前記搭載部にめっき層から成る円形の半導体素子接続パッドを格子状の並びに形成するとともに前記搭載部の外側の上面にめっき層から成る電子部品接続パッドを形成する工程と、前記絶縁基体上に前記半導体素子接続パッドおよび前記電子部品接続パッドを完全に埋めるソルダーレジスト層用の樹脂層を被着するとともに該樹脂層を部分的に除去して前記半導体素子接続パッドの側面および前記電子部品接続パッドの側面を覆うとともに少なくとも前記半導体素子接続パッドの上面全面を底面とする凹部および前記電子部品接続パッドの上面中央部を露出させる開口部を有するソルダーレジスト層を形成する工程とを行なうことを特徴とする配線基板の製造方法。   A circular semiconductor element connection pad made of a plating layer is formed in a grid pattern on the mounting portion of the insulating base having a mounting portion on which the semiconductor element is mounted on the upper surface, and an electron consisting of a plating layer on the upper surface outside the mounting portion. Forming a component connection pad; and depositing a resin layer for a solder resist layer that completely fills the semiconductor element connection pad and the electronic component connection pad on the insulating substrate and partially removing the resin layer A recess that covers the side surface of the semiconductor element connection pad and the side surface of the electronic component connection pad, and at least exposes the center of the upper surface of the electronic component connection pad. And a step of forming a solder resist layer. 前記凹部は、前記搭載部に対応する領域全体を前記底面とし、側壁が前記搭載部を取り囲むように形成されることを特徴とする請求項５または６記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 5, wherein the recess is formed so that the entire region corresponding to the mounting portion is the bottom surface, and a side wall surrounds the mounting portion. 前記凹部は、前記半導体素子接続パッドの各々に対応して個別に形成されることを特徴とする請求項５または６記載の配線基板の製造方法。
7. The method for manufacturing a wiring board according to claim 5, wherein the recess is formed individually corresponding to each of the semiconductor element connection pads.
JP2008251293A 2008-09-22 2008-09-29 Wiring board and manufacturing method thereof Active JP5058929B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2008251293A JP5058929B2 (en) 2008-09-29 2008-09-29 Wiring board and manufacturing method thereof
KR1020090087691A KR101627574B1 (en) 2008-09-22 2009-09-16 Wiring substrate and the method of manufacturing the same
US12/562,956 US8319115B2 (en) 2008-09-22 2009-09-18 Wiring board and manufacturing method thereof
TW98131878A TWI470758B (en) 2008-09-22 2009-09-22 Wiring board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008251293A JP5058929B2 (en) 2008-09-29 2008-09-29 Wiring board and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2010087018A JP2010087018A (en) 2010-04-15
JP5058929B2 true JP5058929B2 (en) 2012-10-24

Family

ID=42250733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008251293A Active JP5058929B2 (en) 2008-09-22 2008-09-29 Wiring board and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP5058929B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5113114B2 (en) 2009-04-06 2013-01-09 新光電気工業株式会社 Wiring board manufacturing method and wiring board
JP2014072372A (en) * 2012-09-28 2014-04-21 Ibiden Co Ltd Printed wiring board manufacturing method and printed wiring board
KR102186151B1 (en) * 2014-05-27 2020-12-03 삼성전기주식회사 Method of printed circuit board
TWI586236B (en) 2015-01-13 2017-06-01 旭德科技股份有限公司 Package carrier and manufacturing method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004259878A (en) * 2003-02-25 2004-09-16 Sony Corp Mounting structure of semiconductor chip, mounting substrate and method for forming electrode land
JP4396839B2 (en) * 2004-08-11 2010-01-13 日本電気株式会社 Cavity structure printed wiring board, manufacturing method thereof, and mounting structure
JP5211493B2 (en) * 2007-01-30 2013-06-12 富士通セミコンダクター株式会社 Wiring substrate and semiconductor device
JP4986738B2 (en) * 2007-06-27 2012-07-25 新光電気工業株式会社 Semiconductor package and semiconductor device using the same

Also Published As

Publication number Publication date
JP2010087018A (en) 2010-04-15

Similar Documents

Publication Publication Date Title
US8319115B2 (en) Wiring board and manufacturing method thereof
JP4769022B2 (en) Wiring board and manufacturing method thereof
US8835773B2 (en) Wiring board and method of manufacturing the same
US9247644B2 (en) Wiring board and method for manufacturing the same
JP5138277B2 (en) Wiring board and manufacturing method thereof
JP5091469B2 (en) Wiring board and manufacturing method thereof
JP2005310946A (en) Semiconductor device
JP2007123524A (en) Substrate with built-in electronic part
JP2007318098A (en) Circuit arrangement and manufacturing method thereof
JP2012054297A (en) Wiring board and method of manufacturing the same
JP5221887B2 (en) Wiring board manufacturing method
JP2012054295A (en) Wiring board and method of manufacturing the same
JP2009105301A (en) Semiconductor package and manufacturing method thereof, and semiconductor device with semiconductor package
JP5058929B2 (en) Wiring board and manufacturing method thereof
JP2010135347A (en) Wiring substrate, and method for manufacturing the same
JP2011014644A (en) Wiring board and manufacturing method thereof
JP2012209418A (en) Wiring board and method for manufacturing the same
JP2010040936A (en) Wiring board and method of manufacturing the same
JP5432800B2 (en) Wiring board manufacturing method
JP4802155B2 (en) Wiring board
JP5106351B2 (en) Wiring board and manufacturing method thereof
JP2009289868A (en) Wiring substrate and its manufacturing method
JP5565951B2 (en) Wiring board and manufacturing method thereof
KR101222820B1 (en) Semiconductor package and manufacturing method of the same
JP2010074032A (en) Wiring board and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110518

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120223

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120223

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120420

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120727

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120801

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150810

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 5058929

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350