JP4769022B2 - Wiring board and manufacturing method thereof - Google Patents

Wiring board and manufacturing method thereof Download PDF

Info

Publication number
JP4769022B2
JP4769022B2 JP2005167063A JP2005167063A JP4769022B2 JP 4769022 B2 JP4769022 B2 JP 4769022B2 JP 2005167063 A JP2005167063 A JP 2005167063A JP 2005167063 A JP2005167063 A JP 2005167063A JP 4769022 B2 JP4769022 B2 JP 4769022B2
Authority
JP
Japan
Prior art keywords
strip
wiring conductor
resist layer
conductive
shaped wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005167063A
Other languages
Japanese (ja)
Other versions
JP2006344664A (en
Inventor
孝一 大隅
Original Assignee
京セラＳｌｃテクノロジー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京セラＳｌｃテクノロジー株式会社 filed Critical 京セラＳｌｃテクノロジー株式会社
Priority to JP2005167063A priority Critical patent/JP4769022B2/en
Publication of JP2006344664A publication Critical patent/JP2006344664A/en
Application granted granted Critical
Publication of JP4769022B2 publication Critical patent/JP4769022B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

本発明は配線基板およびその製造方法に関し、より詳細には、例えばペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載するのに好適な配線基板およびその製造方法に関する。   The present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a wiring board suitable for mounting, for example, a peripheral type semiconductor integrated circuit element by flip chip connection and a manufacturing method thereof.

従来から、半導体集積回路素子として、多数の電極端子を、その一方の主面の外周に沿って配設した、いわゆるペリフェラル型の半導体集積回路素子がある。
このような半導体集積回路素子を配線基板に搭載する方法として、フリップチップ接続により接続する方法がある。フリップチップ接続とは、配線基板上に設けた半導体素子接続用の配線導体の一部を半導体集積回路素子の電極端子の配置に対応した並びに露出させ、この半導体素子接続用の配線導体の露出部と前記半導体集積回路素子の電極端子とを対向させ、これらを半田等の導電バンプを介して電気的に接続する方法である。 2. Description of the Related Art Conventionally, as a semiconductor integrated circuit element, there is a so-called peripheral type semiconductor integrated circuit element in which a large number of electrode terminals are arranged along the outer periphery of one main surface thereof.
As a method of mounting such a semiconductor integrated circuit element on a wiring board, there is a method of connecting by flip chip connection. Flip-chip connection means that a part of a wiring conductor for connecting a semiconductor element provided on a wiring board is exposed corresponding to the arrangement of electrode terminals of a semiconductor integrated circuit element, and an exposed portion of the wiring conductor for connecting a semiconductor element is exposed. And the electrode terminal of the semiconductor integrated circuit element are opposed to each other and are electrically connected through conductive bumps such as solder.

図１３は、ペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載した従来の配線基板を示す概略断面図であり、図１４は、図１３の配線基板を示す平面図である。図１３および図１４に示すように、従来の配線基板１２０は、上面から下面にかけて第一の配線導体１０２が配設された絶縁基板１０３の上下面に絶縁層１０４と第二の配線導体１０５とが交互に積層され、さらに、その最表面には保護用のソルダーレジスト層１０６が被着されている。   FIG. 13 is a schematic cross-sectional view showing a conventional wiring board on which peripheral type semiconductor integrated circuit elements are mounted by flip-chip connection, and FIG. 14 is a plan view showing the wiring board of FIG. As shown in FIGS. 13 and 14, the conventional wiring board 120 includes an insulating layer 104, a second wiring conductor 105, and a second wiring conductor 105 on the upper and lower surfaces of the insulating board 103 on which the first wiring conductor 102 is disposed from the upper surface to the lower surface. Are stacked alternately, and a protective solder resist layer 106 is deposited on the outermost surface.

絶縁基板１０３の上面から下面にかけては複数のスルーホール１０７が形成されており、絶縁基板１０３の上下面およびスルーホール１０７の内面には第一の配線導体１０２が被着され、スルーホール１０７の内部には埋め込み樹脂１０８が充填されている。絶縁層１０４には、それぞれに複数のビアホール１０９が形成されており、各絶縁層１０４の表面およびビアホール１０９の内面には、第二の配線導体１０５がそれぞれ被着形成されている。   A plurality of through holes 107 are formed from the upper surface to the lower surface of the insulating substrate 103, and the first wiring conductor 102 is attached to the upper and lower surfaces of the insulating substrate 103 and the inner surface of the through hole 107. Is filled with embedded resin 108. A plurality of via holes 109 are respectively formed in the insulating layer 104, and second wiring conductors 105 are formed on the surface of each insulating layer 104 and the inner surface of the via hole 109, respectively.

そして、複数の第二の配線導体１０５のうち、配線基板１２０の上面側における最外層の絶縁層１０４上に被着された一部が、半導体集積回路素子１０１の電極端子に導電バンプ１１０を介して電気的に接続される半導体素子接続用の帯状配線導体１０５ａを構成し、この帯状配線導体１０５ａのうち、ソルダーレジスト層１０６から露出した露出部に、半導体集積回路素子１０１の電極端子が半田や金等から成る導電バンプ１１０を介して電気的に接続される。また、配線基板１２０の下面側における最外層の絶縁層１０４上に被着された一部が、外部電気回路基板の配線導体に電気的に接続される外部接続用の配線導体１０５ｂを構成し、この外部接続用の配線導体１０５ｂのうち、ソルダーレジスト層１０６から露出した露出部に、外部電気回路基板の配線導体が半田ボール１１１を介して電気的に接続される。   A part of the plurality of second wiring conductors 105 deposited on the outermost insulating layer 104 on the upper surface side of the wiring board 120 is connected to the electrode terminals of the semiconductor integrated circuit element 101 via the conductive bumps 110. A strip-shaped wiring conductor 105a for connecting a semiconductor element electrically connected to each other is configured, and the electrode terminal of the semiconductor integrated circuit element 101 is soldered or exposed to an exposed portion of the strip-shaped wiring conductor 105a exposed from the solder resist layer 106. They are electrically connected via conductive bumps 110 made of gold or the like. In addition, a part of the lower surface side of the wiring board 120 that is deposited on the outermost insulating layer 104 constitutes a wiring conductor 105b for external connection that is electrically connected to the wiring conductor of the external electric circuit board, Of the wiring conductor 105b for external connection, the wiring conductor of the external electric circuit board is electrically connected to the exposed portion exposed from the solder resist layer 106 through the solder ball 111.

ソルダーレジスト層１０６は、最表層の第二の配線導体１０５を保護するとともに半導体素子接続用の帯状配線導体１０５ａや外部接続用の配線導体１０５ｂの露出部を画定する。このようなソルダーレジスト層１０６は、感光性を有する熱硬化性樹脂ペーストまたはフィルムを第二の配線導体１０５が形成された最外層の絶縁層１０４上に積層したのち、半導体素子接続用の帯状配線導体１０５ａや外部接続用の配線導体１０５ｂにおける露出部を露出させる開口を有するように露光および現像し、硬化させることにより形成される。このため、半導体素子接続用の帯状配線導体１０５ａにおける露出部は、ソルダーレジスト層１０６の表面から凹んで位置することになる。
なお、図１４に示すように、上面側のソルダーレジスト層１０６は、半導体素子接続用の帯状配線導体１０５ａの露出部を露出させるスリット状の開口１０６ａを有している。 The solder resist layer 106 protects the outermost second wiring conductor 105 and defines exposed portions of the strip-like wiring conductor 105a for connecting the semiconductor element and the wiring conductor 105b for external connection. Such a solder resist layer 106 is formed by laminating a photosensitive thermosetting resin paste or film on the outermost insulating layer 104 on which the second wiring conductor 105 is formed, and then forming a strip-like wiring for connecting a semiconductor element. It is formed by exposing, developing, and curing so as to have an opening that exposes an exposed portion of the conductor 105a or the wiring conductor 105b for external connection. For this reason, the exposed portion of the strip-shaped wiring conductor 105 a for connecting a semiconductor element is located recessed from the surface of the solder resist layer 106.
As shown in FIG. 14, the solder resist layer 106 on the upper surface side has a slit-shaped opening 106a that exposes an exposed portion of the strip-shaped wiring conductor 105a for connecting a semiconductor element.

そして、半導体集積回路素子１０１の電極端子と半導体素子接続用の帯状配線導体１０５ａにおける露出部とを導電バンプ１１０を介して電気的に接続した後、半導体集積回路素子１０１と配線基板１２０との間の隙間にエポキシ樹脂等の熱硬化性樹脂から成るアンダーフィルと呼ばれる充填樹脂１１２を充填し、半導体集積回路素子１０１が配線基板１２０上に実装される。   Then, after electrically connecting the electrode terminal of the semiconductor integrated circuit element 101 and the exposed portion of the strip-like wiring conductor 105 a for connecting the semiconductor element via the conductive bump 110, between the semiconductor integrated circuit element 101 and the wiring substrate 120. The gap is filled with a filling resin 112 called an underfill made of a thermosetting resin such as an epoxy resin, and the semiconductor integrated circuit element 101 is mounted on the wiring board 120.

近時、半導体集積回路素子１０１は、その高集積度化が急激に進み、半導体集積回路素子１０１における電極端子のピッチは１００μｍ以下と狭ピッチになってきており、これに伴い、半導体素子接続用の帯状配線導体１０５ａの幅も狭くなってきている（例えば５０μｍ以下）。半導体素子接続用の帯状配線導体１０５ａの幅が狭くなると、この帯状配線導体１０５ａの露出部上に形成される導電バンプ１１０も小さなものにならざるをえず、この小さな導電バンプ１１０を介して半導体集積回路素子１０１を実装した場合には、半導体集積回路素子１０１とソルダーレジスト層１０６との間の隙間が狭くなるという問題がある（例えば４５μｍ以下）。   In recent years, the semiconductor integrated circuit element 101 has rapidly increased in the degree of integration, and the pitch of electrode terminals in the semiconductor integrated circuit element 101 has become a narrow pitch of 100 μm or less. The width of the strip-shaped wiring conductor 105a is also becoming narrower (for example, 50 μm or less). When the width of the strip-shaped wiring conductor 105a for connecting the semiconductor element is narrowed, the conductive bump 110 formed on the exposed portion of the strip-shaped wiring conductor 105a must be small, and the semiconductor is interposed via the small conductive bump 110. When the integrated circuit element 101 is mounted, there is a problem that a gap between the semiconductor integrated circuit element 101 and the solder resist layer 106 becomes narrow (for example, 45 μm or less).

前記隙間が狭くなると、この隙間内への充填樹脂１１２の充填性が低下すると共に、充填された充填樹脂１１２中にボイドが発生しやすくなる。ボイドの発生は、半導体集積回路素子１０１が実装された後の配線基板１２０を外部電気回路基板に接続する際の熱や、半導体集積回路素子１０１が作動時に発生する熱、あるいは外部環境からの熱等が加えられた際に充填樹脂１１２におけるクラック発生の起点となり、このクラックにより、半導体集積回路素子１０１に対する耐湿性が低下したり、そのクラックが配線基板１２０にまで進行し、第二の配線導体１０５が断線するおそれがある。   When the gap is narrowed, the filling property of the filling resin 112 into the gap is lowered, and voids are easily generated in the filled filling resin 112. The generation of voids is caused by heat generated when connecting the wiring board 120 after the semiconductor integrated circuit element 101 is mounted to an external electric circuit board, heat generated when the semiconductor integrated circuit element 101 is operated, or heat from the external environment. Is applied to the filling resin 112, the moisture resistance of the semiconductor integrated circuit element 101 decreases, or the crack progresses to the wiring board 120, and the second wiring conductor. There is a possibility that 105 may be disconnected.

半導体集積回路素子１０１とソルダーレジスト層１０６との間の隙間を広くする方法として、半導体素子接続用の帯状配線導体１０５ａにおけるソルダーレジスト層１０６からの露出部上にめっきで導電突起を形成することにより、該導電突起とソルダーレジスト層１０６とを実質的に同一の高さにする方法がある。この方法によると、前記導電突起上に導電バンプ１１０を形成するので、導電突起が導電バンプ１１０を少量の半田等で十分な高さとするための下地部材として機能すると共に、バンプ１１０の高さに相等する隙間を確保できるようになり、充填樹脂１１２の充填性に優れ、その結果、ボイドの発生が抑制されるとともに、半導体集積回路素子１０１が実装された後の配線基板１２０を外部電気回路基板に接続する際の熱や、半導体集積回路素子１０１が作動時に発生する熱、あるいは外部環境からの熱等が加えられた際におけるクラックの発生が抑制される。   As a method of widening the gap between the semiconductor integrated circuit element 101 and the solder resist layer 106, conductive bumps are formed by plating on the exposed portions from the solder resist layer 106 in the strip-shaped wiring conductor 105a for connecting the semiconductor elements. There is a method of making the conductive protrusions and the solder resist layer 106 substantially the same height. According to this method, since the conductive bumps 110 are formed on the conductive protrusions, the conductive protrusions function as a base member for making the conductive bumps 110 sufficiently high with a small amount of solder or the like, and at the same time as the height of the bumps 110. It becomes possible to ensure a gap equivalent to each other, and the filling property of the filling resin 112 is excellent. As a result, generation of voids is suppressed, and the wiring board 120 after the semiconductor integrated circuit element 101 is mounted is connected to the external electric circuit board. The generation of cracks when heat generated when the semiconductor integrated circuit element 101 is operated, heat generated when the semiconductor integrated circuit element 101 is operated, heat from the external environment, or the like is suppressed.

半導体素子接続用の配線導体１０５ａにおけるソルダーレジスト層１０６からの露出部上に上述の導電突起を形成する方法としては、先ず配線基板１２０の上面側における最外層の絶縁層１０４の表面に半導体素子接続用の帯状配線導体１０５ａを形成した後、その上に帯状配線導体１０５ａの幅よりも若干狭い幅の第一の開口を前記露出部に対応する位置に有する第一のレジスト層を形成する。次に、前記第一の開口内に露出する半導体素子接続用の帯状配線導体１０５ａ上および第一のレジスト層の表面に電解めっき用の下地金属層を無電解めっきにより形成する。次に、前記下地金属層上に前記第一の開口に対応する第二の開口を有する第二のレジスト層を形成した後、この第二の開口内に露出する下地金属層上に電解めっきにより前記導電突起を形成する。そして、前記第二のレジスト層と、第一のレジスト層上の下地金属層と、第一のレジスト層とを除去した後、最外層の絶縁層１０４上および半導体素子接続用の帯状配線導体１０５ａの上に前記導電突起の上面を露出させるようにしてソルダーレジスト層１０６を形成する方法が採用されている（特許文献１参照）。   As a method of forming the above-described conductive protrusion on the exposed portion from the solder resist layer 106 in the wiring conductor 105a for connecting the semiconductor element, first, the semiconductor element is connected to the surface of the outermost insulating layer 104 on the upper surface side of the wiring substrate 120. After forming the band-shaped wiring conductor 105a for use, a first resist layer having a first opening slightly narrower than the width of the band-shaped wiring conductor 105a on the position corresponding to the exposed portion is formed thereon. Next, a base metal layer for electrolytic plating is formed by electroless plating on the strip-like wiring conductor 105a for connecting a semiconductor element exposed in the first opening and on the surface of the first resist layer. Next, after forming a second resist layer having a second opening corresponding to the first opening on the base metal layer, electrolytic plating is performed on the base metal layer exposed in the second opening. The conductive protrusion is formed. Then, after removing the second resist layer, the base metal layer on the first resist layer, and the first resist layer, the strip-shaped wiring conductor 105a for connecting the semiconductor element and the insulating layer 104 on the outermost layer. A method is used in which the solder resist layer 106 is formed so that the upper surface of the conductive protrusion is exposed on the surface (see Patent Document 1).

しかしながら、上述の方法で半導体素子接続用の帯状配線導体１０５ａ上に導電突起を形成する場合には、前記第一の開口および第二の開口が半導体素子接続用の帯状配線導体１０５ａの幅よりも若干狭い幅であるので、導電突起の幅が帯状配線導体１０５ａの幅よりも狭いものとなる。このため、半導体素子接続用の帯状配線導体１０５ａの幅が狭い場合には、その上に十分な幅の導電突起を設けることが困難である。   However, when the conductive protrusion is formed on the band-shaped wiring conductor 105a for connecting the semiconductor element by the above-described method, the first opening and the second opening are larger than the width of the band-shaped wiring conductor 105a for connecting the semiconductor element. Since the width is slightly narrow, the width of the conductive protrusion is narrower than the width of the strip-shaped wiring conductor 105a. For this reason, when the width | variety of the strip | belt-shaped wiring conductor 105a for a semiconductor element connection is narrow, it is difficult to provide the conductive protrusion of sufficient width | variety on it.

また、前記第一のレジスト層に第一の開口を設ける際および第二のレジスト層に第二の開口を設ける際に、これらの間に生じる位置合わせの誤差に起因して半導体素子接続用の帯状配線導体１０５ａと第一の開口との間および第一の開口と第二の開口との間に多少のずれが発生する。そして、半導体素子接続用の帯状配線導体１０５ａの幅が狭い場合には、その帯状配線導体１０５ａ上に前記導電突起を所定の幅および形状で位置精度良く設けることができず、その結果、導電突起が半導体素子接続用の帯状配線導体１０５ａから食み出てしまったり、導電突起の断面形状が歪なものとなったりして、隣接する帯状配線導体１０５ａ間での電気的な絶縁信頼性が低下したり、導電突起と導電バンプ１１０との続信頼性が低下したりするという問題がある。   Further, when the first opening is provided in the first resist layer and when the second opening is provided in the second resist layer, due to an alignment error occurring between them, the semiconductor element connection Some deviation occurs between the strip-shaped wiring conductor 105a and the first opening and between the first opening and the second opening. When the width of the band-shaped wiring conductor 105a for connecting the semiconductor element is narrow, the conductive protrusion cannot be provided on the band-shaped wiring conductor 105a with a predetermined width and shape with high positional accuracy. As a result, the conductive protrusion May protrude from the band-shaped wiring conductor 105a for connecting the semiconductor elements, or the cross-sectional shape of the conductive protrusion may be distorted, resulting in a decrease in electrical insulation reliability between the adjacent band-shaped wiring conductors 105a. And there is a problem that the continuous reliability between the conductive protrusion and the conductive bump 110 is lowered.

特開２００３−８２２８号公報JP 2003-8228 A

本発明の課題は、半導体素子接続用の帯状配線導体間の電気的絶縁信頼性に優れるとともに、導電突起と導電バンプとを信頼性高く接続することが可能であり、かつ充填樹脂の充填性に優れ、ボイドの発生が抑制された配線基板およびその製造方法を提供することである。   The problem of the present invention is that it is excellent in electrical insulation reliability between the strip-shaped wiring conductors for connecting the semiconductor elements, can connect the conductive protrusions and the conductive bumps with high reliability, and has a filling resin filling property. An object of the present invention is to provide a wiring board excellent in the generation of voids and a manufacturing method thereof.

本発明者は、上記課題を解決すべく鋭意検討を重ねた結果、所定のレジスト層を用いて最外層の絶縁層の表面に半導体素子接続用の帯状配線導体と、この帯状配線導体の表面に導電突起を形成し、ついで、前記レジスト層を除去した後に前記絶縁層および帯状配線導体の表面にソルダーレジスト層を被着する場合には、前記導電突起が半導体素子接続用の帯状配線導体の表面に十分な幅および良好な形状で確実に形成されるので、隣接する半導体素子接続用の帯状配線導体間の電気的絶縁信頼性及びこの導電突起の表面に形成される導電バンプとの接続信頼性に優れると共に、前記ソルダーレジスト層は少なくとも前記導電突起の上面を露出するので、導電突起とソルダーレジスト層との高低差が小さくなり、その結果、充填樹脂の充填性に優れ且つボイドの発生が抑制され、電極端子が狭ピッチな半導体集積回路素子を微小な導電バンプを介してフリップチップ搭載することができる配線基板が得られるという新たな知見を見出し、本発明を完成するに至った。   As a result of intensive studies to solve the above-mentioned problems, the present inventor has used a predetermined resist layer on the surface of the outermost insulating layer on the surface of the insulating layer, and on the surface of the band-shaped wiring conductor. In the case where a solder resist layer is deposited on the surface of the insulating layer and the strip-shaped wiring conductor after forming the conductive projection and then removing the resist layer, the conductive projection is the surface of the strip-shaped wiring conductor for connecting the semiconductor element. Is reliably formed with a sufficient width and good shape, so that the electrical insulation reliability between the strip-shaped wiring conductors for connecting adjacent semiconductor elements and the connection reliability with the conductive bumps formed on the surface of the conductive protrusions In addition, the solder resist layer exposes at least the upper surface of the conductive protrusion, so that the height difference between the conductive protrusion and the solder resist layer is reduced. In addition, the inventors have found a new finding that a wiring board capable of flip chip mounting a semiconductor integrated circuit element whose electrode terminals are narrow-pitch through minute conductive bumps is suppressed, and the present invention is completed. It came to do.

すなわち、本発明における配線基板およびその製造方法は、以下の構成からなる。
（１）絶縁層と配線導体とが交互に積層されており、最外層の絶縁層上に、半導体素子接続用であるとともに該半導体素子の外周辺に対して直角な方向に延びる帯状配線導体が前記半導体素子の外周辺に沿って複数並んで形成されているとともに、該帯状配線導体上の一部に、半導体素子の電極端子がフリップチップ接続されるとともに平面視で四角形状である導電突起が前記帯状配線導体の幅と一致する幅で形成されており、かつ前記最外層の絶縁層上および前記帯状配線導体上に前記導電突起の少なくとも上面を露出させるソルダーレジスト層が被着されていることを特徴とする配線基板。
（２）前記帯状配線導体および前記導電突起は、銅めっきから成ることを特徴とする前記（１）記載の配線基板。
（３）前記導電突起の前記半導体素子の外周辺に対して直角な方向に沿った長さが該導電突起の幅よりも長いことを特徴とする前記（１）または（２）に記載の配線基板。
（４）絶縁層と配線導体とを交互に積層し、最外層の絶縁層上に、半導体素子接続用であるとともに該半導体素子の外周辺に対して直角な方向に延びる帯状配線導体を前記半導体素子の外周辺に沿って複数並べて形成するとともに、該帯状配線導体上の一部に、半導体素子の電極端子がフリップチップ接続されるとともに平面視で四角形状の導電突起を設け、かつ前記最外層の絶縁層と前記帯状配線導体上に前記導電突起の少なくとも上面を露出させるソルダーレジスト層を被着する配線基板の製造方法であって、前記最外層の絶縁層上に、該絶縁層上の全面を覆う電解めっき用の下地金属層を形成する工程と、次に前記下地金属層上に前記帯状配線導体に対応する形状の第一開口を有する第一レジスト層を形成する工程と、次に前記第一開口内の前記下地金属層上に電解めっきにより前記帯状配線導体を形成する工程と、次に前記第一レジスト層および前記帯状配線導体の上に、前記第一開口を横切る第二開口を有する第二レジスト層を形成する工程と、次に前記第一開口および第二開口で囲まれた前記帯状配線導体上に電解めっきにより前記導電突起を前記第一開口で画定される幅および第二開口で画定される長さで形成する工程と、次に前記第一レジスト層および第二レジスト層を除去する工程と、次に前記帯状配線導体が形成された部分以外の前記下地金属層を除去する工程と、次に前記最外層の絶縁層および帯状配線導体の表面に前記導電突起の少なくとも上面を露出させるソルダーレジスト層を被着する工程とを含むことを特徴とする配線基板の製造方法。
（５）前記帯状配線導体および前記導電突起を、銅めっきにより形成することを特徴とする前記（４）記載の配線基板の製造方法。
（６）前記導電突起の前記長さを前記幅よりも長く形成することを特徴とする前記（４）または（５）に記載の配線基板の製造方法。
（７）前記ソルダーレジスト層を被着する工程は、ソルダーレジスト層用の樹脂で前記導電突起を含む最外層の絶縁層および帯状配線導体の全面を被覆する工程と、被覆した前記ソルダーレジスト層用の樹脂を前記導電突起の上面が露出するまで研磨する工程とを含んでいる前記（４）乃至（６）の何れかに記載の配線基板の製造方法。
（８）前記ソルダーレジスト層を被着する工程は、ソルダーレジスト層用の感光性樹脂で前記導電突起を含む最外層の絶縁層および帯状配線導体の全面を被覆する工程と、被覆した前記感光性樹脂を露光および現像処理して前記ソルダーレジスト層に前記導電突起の上面を露出させる開口を形成する工程とを含む前記（４）乃至（６）の何れかに記載の配線基板の製造方法。 That is, the wiring board and the manufacturing method thereof according to the present invention have the following configurations.
(1) Insulating layers and wiring conductors are alternately stacked, and a strip-shaped wiring conductor for connecting a semiconductor element and extending in a direction perpendicular to the outer periphery of the semiconductor element is formed on the outermost insulating layer. A plurality of the semiconductor elements are arranged along the outer periphery of the semiconductor element, and the electrode terminals of the semiconductor element are flip-chip connected to a part of the strip-shaped wiring conductor, and a conductive protrusion having a quadrangular shape in plan view. A solder resist layer that is formed to have a width that matches the width of the strip-shaped wiring conductor and that exposes at least the upper surface of the conductive protrusions is deposited on the outermost insulating layer and the strip-shaped wiring conductor. A wiring board characterized by.
(2) the strip line conductor and the conductive protrusions, the wiring substrate of the (1), wherein the formed Rukoto copper plating.
(3) The wiring according to (1) or (2), wherein the length of the conductive protrusion along a direction perpendicular to the outer periphery of the semiconductor element is longer than the width of the conductive protrusion. substrate.
(4) and a wiring conductor and an insulating layer are alternately stacked, the outermost insulating layer, wherein the strip line conductors extending in a direction perpendicular to the outer periphery of the semiconductor element with a semiconductor element connected semiconductor thereby forming side by side a plurality along the outer periphery of the element, on a part of the belt-like wiring conductors is provided a square-shaped conductive projection in plan view together with the electrode terminals of the semiconductor element is flip-chip bonded, and the outermost layer A method of manufacturing a wiring board, wherein a solder resist layer that exposes at least the upper surface of the conductive protrusion is exposed on the insulating layer and the strip-shaped wiring conductor, wherein the entire surface of the insulating layer is formed on the outermost insulating layer. A step of forming a base metal layer for electrolytic plating covering the substrate, a step of forming a first resist layer having a first opening having a shape corresponding to the strip-shaped wiring conductor on the base metal layer, and First opening A step of forming the strip-shaped wiring conductor by electrolytic plating on the base metal layer in the second, and then a second having a second opening across the first opening on the first resist layer and the strip-shaped wiring conductor Forming a resist layer, and then defining the conductive protrusion on the strip-shaped wiring conductor surrounded by the first opening and the second opening by electrolytic plating with a width and a second opening defined by the first opening; A step of forming the first resist layer and the second resist layer, and a step of removing the base metal layer other than the portion where the strip-shaped wiring conductor is formed. And a step of depositing a solder resist layer that exposes at least the upper surface of the conductive protrusion on the surface of the outermost insulating layer and the strip-shaped wiring conductor.
(5) The method for manufacturing a wiring board according to (4), wherein the strip-shaped wiring conductor and the conductive protrusion are formed by copper plating .
(6) The method for manufacturing a wiring board according to (4) or (5), wherein the length of the conductive protrusion is formed longer than the width.
(7) The step of depositing the solder resist layer includes a step of covering the entire surface of the outermost insulating layer including the conductive protrusion and the strip-shaped wiring conductor with a resin for the solder resist layer, and for the coated solder resist layer And a step of polishing the resin until the upper surface of the conductive protrusion is exposed.
(8) The step of depositing the solder resist layer includes the steps of covering the outermost insulating layer including the conductive protrusions and the entire surface of the strip-shaped wiring conductor with the photosensitive resin for the solder resist layer, and covering the photosensitive The method for manufacturing a wiring board according to any one of (4) to (6), further including a step of exposing and developing a resin to form an opening exposing the upper surface of the conductive protrusion in the solder resist layer.

本発明の配線基板によれば、最外層の絶縁層上に形成された半導体素子接続用の帯状配線導体上の一部に半導体素子の電極端子がフリップチップ接続される導電突起が前記帯状配線導体の幅と一致する幅で形成されており、かつ前記最外層の絶縁層上および前記帯状配線導体上に前記導電突起の少なくとも上面を露出させるソルダーレジスト層が被着されていることから、前記帯状配線導体上に十分な幅の導電突起が帯状配線導体からはみ出すことなく良好な断面形状で形成され、隣接する帯状配線導体間の電気的絶縁信頼性が高いとともに、導電突起の表面に形成される導電バンプとの接続信頼性に優れ、且つ導電突起とソルダーレジスト層との高低差が小さくなるので、充填樹脂の充填性に優れ且つボイドの発生が抑制され、電極端子が狭ピッチな半導体集積回路素子を微小な導電バンプを介してフリップチップ搭載することができる。   According to the wiring board of the present invention, the conductive protrusion, in which the electrode terminal of the semiconductor element is flip-chip connected to a part of the band-shaped wiring conductor for connecting the semiconductor element formed on the outermost insulating layer, has the band-shaped wiring conductor. A solder resist layer that is formed on the outermost insulating layer and on the strip-shaped wiring conductor and that exposes at least the upper surface of the conductive protrusion is deposited on the outermost insulating layer and the strip-shaped wiring conductor. Conductive protrusions of sufficient width are formed on the wiring conductor with a good cross-sectional shape without protruding from the strip-shaped wiring conductor, and the electrical insulation reliability between adjacent strip-shaped wiring conductors is high and formed on the surface of the conductive protrusion. Excellent connection reliability with the conductive bumps, and the difference in height between the conductive protrusions and the solder resist layer is reduced, so that the filling of the filling resin is excellent and the generation of voids is suppressed. It can be flip-chip mounting pitch semiconductor integrated circuit device via the fine conductive bumps.

また、本発明の配線基板の製造方法によれば、所定のレジスト層を用いて最外層の絶縁層の表面に半導体素子接続用の帯状配線導体と、この帯状配線導体の表面に導電突起を形成し、ついで、前記レジスト層を除去した後に前記絶縁層および帯状配線導体の表面にソルダーレジスト層を被着するので、前記導電突起が半導体素子接続用の帯状配線導体の表面に所定の幅および形状で確実に形成され、隣接する前記帯状配線導体間の電気的絶縁信頼性及びこの導電突起の表面に形成される導電バンプとの接続信頼性に優れると共に、導電突起とソルダーレジスト層との高低差が小さくなるので、充填樹脂の充填性に優れ且つボイドの発生が抑制され、電極端子が狭ピッチな半導体集積回路素子を微小な導電バンプを介してフリップチップ搭載することができる配線基板が得られるという効果がある。   Further, according to the method for manufacturing a wiring board of the present invention, a predetermined wiring layer is used to form a band-shaped wiring conductor for connecting a semiconductor element on the surface of the outermost insulating layer, and a conductive protrusion on the surface of the band-shaped wiring conductor. Then, after removing the resist layer, a solder resist layer is deposited on the surfaces of the insulating layer and the strip-shaped wiring conductor, so that the conductive protrusion has a predetermined width and shape on the surface of the strip-shaped wiring conductor for connecting semiconductor elements. In addition to being excellent in electrical insulation reliability between adjacent strip-shaped wiring conductors and in connection reliability with conductive bumps formed on the surface of the conductive protrusion, the height difference between the conductive protrusion and the solder resist layer is excellent. Therefore, it is possible to flip-chip a semiconductor integrated circuit element that has excellent filling properties of the filling resin, suppresses the generation of voids, and has a narrow pitch between the electrode terminals via minute conductive bumps. It wiring board has the effect of obtaining capable.

＜配線基板＞
以下、本発明にかかる配線基板について図面を参照して詳細に説明する。図１は、ペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載した本発明にかかる配線基板を示す概略断面図であり、図２は、図１の配線基板を示す平面図である。 <Wiring board>
Hereinafter, a wiring board according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing a wiring board according to the present invention in which peripheral type semiconductor integrated circuit elements are mounted by flip-chip connection, and FIG. 2 is a plan view showing the wiring board of FIG.

図１，図２に示すように、本発明にかかる配線基板１０は、上面から下面にかけて第一の配線導体２が配設された絶縁基板３の上下面に絶縁層４と第二の配線導体５とが交互に積層され、さらに、その最表面には保護用のソルダーレジスト層６が被着されて成る。   As shown in FIGS. 1 and 2, a wiring board 10 according to the present invention includes an insulating layer 4 and a second wiring conductor on the upper and lower surfaces of an insulating board 3 on which a first wiring conductor 2 is disposed from the upper surface to the lower surface. 5 are alternately laminated, and a protective solder resist layer 6 is deposited on the outermost surface.

絶縁基板３は、厚みが０．３〜１．５ｍｍ程度であり、例えばガラス繊維束を縦横に織ったガラスクロスにビスマレイミドトリアジン樹脂やエポキシ樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成り、配線基板１０のコア部材として機能する。   The insulating substrate 3 has a thickness of about 0.3 to 1.5 mm. For example, an electrically insulating material obtained by impregnating a glass cloth in which glass fiber bundles are woven vertically and horizontally with a thermosetting resin such as bismaleimide triazine resin or epoxy resin. And functions as a core member of the wiring board 10.

絶縁基板３の上面から下面にかけて直径が０．０５〜０．３ｍｍ程度の複数のスルーホール７が形成されており、絶縁基板３の上下面およびスルーホール７の内面には、第一の配線導体２が被着されている。第一の配線導体２は、絶縁基板３の上下面では、主として銅箔から形成されており、スルーホール７内面では、無電解銅めっきおよびその上の電解銅めっきから形成されている。   A plurality of through holes 7 having a diameter of about 0.05 to 0.3 mm are formed from the upper surface to the lower surface of the insulating substrate 3, and the first wiring conductor is formed on the upper and lower surfaces of the insulating substrate 3 and the inner surface of the through hole 7. 2 is attached. The first wiring conductor 2 is mainly formed of copper foil on the upper and lower surfaces of the insulating substrate 3, and is formed of electroless copper plating and electrolytic copper plating thereon on the inner surface of the through hole 7.

また、スルーホール７内部には、エポキシ樹脂等の熱硬化性樹脂から成る埋め込み樹脂８が充填されており、絶縁基板３の上下面に形成された第一の配線導体２同士がスルーホール７内の第一の配線導体２を介して電気的に接続されている。   The through hole 7 is filled with an embedded resin 8 made of a thermosetting resin such as an epoxy resin, and the first wiring conductors 2 formed on the upper and lower surfaces of the insulating substrate 3 are in the through hole 7. The first wiring conductor 2 is electrically connected.

このような絶縁基板３は、ガラス織物に未硬化の熱硬化性樹脂を含浸させたシートの上下面に第一の配線導体２用の銅箔を貼着した後、そのシートを熱硬化させ、これに上面から下面にかけてスルーホール７用のドリル加工を施すことにより製作される。   Such an insulating substrate 3 is formed by sticking a copper foil for the first wiring conductor 2 on the upper and lower surfaces of a sheet of glass fabric impregnated with an uncured thermosetting resin, and then thermally curing the sheet. This is manufactured by drilling through holes 7 from the upper surface to the lower surface.

第一の配線導体２は、絶縁基板３用のシートの上下全面に、厚みが３〜５０μｍ程度の銅箔を上述のように貼着しておくとともに、これらの銅箔および絶縁基板３にスルーホール７を穿孔した後、このスルーホール7の内面および銅箔表面に無電解銅めっきおよび電解銅めっきを順次施し、次にスルーホール７内を埋め込み樹脂８で充填した後、この上下面の銅箔および銅めっきをフォトリソグラフィ技術を用いて所定のパターンにエッチング加工することにより絶縁基板３の上下面およびスルーホール７の内面に形成される。   The first wiring conductor 2 has a copper foil having a thickness of about 3 to 50 μm adhered to the entire upper and lower surfaces of the sheet for the insulating substrate 3 as described above, and through the copper foil and the insulating substrate 3. After the hole 7 is drilled, the inner surface of the through hole 7 and the surface of the copper foil are sequentially subjected to electroless copper plating and electrolytic copper plating, and the inside of the through hole 7 is filled with the embedded resin 8. The foil and the copper plating are etched into a predetermined pattern using a photolithography technique to form the upper and lower surfaces of the insulating substrate 3 and the inner surface of the through hole 7.

埋め込み樹脂８は、スルーホール７を塞ぐことによりスルーホール７の直上および直下に絶縁層４を形成可能とするためのものであり、未硬化のペースト状の熱硬化性樹脂をスルーホール７内にスクリーン印刷法により充填し、これを熱硬化させた後、その上下面を略平坦に研磨することにより形成される。   The embedded resin 8 is used to form the insulating layer 4 immediately above and below the through hole 7 by closing the through hole 7, and an uncured paste-like thermosetting resin is placed in the through hole 7. After filling with a screen printing method and thermosetting it, the upper and lower surfaces thereof are polished to be substantially flat.

絶縁基板３の上下面に積層された絶縁層４は、それぞれの厚みが２０〜６０μｍ程度であり、絶縁基板３と同様にガラスクロスに熱硬化性樹脂を含浸させた電気絶縁材料や、あるいはエポキシ樹脂等の熱硬化性樹脂に酸化ケイ素等の無機フィラーを分散させた電気絶縁材料から成る。また、各絶縁層４には、直径が３０〜１００μｍ程度の複数のビアホール９が形成されている。   The insulating layers 4 laminated on the upper and lower surfaces of the insulating substrate 3 each have a thickness of about 20 to 60 μm. Similarly to the insulating substrate 3, an electric insulating material in which a glass cloth is impregnated with a thermosetting resin, or an epoxy It consists of an electrically insulating material in which an inorganic filler such as silicon oxide is dispersed in a thermosetting resin such as a resin. Each insulating layer 4 is formed with a plurality of via holes 9 having a diameter of about 30 to 100 μm.

各絶縁層４の表面およびビアホール９内面には、無電解銅めっきおよびその上の電解銅めっきから成る第二の配線導体５が被着形成されている。そして、絶縁層４を挟んで上層に位置する配線導体５と下層に位置する配線導体５とをビアホール９内の配線導体５を介して電気的に接続することにより高密度配線が立体的に形成される。   A second wiring conductor 5 made of electroless copper plating and electrolytic copper plating thereon is deposited on the surface of each insulating layer 4 and the inner surface of the via hole 9. Then, the wiring conductor 5 located in the upper layer and the wiring conductor 5 located in the lower layer are electrically connected via the wiring conductor 5 in the via hole 9 with the insulating layer 4 interposed therebetween, thereby forming a high-density wiring in three dimensions. Is done.

複数の第二の配線導体５のうち、配線基板１０の上面側における最外層の絶縁層４上に被着された一部が半導体集積回路素子１０１の電極と半田等の導電バンプ１１０および後述する導電突起１２を介して電気的に接続される半導体素子接続用の帯状配線導体５ａを形成しており、配線基板１０の下面側における最外層の絶縁層４上に被着された一部が外部電気回路基板の配線導体に半田ボール１１１を介して電気的に接続される外部接続用の配線導体５ｂを形成している。   Among the plurality of second wiring conductors 5, a part of the second wiring conductor 5 deposited on the outermost insulating layer 4 on the upper surface side of the wiring substrate 10 is electrically conductive bumps 110 such as electrodes of the semiconductor integrated circuit element 101 and solder and will be described later. A band-like wiring conductor 5a for connecting a semiconductor element electrically connected via the conductive protrusion 12 is formed, and a part of the belt-shaped wiring conductor 5a attached to the outermost insulating layer 4 on the lower surface side of the wiring board 10 is externally connected. An external connection wiring conductor 5b that is electrically connected to the wiring conductor of the electric circuit board via the solder ball 111 is formed.

このような第二の配線導体５は、セミアディティブ法といわれる方法により形成される。セミアディティブ法は、例えば、ビアホール９が形成された絶縁層４の表面に電解めっき用の下地金属層を無電解銅めっきにより形成し、その上に第二の配線導体５に対応した開口を有するめっきレジスト層を形成し、次に、下地金属層を給電用の電極として開口から露出する下地金属層上に電解銅めっきを施し第二の配線導体５を形成し、めっきレジストを剥離した後、露出する下地金属層をエッチング除去することによって各第二の配線導体５を電気的に独立させる方法である。   Such a second wiring conductor 5 is formed by a method called a semi-additive method. In the semi-additive method, for example, a base metal layer for electrolytic plating is formed on the surface of the insulating layer 4 in which the via hole 9 is formed by electroless copper plating, and an opening corresponding to the second wiring conductor 5 is formed thereon. After forming the plating resist layer, and then applying the electrolytic copper plating on the base metal layer exposed from the opening as the power supply electrode as the base metal layer to form the second wiring conductor 5 and peeling the plating resist, This is a method in which each second wiring conductor 5 is electrically independent by etching away the exposed base metal layer.

半導体素子接続用の帯状配線導体５ａは、図２に示すように、半導体集積回路素子１０１の外周部に対応する位置を半導体集積回路素子１０１の外周辺に対して直角な方向に延びるようにして所定のピッチで複数並んで設けられており、その上には半導体集積回路素子１０１の電極端子に対応する位置に、導電バンプ１１０と接続される導電突起１２が帯状配線導体５ａの幅と一致する幅で形成されている。   As shown in FIG. 2, the strip-shaped wiring conductor 5a for connecting the semiconductor element extends at a position corresponding to the outer peripheral portion of the semiconductor integrated circuit element 101 in a direction perpendicular to the outer periphery of the semiconductor integrated circuit element 101. A plurality of conductive projections 12 are provided at a predetermined pitch, and conductive projections 12 connected to the conductive bumps 110 coincide with the width of the strip-shaped wiring conductor 5a at positions corresponding to the electrode terminals of the semiconductor integrated circuit element 101. It is formed with a width.

導電突起１２は、帯状配線導体５ａの幅と一致する幅で形成されていることから、帯状配線導体５ａからはみ出ることがないとともに導電バンプ１１０と接続するための十分な幅を確保することができる。したがって、本発明の配線基板１０は、隣接する帯状配線導体５ａ間の電気的絶縁信頼性に優れるとともに導電突起１２と導電バンプ１１０との接続信頼性に優れる。   Since the conductive protrusions 12 are formed with a width that matches the width of the strip-shaped wiring conductor 5a, the conductive protrusion 12 does not protrude from the strip-shaped wiring conductor 5a and can secure a sufficient width for connection to the conductive bump 110. . Therefore, the wiring board 10 of the present invention is excellent in the electrical insulation reliability between the adjacent strip-shaped wiring conductors 5a and is excellent in the connection reliability between the conductive protrusions 12 and the conductive bumps 110.

また、導電突起１２は、その長さが前記幅よりも例えば５０μｍ以上長く形成されている。このように、導電突起１２の長さが前記幅よりも長く形成されることにより、例えば導電突起１２の形成位置が帯状配線導体５ａの長さ方向に多少ずれた場合であっても、半導体集積回路素子１０１の電極端子と導電突起１２との位置が合い、両者を導電バンプ１１０を介して正確に接続することができる。   In addition, the length of the conductive protrusion 12 is longer than the width by, for example, 50 μm or more. As described above, since the length of the conductive protrusion 12 is formed to be longer than the above width, for example, even when the formation position of the conductive protrusion 12 is slightly shifted in the length direction of the strip-shaped wiring conductor 5a, The electrode terminals of the circuit element 101 and the conductive protrusions 12 are aligned, and both can be accurately connected via the conductive bumps 110.

さらに、最外層の絶縁層４およびその上の第二の配線導体５上には、ソルダーレジスト層６が被着されている。該ソルダーレジスト層６は、最外層の第二の配線導体５を熱や外部環境から保護するための保護膜であり、上面側のソルダーレジスト層６は、導電突起１２の上面を露出させるようにして、また下面側のソルダーレジスト層６は、外部接続用の配線導体５ｂを露出させるようにして被着されている。   Further, a solder resist layer 6 is deposited on the outermost insulating layer 4 and the second wiring conductor 5 thereon. The solder resist layer 6 is a protective film for protecting the outermost second wiring conductor 5 from heat and the external environment. The solder resist layer 6 on the upper surface side exposes the upper surface of the conductive protrusion 12. In addition, the solder resist layer 6 on the lower surface side is applied so as to expose the wiring conductor 5b for external connection.

そして、本発明の配線基板１０においては、導電突起１２の上面とソルダーレジスト層６の上面とが実質的に同じ高さとなっている。これにより、導電突起１２の上に導電バンプ１１０を介して半導体集積回路素子１０１の電極端子を接続する際には、ソルダーレジスト層６と半導体集積回路素子１０１との間に導電バンプ１１０の高さに相当する隙間が確保され、その隙間に充填樹脂１１２を充填性良く、かつボイドを発生させることなく充填することができる。なお、導電突起１２の上面とソルダーレジスト層６の上面とは、完全に同一の高さである必要はなく、両者間に５μｍ以下の高低差があってもよい。   In the wiring board 10 of the present invention, the upper surface of the conductive protrusion 12 and the upper surface of the solder resist layer 6 are substantially the same height. As a result, when the electrode terminal of the semiconductor integrated circuit element 101 is connected to the conductive protrusion 12 via the conductive bump 110, the height of the conductive bump 110 is between the solder resist layer 6 and the semiconductor integrated circuit element 101. The filling resin 112 can be filled with good filling properties and without generating voids. Note that the upper surface of the conductive protrusion 12 and the upper surface of the solder resist layer 6 do not have to be completely the same height, and there may be a height difference of 5 μm or less between them.

＜配線基板の製造方法＞
次に本発明の配線基板の製造方法に従い、上述の帯状配線導体５ａ、導電突起１２およびソルダーレジスト層６を形成する方法について図３〜図１２を基にして説明する。
（第一の製造方法）
図３〜図５は、本発明にかかる配線基板の第一の製造方法を示す概略説明図であり、図６〜図８は、その工程説明図である。これらのうち、図６，図７は、半導体素子接続用の帯状配線導体およびその上の導電突起の形成方法を示す工程説明図であり、図８は、ソルダーレジスト層の被着方法を示す工程説明図である。 <Manufacturing method of wiring board>
Next, a method for forming the above-described strip-like wiring conductor 5a, conductive protrusion 12 and solder resist layer 6 according to the method for manufacturing a wiring board of the present invention will be described with reference to FIGS.
(First manufacturing method)
3 to 5 are schematic explanatory views showing a first method of manufacturing a wiring board according to the present invention, and FIGS. 6 to 8 are explanatory views of the steps. Among these, FIG. 6 and FIG. 7 are process explanatory views showing a method for forming a strip-like wiring conductor for connecting a semiconductor element and a conductive protrusion thereon, and FIG. 8 is a process showing a method for depositing a solder resist layer. It is explanatory drawing.

まず、図３（ａ），（ｂ）および図６（ａ），（ｂ）に示すように、上面側における最外層の絶縁層４の表面に、電解めっき用の下地金属層５１を無電解めっきにより被着形成する。下地金属層５１を形成する無電解めっきとしては、無電解銅めっきが好ましい。   First, as shown in FIGS. 3A and 3B and FIGS. 6A and 6B, the base metal layer 51 for electroplating is electrolessly formed on the surface of the outermost insulating layer 4 on the upper surface side. Deposited by plating. As the electroless plating for forming the base metal layer 51, electroless copper plating is preferable.

ついで、図３（ｃ），図６（ｃ）に示すように、下地金属層５１の表面に、第一レジスト層Ｒ１を形成する。第一レジスト層Ｒ１は、帯状配線導体５ａに対応する形状の第一開口Ａ１を有しており、光感光性アルカリ現像型ドライフィルムレジストを下地金属層５１上に貼着するとともに、それにフォトリソグラフィ技術を用いて露光および現像を行なうことにより帯状配線導体５ａに対応する形状の第一開口Ａ１を有するパターンに形成される。また、第一レジスト層Ｒ１の厚みは、帯状配線導体５ａおよびその上に形成される導電突起１２の合計厚みよりも若干厚い厚みであるのがよい。   Next, as shown in FIGS. 3C and 6C, a first resist layer R <b> 1 is formed on the surface of the base metal layer 51. The first resist layer R1 has a first opening A1 having a shape corresponding to the strip-shaped wiring conductor 5a, and a photo-sensitive alkaline developing dry film resist is attached on the base metal layer 51 and photolithography is applied thereto. By performing exposure and development using a technique, a pattern having a first opening A1 having a shape corresponding to the strip-shaped wiring conductor 5a is formed. Further, the thickness of the first resist layer R1 is preferably slightly thicker than the total thickness of the strip-like wiring conductor 5a and the conductive protrusions 12 formed thereon.

ついで、図４（ｄ），図６（ｄ）に示すように、第一レジスト層Ｒ１の第一開口Ａ１内に露出する下地金属層５１上に電解めっきにより半導体素子接続用の帯状配線導体５ａを被着形成する。帯状配線導体５ａを形成するための電解めっきとしては、電解銅めっきが好ましい。ここで、帯状配線導体５ａの厚みは、第一レジスト層Ｒ１の厚みより薄い。具体的には、帯状配線導体５ａの厚みは、８〜２０μｍ、好ましくは１０〜１５μｍであるのがよい。   Next, as shown in FIGS. 4D and 6D, a strip-shaped wiring conductor 5a for connecting a semiconductor element is formed on the underlying metal layer 51 exposed in the first opening A1 of the first resist layer R1 by electrolytic plating. Is formed. As electrolytic plating for forming the strip-shaped wiring conductor 5a, electrolytic copper plating is preferable. Here, the thickness of the strip-shaped wiring conductor 5a is smaller than the thickness of the first resist layer R1. Specifically, the thickness of the strip-shaped wiring conductor 5a is 8 to 20 μm, preferably 10 to 15 μm.

ついで、図４（ｅ），図７（ｅ）に示すように、第一レジスト層Ｒ１および帯状配線導体５ａの表面に第二レジスト層Ｒ２を形成する。第二レジスト層Ｒ２は、導電突起１２が形成される位置に導電突起１２の長さに対応した幅で第一開口Ａ１を真横に横切る第二開口Ａ２を有しており、光感光性アルカリ現像型ドライフィルムレジストを第一レジスト層Ｒ１および帯状配線導体５ａ上に貼着するとともに、それにフォトリソグラフィ技術を用いて露光および現像を行なうことにより第二開口Ａ２を有するパターンに形成される。なお、第二レジスト層Ｒ２の厚みは第一レジスト層Ｒ２の厚み以上であることが好ましい。   Next, as shown in FIGS. 4E and 7E, a second resist layer R2 is formed on the surfaces of the first resist layer R1 and the strip-like wiring conductor 5a. The second resist layer R2 has a second opening A2 across the first opening A1 with a width corresponding to the length of the conductive protrusion 12 at a position where the conductive protrusion 12 is formed. A mold dry film resist is stuck on the first resist layer R1 and the strip-like wiring conductor 5a, and is exposed to light and developed using a photolithography technique to form a pattern having a second opening A2. In addition, it is preferable that the thickness of 2nd resist layer R2 is more than the thickness of 1st resist layer R2.

ついで、図４（ｆ），図７（ｆ）に示すように、第一開口Ａ１および第二開口Ａ２で囲まれた帯状配線導体５ａ上に、導電突起１２を電解めっきにより形成する。導電突起１２を形成するための電解めっきとしては、電解銅めっきが好ましい。なお、導電突起１２の高さは第一レジスト層Ｒ１の上面よりも若干低い位置とするのが好ましい。   Next, as shown in FIGS. 4 (f) and 7 (f), conductive protrusions 12 are formed on the strip-shaped wiring conductor 5a surrounded by the first opening A1 and the second opening A2 by electrolytic plating. As the electrolytic plating for forming the conductive protrusions 12, electrolytic copper plating is preferable. In addition, it is preferable that the height of the conductive protrusions 12 is slightly lower than the upper surface of the first resist layer R1.

このとき、導電突起１２は、第一開口Ａ１および第二開口Ａ２で囲まれた帯状配線導体５ａ上に形成されるので、その幅が第一開口Ａ１で画定される幅、すなわち帯状配線導体５ａの幅と一致する幅で形成されるとともに、その長さが第二開口Ａ２で画定される幅で形成される。その結果、導電突起１２が帯状配線導体５ａからはみ出すことがないとともに、導電バンプ１１０と接続するために十分な幅が確保され、かつその断面形状が歪になることもない。したがって、導電バンプ１１０との接続信頼性に優れる導電突起１２を形成することができる。   At this time, since the conductive protrusion 12 is formed on the strip-shaped wiring conductor 5a surrounded by the first opening A1 and the second opening A2, the width is defined by the first opening A1, that is, the strip-shaped wiring conductor 5a. And a length that is the width defined by the second opening A2. As a result, the conductive protrusion 12 does not protrude from the strip-shaped wiring conductor 5a, and a sufficient width is secured for connection to the conductive bump 110, and the cross-sectional shape thereof is not distorted. Therefore, the conductive protrusion 12 having excellent connection reliability with the conductive bump 110 can be formed.

なお、第二開口Ａ２の幅を、第一開口Ａ１の幅よりも例えば５０μｍ以上広い幅で形成しておくと、その分、導電突起１２の長さが長く形成されることになり、第二レジスト層Ｒ２を形成する際の位置合わせの誤差に起因して第二開口Ａ２の位置が帯状配線導体５ａの長さ方向に例えば２５μｍ程度ずれたとしても、導電突起１２上に半導体集積回路素子１０１の電極端子と正確に対向する領域を確保することができるので、半導体集積回路素子１０１の電極端子と導電突起１２とを導電バンプ１１０を介して正確に接続することができる。したがって、第二開口Ａ２の幅は、第一開口Ａ１の幅よりも、例えば５０μｍ以上広くしておくことが好ましい。   If the width of the second opening A2 is formed to be, for example, 50 μm or more wider than the width of the first opening A1, the length of the conductive protrusion 12 is increased accordingly, Even if the position of the second opening A2 is shifted by, for example, about 25 μm in the length direction of the strip-shaped wiring conductor 5a due to an alignment error when forming the resist layer R2, the semiconductor integrated circuit element 101 is formed on the conductive protrusion 12. Therefore, the electrode terminal of the semiconductor integrated circuit element 101 and the conductive protrusion 12 can be accurately connected via the conductive bump 110. Therefore, it is preferable that the width of the second opening A2 is, for example, 50 μm or more wider than the width of the first opening A1.

ところで、第二開口Ａ２は、第一開口Ａ１を横切るように形成されていることから、第二レジスト層Ｒ２を形成する際の位置合わせの誤差に起因して、第二開口Ａ２の位置が帯状配線導体５ａの幅方向にずれたとしても、帯状配線導体５ａの露出幅が変わることはなく、したがって形成される導電突起１２の幅に影響を与えることはない。   By the way, since the second opening A2 is formed so as to cross the first opening A1, the position of the second opening A2 is strip-shaped due to an alignment error when forming the second resist layer R2. Even if the wiring conductor 5a is displaced in the width direction, the exposed width of the strip-shaped wiring conductor 5a does not change, and therefore does not affect the width of the conductive protrusion 12 to be formed.

導電突起１２を形成後、図４（ｇ），図７（ｇ）に示すように、第一レジスト層Ｒ１および第二レジスト層Ｒ２を除去する。前記第一レジスト層Ｒ１および第二レジスト層Ｒ２の除去は、例えば水酸化ナトリウム水溶液への浸漬により行なうことができる。   After forming the conductive protrusions 12, the first resist layer R1 and the second resist layer R2 are removed as shown in FIGS. 4 (g) and 7 (g). The removal of the first resist layer R1 and the second resist layer R2 can be performed, for example, by immersion in an aqueous sodium hydroxide solution.

次に、図５（ｈ）、図７（ｈ）および図８（ａ）に示すように、帯状配線導体５ａが形成された部分以外の下地金属層５１を除去する。これにより、隣接する帯状配線導体５ａ間が電気的に独立することになる。このとき、帯状配線導体５ａの上に形成された導電突起１２は、その幅が帯状配線導体５ａと一致する幅で形成されており、帯状配線導体５ａからはみ出すことはないので、隣接する帯状配線導体５ａ間の電気的な絶縁が良好に保たれる。なお、帯状配線導体５ａが形成された部分以外の下地金属層５１を除去するには、前記第一レジスト層Ｒ１および第二レジスト層Ｒ２を除去した後に露出する下地金属層５１を例えば塩化第二銅を含有するエッチング液によりエッチング除去する方法が採用可能である。   Next, as shown in FIGS. 5 (h), 7 (h) and 8 (a), the base metal layer 51 other than the portion where the strip-like wiring conductor 5a is formed is removed. As a result, the adjacent strip-shaped wiring conductors 5a are electrically independent. At this time, the conductive protrusions 12 formed on the strip-shaped wiring conductor 5a are formed with a width that matches the strip-shaped wiring conductor 5a and do not protrude from the strip-shaped wiring conductor 5a. The electrical insulation between the conductors 5a is kept good. In order to remove the base metal layer 51 other than the portion where the strip-shaped wiring conductor 5a is formed, the base metal layer 51 exposed after removing the first resist layer R1 and the second resist layer R2 is, for example, second chloride. A method of etching away with an etching solution containing copper can be employed.

ついで、図５（ｉ），図８（ｂ）に示すように、ソルダーレジスト層用の樹脂６ａで最外層の絶縁層４、前記帯状配線導体５ａおよび導電突起１２を被覆する。ソルダーレジスト層用の樹脂６ａとしては、配線基板の表面を保護するソルダーレジスト層として機能する各種の公知の樹脂が採用可能であり、具体的には、例えばエポキシ樹脂等にシリカやタルク等の無機物粉末フィラーを３０〜７０質量％程度分散させた絶縁材料から成る熱硬化性樹脂が好ましく、該樹脂を被覆後、硬化させるのがよい。   Next, as shown in FIGS. 5 (i) and 8 (b), the outermost insulating layer 4, the strip-shaped wiring conductor 5 a and the conductive protrusions 12 are covered with a resin 6 a for a solder resist layer. As the resin 6a for the solder resist layer, various known resins that function as a solder resist layer that protects the surface of the wiring board can be used. Specifically, for example, an epoxy resin or the like inorganic material such as silica or talc. A thermosetting resin made of an insulating material in which about 30 to 70% by mass of a powder filler is dispersed is preferable, and it is preferable to cure the resin after coating the resin.

ソルダーレジスト層用の樹脂６ａで被覆した後、図５（ｊ），図８（ｃ）に示すように、該ソルダーレジスト層用の樹脂６ａを前記導電突起１２の上面が露出するまで研磨してソルダーレジスト層６を形成し、導電突起１２の上面がソルダーレジスト層６の上面と実質的に同じ平面で露出する配線基板１０が得られる。なお、前記研磨は各種の公知の機械的研磨方法やレーザスクライブ法が採用可能であり、ソルダーレジスト層６の厚みとしては、ソルダーレジスト層６の上面と導電突起１２の上面との高低差が５μｍ以下となる厚みが好ましい。   After coating with the solder resist layer resin 6a, as shown in FIGS. 5 (j) and 8 (c), the solder resist layer resin 6a is polished until the upper surface of the conductive protrusion 12 is exposed. The solder resist layer 6 is formed, and the wiring substrate 10 is obtained in which the upper surface of the conductive protrusion 12 is exposed in substantially the same plane as the upper surface of the solder resist layer 6. Various known mechanical polishing methods and laser scribing methods can be used for the polishing. The thickness of the solder resist layer 6 is 5 μm in height difference between the upper surface of the solder resist layer 6 and the upper surface of the conductive protrusion 12. The following thickness is preferred.

ソルダーレジスト層６が被着形成された配線基板１０は、図１に示すように、ペリフェラル型の半導体集積回路素子１０１の電極端子（ピッチが１００μｍ以下）と半導体素子接続用の帯状配線導体５ａ上に形成された導電突起１２とを導電バンプ１１０を介して電気的に接続（フリップチップ接続）することにより、半導体集積回路素子１０１の電極端子と帯状配線導体５ａとが電気的に接続される。ここで、半導体素子接続用の帯状配線導体５ａ上に導電突起１２が帯状配線導体５ａの幅と一致する幅で確実に被着形成されているので、導電突起１２は導電バンプ１１０との接続のために十分な幅が確保されているとともに断面形状に歪みもなく、導電バンプ１１０との接続信頼性に優れたものとなる。   As shown in FIG. 1, the wiring substrate 10 on which the solder resist layer 6 is deposited is formed on the electrode terminals (pitch is 100 μm or less) of the peripheral type semiconductor integrated circuit element 101 and the band-shaped wiring conductor 5a for connecting the semiconductor elements. By electrically connecting (flip chip connection) the conductive protrusions 12 formed on the conductive bumps 110, the electrode terminals of the semiconductor integrated circuit element 101 and the strip-shaped wiring conductor 5a are electrically connected. Here, since the conductive protrusions 12 are reliably formed on the band-shaped wiring conductors 5a for connecting the semiconductor elements with a width that matches the width of the band-shaped wiring conductors 5a, the conductive protrusions 12 are connected to the conductive bumps 110. Therefore, a sufficient width is ensured, the cross-sectional shape is not distorted, and the connection reliability with the conductive bump 110 is excellent.

ついで、半導体集積回路素子１０１と配線基板１０との間の隙間に充填樹脂１１２を充填し、半導体集積回路素子１０１が配線基板１０上に実装される。ここで、導電突起１２の上面およびソルダーレジスト層６の上面は実質的に同じ高さとなるので、半導体集積回路素子１０１と配線基板１０との間に導電バンプ１１０の高さに相等する隙間を確保できるようになり、充填樹脂１１２の充填性に優れ、その結果、ボイドの発生が抑制される。   Next, the gap between the semiconductor integrated circuit element 101 and the wiring substrate 10 is filled with the filling resin 112, and the semiconductor integrated circuit element 101 is mounted on the wiring substrate 10. Here, since the upper surface of the conductive protrusion 12 and the upper surface of the solder resist layer 6 have substantially the same height, a gap equivalent to the height of the conductive bump 110 is ensured between the semiconductor integrated circuit element 101 and the wiring substrate 10. As a result, the filling property of the filling resin 112 is excellent, and as a result, generation of voids is suppressed.

なお、上記した方法では、第二開口Ａ２を、第一開口Ａ１と直交する向きに形成したが、本発明にかかる配線基板の製造方法はこれに限定されるものではなく、導電突起１２の形状に合わせて、任意の向きに第二開口Ａ２を形成すればよい。また、一つの帯状配線導体５ａの表面には、一つの導電突起１２が形成されているが、複数の第一開口Ａ１および第二開口Ａ２を組み合わせることにより、一つの帯状配線導体５ａの表面に複数の導電突起１２が被着形成されていてもよい。   In the above-described method, the second opening A2 is formed in the direction orthogonal to the first opening A1, but the method of manufacturing the wiring board according to the present invention is not limited to this, and the shape of the conductive protrusion 12 The second opening A2 may be formed in any direction according to the above. Further, one conductive protrusion 12 is formed on the surface of one strip-shaped wiring conductor 5a. By combining a plurality of first openings A1 and second openings A2, the surface of one strip-shaped wiring conductor 5a is formed. A plurality of conductive protrusions 12 may be deposited.

（第二の製造方法）
図９〜図１１は、本発明にかかる配線基板の第二の製造方法を示す概略説明図であり、図１２は、その工程説明図である。なお、図９〜図１２においては、前述した図１〜８の構成と同一または同等な部分には同一の符号を付して説明は省略する。さらに、図９〜図１１（ｈ）および図１２（ａ）は、図３〜図５（ｈ）および図８（ａ）と同じであるので、これらの工程の説明は省略する。 (Second manufacturing method)
9 to 11 are schematic explanatory views showing a second method for manufacturing a wiring board according to the present invention, and FIG. 12 is a process explanatory view thereof. 9 to 12, the same reference numerals are given to the same or equivalent parts as in the above-described configurations of FIGS. 1 to 8, and description thereof is omitted. Furthermore, since FIGS. 9 to 11 (h) and FIG. 12 (a) are the same as FIGS. 3 to 5 (h) and FIG. 8 (a), description of these steps is omitted.

まず、図９〜図１１（ｈ）に示す手順にて、半導体素子接続用の帯状配線導体５ａ上に導電突起１２を形成する。ついで、図１１（ｉ），図１２（ｂ）に示すように、ソルダーレジスト層用の感光性樹脂６ｂで最外層の絶縁層４、帯状配線導体５ａおよび導電突起１２を被覆する。感光性樹脂６ｂによる被覆方法としては、感光性樹脂ペーストを塗布した後に乾燥する方法や感光性樹脂フィルムを貼着する方が採用される。   First, the conductive protrusions 12 are formed on the strip-shaped wiring conductor 5a for connecting the semiconductor elements by the procedure shown in FIGS. Next, as shown in FIGS. 11 (i) and 12 (b), the outermost insulating layer 4, the strip-shaped wiring conductor 5a, and the conductive protrusions 12 are covered with the photosensitive resin 6b for the solder resist layer. As a coating method with the photosensitive resin 6b, a method of drying after applying a photosensitive resin paste or a method of sticking a photosensitive resin film is employed.

ここで、ソルダーレジスト層用の感光性樹脂６ｂの厚みは、帯状配線導体５ａおよび導電突起１２の合計の厚みとほぼ同じ厚みであるのが好ましく、特に、若干薄い方が好ましい。ほぼ同じ厚みで被覆する方法としては、例えば感光性樹脂ペーストを塗布する場合であれば、感光性樹脂ペーストを塗布する際の感光性樹脂ペーストの量および粘度を制御する方法が採用され、感光性樹脂フィルムを貼着する場合であれば、感光性樹脂フィルムの貼着時にフィルムが軟化流動する程度に熱を加えながらプレスして厚みを整えることで、ほぼ同じ厚みで被覆することができる。この場合には、導電突起１２の上面に感光性樹脂６ｂの薄い膜が被覆されるが、同じ厚みとなるように、ソルダーレジスト層用の感光性樹脂６ｂを研磨してもよい。ソルダーレジスト層用の感光性樹脂６ｂとしては、例えばアクリル変性エポキシ樹脂等を含有する感光性樹脂等が挙げられる。   Here, the thickness of the photosensitive resin 6b for the solder resist layer is preferably substantially the same as the total thickness of the strip-shaped wiring conductor 5a and the conductive protrusions 12, and is particularly preferably slightly thinner. As a method of coating with substantially the same thickness, for example, in the case of applying a photosensitive resin paste, a method of controlling the amount and viscosity of the photosensitive resin paste when applying the photosensitive resin paste is adopted. In the case of sticking a resin film, it can be coated with substantially the same thickness by pressing while adjusting the thickness while applying heat to such an extent that the film softens and flows when the photosensitive resin film is stuck. In this case, the upper surface of the conductive protrusion 12 is coated with a thin film of the photosensitive resin 6b. However, the photosensitive resin 6b for the solder resist layer may be polished so as to have the same thickness. Examples of the photosensitive resin 6b for the solder resist layer include a photosensitive resin containing an acrylic-modified epoxy resin.

そして、図１１（ｊ），図１２（ｃ）に示すように、導電突起１２の上面が露出するように、導電突起１２上およびその周辺の感光性樹脂６ｂの一部をフォトリソグラフィ技術を用いて露光・現像処理して開口し、該開口部分を除く最外層の絶縁層４および帯状配線導体５ａの表面がソルダーレジスト層６で被覆された配線基板１０が得られる。この構成であっても、導電突起１２と導電バンプ１１０との接続信頼性に優れるとともに、充填樹脂の充填性に優れ且つボイドの発生が抑制された配線基板とすることができる。   Then, as shown in FIGS. 11 (j) and 12 (c), a part of the photosensitive resin 6b on and around the conductive protrusion 12 is photolithography technique so that the upper surface of the conductive protrusion 12 is exposed. Thus, an opening is obtained by exposure and development, and the wiring substrate 10 in which the outermost insulating layer 4 and the surface of the strip-like wiring conductor 5a excluding the opening are covered with the solder resist layer 6 is obtained. Even with this configuration, it is possible to provide a wiring board that has excellent connection reliability between the conductive protrusions 12 and the conductive bumps 110, is excellent in filling resin filling properties, and suppresses the generation of voids.

なお、本発明は、上述の実施の形態例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、例えば上述の実施形態例では、半導体素子接続用の帯状配線導体５ａおよび導電突起１２を配線基板１０の上面側に設けた場合を例に示したが、半導体素子接続用の帯状配線導体５ａおよび導電突起１２を配線基板１０の下面側あるいは両面に設けてもよい。   The present invention is not limited to the above-described embodiment, and various modifications are possible within the scope not departing from the gist of the present invention. For example, in the above-described embodiment, semiconductor element connection In the above example, the band-like wiring conductor 5a and the conductive protrusion 12 are provided on the upper surface side of the wiring board 10. However, the band-like wiring conductor 5a and the conductive protrusion 12 for connecting the semiconductor elements are arranged on the lower surface side or both surfaces of the wiring board 10. May be provided.

また、上述の実施の形態例では、上面側におけるソルダーレジスト層６は、最外層の絶縁層４および帯状配線導体５ａの上を、導電突起１２が形成された領域を除く略全面にわたり被覆していたが、上面側におけるソルダーレジスト層６は、半導体集積回路素子１０１の下面中央部に対向する領域において最外層の絶縁層４の一部を露出させる開口を有していてもよい。このような開口を設けることにより半導体集積回路素子１０１下面中央部と配線基板１０との間に形成される隙間をさらに大きなものとすることができる。   In the above-described embodiment, the solder resist layer 6 on the upper surface side covers the outermost insulating layer 4 and the strip-shaped wiring conductor 5a over substantially the entire surface except the region where the conductive protrusions 12 are formed. However, the solder resist layer 6 on the upper surface side may have an opening for exposing a part of the outermost insulating layer 4 in a region facing the lower surface central portion of the semiconductor integrated circuit element 101. By providing such an opening, the gap formed between the central portion of the lower surface of the semiconductor integrated circuit element 101 and the wiring substrate 10 can be further increased.

ペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載した本発明にかかる配線基板を示す概略断面図である。1 is a schematic cross-sectional view showing a wiring board according to the present invention on which peripheral type semiconductor integrated circuit elements are mounted by flip-chip connection. 図１の配線基板を示す平面図であるIt is a top view which shows the wiring board of FIG. （ａ）〜（ｃ）は、本発明にかかる配線基板の第一の製造方法を示す概略説明図である。(A)-(c) is a schematic explanatory drawing which shows the 1st manufacturing method of the wiring board concerning this invention. （ｄ）〜（ｇ）は、本発明にかかる配線基板の第一の製造方法を示す概略説明図である。(D)-(g) is a schematic explanatory drawing which shows the 1st manufacturing method of the wiring board concerning this invention. （ｈ）〜（ｊ）は、本発明にかかる配線基板の第一の製造方法を示す概略説明図である。(H)-(j) is a schematic explanatory drawing which shows the 1st manufacturing method of the wiring board concerning this invention. （ａ）〜（ｄ）は、第一の製造方法にかかる帯状配線導体の形成方法を示す工程説明図である。(A)-(d) is process explanatory drawing which shows the formation method of the strip | belt-shaped wiring conductor concerning a 1st manufacturing method. （ｅ）〜（ｈ）は、第一の製造方法にかかる導電突起の形成方法を示す工程説明図である。(E)-(h) is process explanatory drawing which shows the formation method of the electrically conductive protrusion concerning a 1st manufacturing method. （ａ）〜（ｃ）は、第一の製造方法にかかるソルダーレジスト層の被着方法を示す工程説明図である。(A)-(c) is process explanatory drawing which shows the deposition method of the soldering resist layer concerning a 1st manufacturing method. （ａ）〜（ｃ）は、本発明にかかる配線基板の第二の製造方法を示す概略説明図である。(A)-(c) is a schematic explanatory drawing which shows the 2nd manufacturing method of the wiring board concerning this invention. （ｄ）〜（ｇ）は、本発明にかかる配線基板の第二の製造方法を示す概略説明図である。(D)-(g) is a schematic explanatory drawing which shows the 2nd manufacturing method of the wiring board concerning this invention. （ｈ）〜（ｊ）は、本発明にかかる配線基板の第二の製造方法を示す概略説明図である。(H)-(j) is a schematic explanatory drawing which shows the 2nd manufacturing method of the wiring board concerning this invention. （ａ）〜（ｃ）は、第二の製造方法にかかるソルダーレジスト層の被着方法を示す工程説明図である。(A)-(c) is process explanatory drawing which shows the deposition method of the soldering resist layer concerning a 2nd manufacturing method. ペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載した従来の配線基板を示す概略断面図である。It is a schematic sectional view showing a conventional wiring board on which a peripheral type semiconductor integrated circuit element is mounted by flip chip connection. 図１３の配線基板を示す平面図である。It is a top view which shows the wiring board of FIG.

符号の説明Explanation of symbols

２ 第一の配線導体
３ 絶縁基板
４ 絶縁層
５ 第二の配線導体
５ａ 半導体素子接続用の帯状配線導体
５ｂ 外部接続用の配線導体
６ ソルダーレジスト層
６ａ，６ｂ ソルダーレジスト層用の樹脂
７ スルーホール
８ 埋め込み樹脂
９ ビアホール
１０ 配線基板
１２ 導電突起
５１ 下地金属層
１０１ 半導体集積回路素子
１１０ 導電バンプ
１１１ 半田ボール
１１２ 充填樹脂
Ａ１ 第一開口
Ａ２ 第二開口
Ｒ１ 第一レジスト層
Ｒ２ 第二レジスト層 2 First wiring conductor 3 Insulating substrate 4 Insulating layer 5 Second wiring conductor 5a Band-shaped wiring conductor 5a for connecting semiconductor elements 5b Wiring conductor for external connection 6 Solder resist layer 6a, 6b Resin for solder resist layer 7 Through hole 8 embedded resin 9 via hole 10 wiring board 12 conductive protrusion 51 underlying metal layer 101 semiconductor integrated circuit element 110 conductive bump 111 solder ball 112 filling resin A1 first opening A2 second opening R1 first resist layer R2 second resist layer

Claims (8)

絶縁層と配線導体とが交互に積層されており、
最外層の絶縁層上に、半導体素子接続用であるとともに該半導体素子の外周辺に対して直角な方向に延びる帯状配線導体が前記半導体素子の外周辺に沿って複数並んで形成されているとともに、
該帯状配線導体上の一部に、半導体素子の電極端子がフリップチップ接続されるとともに平面視で四角形状である導電突起が前記帯状配線導体の幅と一致する幅で形成されており、かつ前記最外層の絶縁層上および前記帯状配線導体上に前記導電突起の少なくとも上面を露出させるソルダーレジスト層が被着されていることを特徴とする配線基板。 Insulating layers and wiring conductors are laminated alternately,
On the outermost insulating layer , a plurality of strip-shaped wiring conductors that are connected to the semiconductor element and extend in a direction perpendicular to the outer periphery of the semiconductor element are arranged side by side along the outer periphery of the semiconductor element . ,
The electrode terminal of the semiconductor element is flip-chip connected to a part on the strip-shaped wiring conductor, and a conductive projection having a quadrangular shape in plan view is formed with a width that matches the width of the strip-shaped wiring conductor, and A wiring board, wherein a solder resist layer that exposes at least an upper surface of the conductive protrusion is deposited on an outermost insulating layer and the strip-shaped wiring conductor. 前記帯状配線導体および前記導電突起は、銅めっきから成ることを特徴とする請求項１記載の配線基板。 The strip conductor and the conductive protrusions, the wiring board according to claim 1, wherein the formed Rukoto copper plating. 前記導電突起の前記半導体素子の外周辺に対して直角な方向に沿った長さが該導電突起の幅よりも長いことを特徴とする請求項１または２に記載の配線基板。 The wiring board according to claim 1, wherein a length of the conductive protrusion along a direction perpendicular to the outer periphery of the semiconductor element is longer than a width of the conductive protrusion. 絶縁層と配線導体とを交互に積層し、
最外層の絶縁層上に、半導体素子接続用であるとともに該半導体素子の外周辺に対して直角な方向に延びる帯状配線導体を前記半導体素子の外周辺に沿って複数並べて形成するとともに、
該帯状配線導体上の一部に、半導体素子の電極端子がフリップチップ接続されるとともに平面視で四角形状の導電突起を設け、かつ前記最外層の絶縁層と前記帯状配線導体上に前記導電突起の少なくとも上面を露出させるソルダーレジスト層を被着する配線基板の製造方法であって、
前記最外層の絶縁層上に、該絶縁層上の全面を覆う電解めっき用の下地金属層を形成する工程と、
次に前記下地金属層上に前記帯状配線導体に対応する形状の第一開口を有する第一レジスト層を形成する工程と、
次に前記第一開口内の前記下地金属層上に電解めっきにより前記帯状配線導体を形成する工程と、
次に前記第一レジスト層および前記帯状配線導体の上に、前記第一開口を横切る第二開口を有する第二レジスト層を形成する工程と、
次に前記第一開口および第二開口で囲まれた前記帯状配線導体上に電解めっきにより前記導電突起を前記第一開口で画定される幅および第二開口で画定される長さで形成する工程と、
次に前記第一レジスト層および第二レジスト層を除去する工程と、
次に前記帯状配線導体が形成された部分以外の前記下地金属層を除去する工程と、
次に前記最外層の絶縁層および帯状配線導体の表面に前記導電突起の少なくとも上面を露出させるソルダーレジスト層を被着する工程とを含むことを特徴とする配線基板の製造方法。 Insulating layers and wiring conductors are laminated alternately,
On the outermost insulating layer , a plurality of strip-like wiring conductors that are used for connecting a semiconductor element and extend in a direction perpendicular to the outer periphery of the semiconductor element are arranged side by side along the outer periphery of the semiconductor element ,
The electrode terminal of the semiconductor element is flip-chip connected to a part of the strip-shaped wiring conductor, and a rectangular conductive projection is provided in plan view, and the conductive projection is formed on the outermost insulating layer and the strip-shaped wiring conductor. A method of manufacturing a wiring board for depositing a solder resist layer that exposes at least the upper surface of
Forming a base metal layer for electrolytic plating covering the entire surface of the insulating layer on the outermost insulating layer;
Next, forming a first resist layer having a first opening having a shape corresponding to the strip-shaped wiring conductor on the base metal layer;
Next, forming the strip-shaped wiring conductor by electrolytic plating on the base metal layer in the first opening;
Next, forming a second resist layer having a second opening across the first opening on the first resist layer and the strip-shaped wiring conductor;
Next, the step of forming the conductive protrusion on the strip-shaped wiring conductor surrounded by the first opening and the second opening by electrolytic plating with a width defined by the first opening and a length defined by the second opening. When,
Next, removing the first resist layer and the second resist layer,
Next, the step of removing the base metal layer other than the portion where the strip-shaped wiring conductor is formed,
And a step of depositing a solder resist layer that exposes at least the upper surface of the conductive protrusion on the outermost insulating layer and the surface of the strip-shaped wiring conductor. 前記帯状配線導体および前記導電突起を、銅めっきにより形成することを特徴とする請求項４記載の配線基板の製造方法。 5. The method for manufacturing a wiring board according to claim 4, wherein the strip-shaped wiring conductor and the conductive protrusion are formed by copper plating . 前記導電突起の前記長さを前記幅よりも長く形成することを特徴とする請求項４または５に記載の配線基板の製造方法。   6. The method of manufacturing a wiring board according to claim 4, wherein the length of the conductive protrusion is formed longer than the width. 前記ソルダーレジスト層を被着する工程は、ソルダーレジスト層用の樹脂で前記導電突起を含む最外層の絶縁層および帯状配線導体の全面を被覆する工程と、被覆した前記ソルダーレジスト層用の樹脂を前記導電突起の上面が露出するまで研磨する工程とを含んでいる請求項４乃至６の何れかに記載の配線基板の製造方法。   The step of depositing the solder resist layer includes a step of covering the entire surface of the outermost insulating layer including the conductive protrusion and the strip-shaped wiring conductor with a resin for the solder resist layer, and a resin for the coated solder resist layer. The method for manufacturing a wiring board according to claim 4, further comprising a step of polishing until an upper surface of the conductive protrusion is exposed. 前記ソルダーレジスト層を被着する工程は、ソルダーレジスト層用の感光性樹脂で前記導電突起を含む最外層の絶縁層および帯状配線導体の全面を被覆する工程と、被覆した前記感光性樹脂を露光および現像処理して前記ソルダーレジスト層に前記導電突起の上面を露出させる開口を形成する工程とを含む請求項４乃至６の何れかに記載の配線基板の製造方法。   The step of depositing the solder resist layer includes a step of covering the entire surface of the outermost insulating layer including the conductive protrusion and the strip-shaped wiring conductor with a photosensitive resin for the solder resist layer, and exposing the coated photosensitive resin. And a developing process to form an opening in the solder resist layer that exposes the upper surface of the conductive protrusion. 7. The method of manufacturing a wiring board according to claim 4.
JP2005167063A 2005-06-07 2005-06-07 Wiring board and manufacturing method thereof Expired - Fee Related JP4769022B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005167063A JP4769022B2 (en) 2005-06-07 2005-06-07 Wiring board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005167063A JP4769022B2 (en) 2005-06-07 2005-06-07 Wiring board and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2006344664A JP2006344664A (en) 2006-12-21
JP4769022B2 true JP4769022B2 (en) 2011-09-07

Family

ID=37641425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005167063A Expired - Fee Related JP4769022B2 (en) 2005-06-07 2005-06-07 Wiring board and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4769022B2 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008140886A (en) 2006-11-30 2008-06-19 Shinko Electric Ind Co Ltd Wiring substrate and manufacturing method therefor
JP5138277B2 (en) * 2007-05-31 2013-02-06 京セラＳｌｃテクノロジー株式会社 Wiring board and manufacturing method thereof
JP4802155B2 (en) * 2007-08-07 2011-10-26 京セラＳｌｃテクノロジー株式会社 Wiring board
CN101681891A (en) * 2007-09-12 2010-03-24 播磨化成株式会社 Solder precoated substrate, mounting substrate, and solder precoating method
JP5001903B2 (en) * 2008-05-28 2012-08-15 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP2009289868A (en) * 2008-05-28 2009-12-10 Kyocer Slc Technologies Corp Wiring substrate and its manufacturing method
JP2010040936A (en) * 2008-08-07 2010-02-18 Kyocer Slc Technologies Corp Wiring board and method of manufacturing the same
JP2010074032A (en) * 2008-09-22 2010-04-02 Kyocer Slc Technologies Corp Wiring board and manufacturing method thereof
JP5113114B2 (en) 2009-04-06 2013-01-09 新光電気工業株式会社 Wiring board manufacturing method and wiring board
JP2011009570A (en) * 2009-06-26 2011-01-13 Fujitsu Ltd Electronic component package and method of manufacturing the same
JP2012009586A (en) 2010-06-24 2012-01-12 Shinko Electric Ind Co Ltd Wiring board, semiconductor device and wiring board manufacturing method
KR101891840B1 (en) 2010-09-28 2018-08-24 미쓰비시 세이시 가부시키가이샤 Method for forming solder resist pattern
US9269610B2 (en) * 2014-04-15 2016-02-23 Qualcomm Incorporated Pattern between pattern for low profile substrate
CN106455362A (en) * 2016-11-24 2017-02-22 生益电子股份有限公司 PCB (printed circuit board) manufacture method and PCB
CN113495384B (en) * 2020-03-18 2022-12-30 华为技术有限公司 Direct type backlight module, display device and manufacturing method of circuit board
WO2022170162A1 (en) * 2021-02-05 2022-08-11 Qorvo Us, Inc. Electronic device comprising a single dielectric layer for solder mask and cavity and method for fabricating the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003008228A (en) * 2001-06-22 2003-01-10 Ibiden Co Ltd Multilayer printed wiring board and method of manufacturing the same
JP2004095972A (en) * 2002-09-03 2004-03-25 Sumitomo Metal Electronics Devices Inc Manufacturing method for plastic package

Also Published As

Publication number Publication date
JP2006344664A (en) 2006-12-21

Similar Documents

Publication Publication Date Title
JP4769022B2 (en) Wiring board and manufacturing method thereof
JP5091469B2 (en) Wiring board and manufacturing method thereof
TWI470758B (en) Wiring board and manufacturing method thereof
JP5138277B2 (en) Wiring board and manufacturing method thereof
US8835773B2 (en) Wiring board and method of manufacturing the same
KR20070120449A (en) Wiring substrate and manufacturing method thereof, and semiconductor apparatus
JP5106197B2 (en) Semiconductor device and manufacturing method thereof
JP2010040936A (en) Wiring board and method of manufacturing the same
JP4802155B2 (en) Wiring board
JP5599860B2 (en) Manufacturing method of semiconductor package substrate
JP2010135347A (en) Wiring substrate, and method for manufacturing the same
JP5058929B2 (en) Wiring board and manufacturing method thereof
JP2007059588A (en) Method of manufacturing wiring board, and wiring board
JP2009289868A (en) Wiring substrate and its manufacturing method
JP2004200412A (en) Wiring board with solder bump, and manufacturing method thereof
JP5106351B2 (en) Wiring board and manufacturing method thereof
JP2006049762A (en) Part built-in substrate and manufacturing method thereof
JP4751121B2 (en) Wiring board
JP2011119655A (en) Printed circuit board and method of manufacturing the same
JP2010010494A (en) Wiring board and method of manufacturing the same
JP6259045B2 (en) Wiring board manufacturing method
JP5455116B2 (en) Wiring board and manufacturing method thereof
JP4439248B2 (en) Wiring substrate and semiconductor device using the same
JP6121831B2 (en) Wiring board
JP2012119361A (en) Wiring board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080530

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100729

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100810

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101007

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110607

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110617

R150 Certificate of patent or registration of utility model

Ref document number: 4769022

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140624

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees