JP4439248B2 - Wiring substrate and semiconductor device using the same - Google Patents

Wiring substrate and semiconductor device using the same Download PDF

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JP4439248B2
JP4439248B2 JP2003394571A JP2003394571A JP4439248B2 JP 4439248 B2 JP4439248 B2 JP 4439248B2 JP 2003394571 A JP2003394571 A JP 2003394571A JP 2003394571 A JP2003394571 A JP 2003394571A JP 4439248 B2 JP4439248 B2 JP 4439248B2
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semiconductor element
mounting portion
wiring board
wiring
connection
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JP2005158968A (en
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義政 宮本
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

本発明は、半導体素子を搭載するために用いられる配線基板およびこれを用いた半導体装置に関する。   The present invention relates to a wiring board used for mounting a semiconductor element and a semiconductor device using the wiring board.

近年、マイクロプロセッサやＡＳＩＣ（Application Specific Integrated Circuit）等に代表される半導体素子を小型、高密度配線の配線基板上に搭載して成る半導体装置においては、半導体素子の高集積化に伴い、半導体素子の搭載方法として、素子および半導体装置の小型化に対応できるフリップチップ接続による搭載が多用されるようになってきている。   2. Description of the Related Art In recent years, in semiconductor devices in which semiconductor elements typified by microprocessors, ASICs (Application Specific Integrated Circuits), and the like are mounted on a small-sized, high-density wiring substrate, As a mounting method, mounting by flip chip connection, which can cope with the miniaturization of elements and semiconductor devices, has been increasingly used.

このフリップチップ接続による搭載は、半導体素子の電極を半導体素子の下面に縦横の並びに多数配列するとともに、この半導体素子を搭載するための配線基板の上面に半導体素子の電極に対応した配列の接続パッドを設けておき、半導体素子の電極と配線基板の接続パッドとを互いに対向させて半田バンプを介して電気的に接続したものである。   Mounting by flip-chip connection is performed by arranging a large number of electrodes of a semiconductor element vertically and horizontally on the lower surface of the semiconductor element, and a connection pad having an arrangement corresponding to the electrode of the semiconductor element on the upper surface of the wiring board for mounting the semiconductor element. The electrodes of the semiconductor element and the connection pads of the wiring board are opposed to each other and electrically connected via solder bumps.

半導体素子が搭載される配線基板としては、主に樹脂製の配線基板が用いられる。この樹脂製の配線基板は、例えばガラス−エポキシ板等から成る絶縁層やエポキシ樹脂等から成る樹脂層を複数層積層して成る絶縁基板の内部および表面に銅箔や銅めっき膜等の導体層から成る配線導体を設けて成る。配線導体の一部は絶縁基板の上面に露出して半導体素子の電極と接続される接続パッドを形成している。また、絶縁基板の表面には接続パッドの中央部を露出させる開口部を有するソルダーレジスト層が被着されている。ソルダーレジスト層は接続パッド間の電気的な絶縁を良好に保つとともに接続パッドを絶縁基体に強固に密着させるための保護層である。そして、ソルダーレジスト層の開口部内に露出した接続パッドと半導体素子の電極とを半田バンプを介して接続することにより半導体素子がフリップチップ接続により配線基板上に搭載されて半導体装置となる。
特開２００３−１３３７０２号公報 As the wiring board on which the semiconductor element is mounted, a resin wiring board is mainly used. This resin wiring board is made of, for example, a conductive layer such as a copper foil or a copper plating film on the inside and the surface of an insulating board formed by laminating a plurality of insulating layers made of glass-epoxy board or the like or a resin layer made of epoxy resin or the like. The wiring conductor which consists of is provided. A part of the wiring conductor is exposed on the upper surface of the insulating substrate to form a connection pad connected to the electrode of the semiconductor element. Also, a solder resist layer having an opening exposing the central portion of the connection pad is deposited on the surface of the insulating substrate. The solder resist layer is a protective layer for maintaining good electrical insulation between the connection pads and firmly attaching the connection pads to the insulating substrate. Then, by connecting the connection pads exposed in the openings of the solder resist layer and the electrodes of the semiconductor elements via solder bumps, the semiconductor elements are mounted on the wiring substrate by flip-chip connection to form a semiconductor device.
JP 2003-133702 A

しかしながら、上述のように樹脂製の配線基板に半導体素子を半田バンプを介してフリップチップ接続により搭載した半導体装置においては、配線基板と半導体素子との熱膨張係数の差が大きいとともに半導体素子が配線基板よりも硬くて変形しにくいことから、半導体素子の作動や使用環境温度の変化等により熱が繰り返し加えられた場合に、半導体素子と配線基板との熱膨張率差に起因して発生する応力が半導体素子の外周部に対応する配線基板の上面側に半田バンプを介して加わり、それが半田バンプを支点として最外周に配列された接続パッドにおける外側の縁と絶縁層との間に大きく作用し、そこを起点として絶縁層にクラックが発生してしまい、その結果、半導体素子と配線基板との電気的および機械的な接続信頼性が損なわれてしまうという問題点を有していた。   However, as described above, in a semiconductor device in which a semiconductor element is mounted on a resin wiring board through solder bumps by flip chip connection, the difference in thermal expansion coefficient between the wiring board and the semiconductor element is large and the semiconductor element is wired. Because it is harder and less deformable than the substrate, the stress generated due to the difference in thermal expansion coefficient between the semiconductor element and the wiring board when heat is repeatedly applied due to the operation of the semiconductor element or changes in the operating environment temperature, etc. Is applied to the upper surface side of the wiring board corresponding to the outer peripheral portion of the semiconductor element via a solder bump, which acts greatly between the outer edge of the connection pad arranged on the outermost periphery with the solder bump as a fulcrum and the insulating layer As a result, cracks occur in the insulating layer starting from that point, and as a result, the electrical and mechanical connection reliability between the semiconductor element and the wiring board is impaired. We had a problem that put away.

本発明は、上記のような問題に鑑み案出されたものであり、その目的は、半導体素子の動作および使用環境温度の変化等により熱が長期間にわたり繰り返し加えられたとしても絶縁基板にクラックが発生することがなく、半導体素子と配線基板との接続信頼性に優れた半導体装置を提供することにある。   The present invention has been devised in view of the above problems, and its purpose is to crack the insulating substrate even if heat is repeatedly applied over a long period of time due to the operation of the semiconductor element and changes in the operating environment temperature. It is an object of the present invention to provide a semiconductor device that is excellent in connection reliability between a semiconductor element and a wiring board.

本発明の配線基板は、上面の中央部に半導体素子がフリップチップ接続により搭載される搭載部を有する絶縁基板と、前記搭載部に縦横に並んで配列された、前記半導体素子の電極が半田を介して接続される複数の接続パッドと、前記搭載部内に形成され、内部に導体を有するビア孔と、前記ビア孔を介して前記接続パッドに接続された下層の配線導体と、を具備する配線基板において、前記複数の接続パッドのうち最外周に配列された前記各接続パッドは、前記ビア孔内の前記導体に対して前記搭載部内で接続され、且つ該接続部よりも外側に向けて延出する延出部を有し、前記延出部は、前記搭載部の外側で他の配線と接続されないように前記搭載部の外側に延出されていることを特徴とするものである。 In the wiring board of the present invention, an insulating substrate having a mounting portion on which a semiconductor element is mounted by flip-chip connection at the center of the upper surface, and electrodes of the semiconductor element arranged vertically and horizontally on the mounting portion are soldered. A wiring comprising: a plurality of connection pads connected through the via ; a via hole formed in the mounting portion and having a conductor therein; and a lower wiring conductor connected to the connection pad through the via hole in the substrate, wherein the connection pads that are arranged at the outermost periphery among the plurality of connection pads, which is connected with the mounting portion relative to the conductor in the via hole, and towards the outer side than the connecting portion extending It has an extending part to be extended , and the extending part is extended outside the mounting part so as not to be connected to other wiring outside the mounting part .

また本発明の半導体装置は、上記の配線基板の搭載部に半導体素子をフリップチップ接続により搭載したことを特徴とするものである。   The semiconductor device of the present invention is characterized in that a semiconductor element is mounted on the mounting portion of the wiring board by flip chip connection.

本発明の配線基板およびこれを用いた半導体装置によれば、最外周に配列された接続パッドは、搭載部の外側に向けて延出する延出部が形成されていることから、半導体素子の作動や使用環境温度の変化等により熱が繰り返し加えられた場合に、半導体素子と配線基板との熱膨張率差に起因して発生する応力が半導体素子の外周部に対応する配線基板の上面側に集中したとしても、半田バンプを支点として最外周に配列された接続パッドと絶縁層との間に作用する応力は延出部により分散される。その結果、絶縁層にクラックが発生することが有効に防止され、半導体素子と配線基板との接続信頼性に優れる半導体装置を提供することができる。   According to the wiring board of the present invention and the semiconductor device using the same, since the connection pads arranged on the outermost periphery are formed with the extending portions extending toward the outside of the mounting portion, When heat is repeatedly applied due to changes in operating temperature, operating environment, etc., the stress generated due to the difference in coefficient of thermal expansion between the semiconductor element and the wiring board is the upper side of the wiring board corresponding to the outer periphery of the semiconductor element Even if concentrated, the stress acting between the connection pads arranged on the outermost periphery with the solder bump as a fulcrum and the insulating layer is dispersed by the extending portion. As a result, the occurrence of cracks in the insulating layer is effectively prevented, and a semiconductor device having excellent connection reliability between the semiconductor element and the wiring board can be provided.

次に、本発明の配線基板およびこれを用いた半導体装置を添付の図面に基づき詳細に説明する。   Next, a wiring board of the present invention and a semiconductor device using the same will be described in detail with reference to the accompanying drawings.

図１は、本発明の配線基板およびこれを用いた半導体装置の実施の形態例を示す断面図である。図１において１は絶縁基板、２は配線導体であり、主としてこれらで本発明の配線基板が構成され、この配線基板上に半導体素子３がフリップチップ接続により搭載されることにより本発明の半導体装置が構成される。   FIG. 1 is a cross-sectional view showing an embodiment of a wiring board of the present invention and a semiconductor device using the same. In FIG. 1, reference numeral 1 denotes an insulating substrate, and 2 denotes a wiring conductor, which mainly constitutes the wiring substrate of the present invention, and the semiconductor element 3 is mounted on the wiring substrate by flip-chip connection. Is configured.

絶縁基板１は、例えばガラス繊維を縦横に織り込んだガラス織物にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させて成る板状の絶縁層１ａの上下面にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る絶縁層１ｂをそれぞれ複数層ずつ積層して成り、その上面中央部に半導体素子３がフリップチップ接続により搭載される搭載部を有している。そして、その搭載部から下面にかけて銅箔や銅めっき膜等の導体層から成る複数の配線導体２が形成されている。   The insulating substrate 1 is made of, for example, epoxy resin or bismaleimide triazine on the upper and lower surfaces of a plate-like insulating layer 1a formed by impregnating a glass fabric in which glass fibers are woven vertically and horizontally with a thermosetting resin such as epoxy resin or bismaleimide triazine resin. A plurality of insulating layers 1b made of a thermosetting resin such as a resin are stacked, and a mounting portion on which the semiconductor element 3 is mounted by flip chip connection is provided at the center of the upper surface. A plurality of wiring conductors 2 made of a conductor layer such as a copper foil or a copper plating film are formed from the mounting portion to the lower surface.

絶縁基板１を構成する絶縁層１ａは、厚みが０．３〜１．５ｍｍ程度であり、その上面から下面にかけて直径が０．２〜１．０ｍｍ程度の複数の貫通孔４を有している。そして、その上下面および各貫通孔４の内面には配線導体２の一部が被着されており、上下面の配線導体２が貫通孔４の内部を介して電気的に接続されている。   The insulating layer 1a constituting the insulating substrate 1 has a thickness of about 0.3 to 1.5 mm, and has a plurality of through holes 4 having a diameter of about 0.2 to 1.0 mm from the upper surface to the lower surface. . A part of the wiring conductor 2 is attached to the upper and lower surfaces and the inner surface of each through-hole 4, and the upper and lower wiring conductors 2 are electrically connected via the inside of the through-hole 4.

このような絶縁層１ａは、ガラス織物に未硬化の熱硬化性樹脂を含浸させたシートを熱硬化させた後、これに上面から下面にかけてドリル加工を施すことにより製作される。なお、絶縁層１ａ上下面の配線導体２は、絶縁層１ａ用のシートの上下全面に厚みが５〜５０μｍ程度の銅箔を貼着しておくとともに、この銅箔をシートの硬化後にエッチング加工することにより所定のパターンに形成される。また、貫通孔４内面の配線導体２は、絶縁層１ａに貫通孔４を設けた後に、この貫通孔４内面に無電解めっき法および電解めっき法により厚みが５〜５０μｍ程度の銅めっき膜を析出させることにより形成される。   Such an insulating layer 1a is manufactured by thermally curing a sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then drilling the sheet from the upper surface to the lower surface. The wiring conductors 2 on the upper and lower surfaces of the insulating layer 1a have a copper foil having a thickness of about 5 to 50 μm attached to the entire upper and lower surfaces of the sheet for the insulating layer 1a, and the copper foil is etched after the sheet is cured. By doing so, a predetermined pattern is formed. The wiring conductor 2 on the inner surface of the through hole 4 is provided with a copper plating film having a thickness of about 5 to 50 μm by electroless plating and electrolytic plating on the inner surface of the through hole 4 after the through hole 4 is provided in the insulating layer 1a. Formed by precipitation.

さらに、絶縁層１ａは、その貫通孔４の内部にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る樹脂柱５が充填されている。樹脂柱５は、貫通孔４を塞ぐことにより貫通孔４の直上および直下に絶縁層１ｂを形成可能とするためのものであり、未硬化のペースト状の熱硬化性樹脂を貫通孔４内にスクリーン印刷法により充填し、これを熱硬化させた後、その上下面を略平坦に研磨することにより形成される。そして、この樹脂柱５を含む絶縁層１ａの上下面に絶縁層１ｂが積層されている。   Further, the insulating layer 1a is filled with a resin column 5 made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin in the through hole 4 thereof. The resin pillar 5 is for making it possible to form the insulating layer 1b directly above and below the through-hole 4 by closing the through-hole 4, and an uncured paste-like thermosetting resin is placed in the through-hole 4. After filling with a screen printing method and thermosetting it, the upper and lower surfaces thereof are polished to be substantially flat. And the insulating layer 1b is laminated | stacked on the upper and lower surfaces of the insulating layer 1a containing this resin pillar 5. FIG.

絶縁層１ａの上下面に積層された絶縁層１ｂは、それぞれの厚みが２０〜５０μｍ程度であり、各層の上面から下面にかけて直径が３０〜１００μｍ程度の複数のビア孔６を有している。これらの絶縁層１ｂは、配線導体２を高密度に配線するための絶縁間隔を提供するためのものであり、絶縁層１ｂにはその表面およびビア孔６内に配線導体２の一部が被着されている。そして、上層の配線導体２と下層の配線導体２とをビア孔６の内部を介して電気的に接続することにより高密度配線を立体的に形成可能としている。   The insulating layer 1b laminated on the upper and lower surfaces of the insulating layer 1a has a thickness of about 20 to 50 μm, and has a plurality of via holes 6 having a diameter of about 30 to 100 μm from the upper surface to the lower surface of each layer. These insulating layers 1b are provided to provide an insulating interval for wiring the wiring conductors 2 at a high density. The insulating layer 1b is covered with a part of the wiring conductors 2 on the surface and in the via holes 6. It is worn. A high-density wiring can be formed three-dimensionally by electrically connecting the upper wiring conductor 2 and the lower wiring conductor 2 via the inside of the via hole 6.

このような絶縁層１ｂは、厚みが２０〜５０μｍ程度の未硬化の熱硬化性樹脂フィルムを絶縁層１ａの上下面に貼着し、これを熱硬化させるとともにレーザ加工によりビア孔６を穿孔し、さらにその上に同様にして次の絶縁層１ｂを順次積み重ねることによって形成される。なお、各絶縁層１ｂ表面およびビア孔６内に被着された配線導体２は、各絶縁層１ｂを形成する毎に各絶縁層１ｂの表面およびビア孔６内に５〜５０μｍ程度の厚みの銅めっき膜を公知のセミアディティブ法やサブトラクティブ法等のパターン形成法により所定のパターンに被着させることによって形成される。   For such an insulating layer 1b, an uncured thermosetting resin film having a thickness of about 20 to 50 μm is stuck on the upper and lower surfaces of the insulating layer 1a, and this is thermoset, and via holes 6 are drilled by laser processing. Further, it is formed by sequentially stacking the next insulating layer 1b in the same manner. The wiring conductor 2 deposited on the surface of each insulating layer 1b and the via hole 6 has a thickness of about 5 to 50 μm on the surface of each insulating layer 1b and the via hole 6 every time each insulating layer 1b is formed. It is formed by depositing a copper plating film in a predetermined pattern by a pattern forming method such as a known semi-additive method or subtractive method.

さらに、最表層の絶縁層１ｂ上にはソルダーレジスト層７が被着されている。ソルダーレジスト層７は、例えばアクリル変性エポキシ樹脂にシリカやタルク等の無機物粉末フィラーを３０〜７０質量％程度分散させた絶縁材料から成り、表層の配線導体２同士の電気的絶縁信頼性を高めるとともに、後述する接続パッド２ａ、２ｂの絶縁基板１への接合強度を大きなものとする作用をなす。   Further, a solder resist layer 7 is deposited on the outermost insulating layer 1b. The solder resist layer 7 is made of an insulating material in which, for example, an inorganic powder filler such as silica or talc is dispersed in an acrylic-modified epoxy resin in an amount of about 30 to 70% by mass, and improves the electrical insulation reliability between the wiring conductors 2 on the surface layer. The function is to increase the bonding strength of the connection pads 2a and 2b described later to the insulating substrate 1.

このようなソルダーレジスト層７は、その厚みが１０〜５０μｍ程度であり、感光性を有するソルダーレジスト層７用の未硬化樹脂ペーストをロールコーター法やスクリーン印刷法を採用して最表層の絶縁層１ｂ上に塗布し、これを乾燥させた後、露光および現像処理を行なって接続パッド２ａ、２ｂを露出させる開口部を形成した後、これを熱硬化させることによって形成される。あるいは、ソルダーレジスト層７用の未硬化の樹脂フィルムを最上層の絶縁層１ｂ上に貼着した後、これを熱硬化させ、しかる後、接続パッド２ａ、２ｂに対応する位置にレーザ光を照射し、硬化した樹脂フィルムを部分的に除去することによって接続パッド２ａ、２ｂを露出させる開口部を有するように形成される。   Such a solder resist layer 7 has a thickness of about 10 to 50 μm, and an uncured resin paste for the solder resist layer 7 having photosensitivity is applied to the outermost layer by adopting a roll coater method or a screen printing method. It is formed by applying on 1b and drying it, then performing exposure and development processes to form openings that expose the connection pads 2a, 2b, and then thermally curing them. Alternatively, after an uncured resin film for the solder resist layer 7 is stuck on the uppermost insulating layer 1b, it is thermally cured, and then irradiated with laser light at positions corresponding to the connection pads 2a and 2b. Then, the cured resin film is partially removed to form openings that expose the connection pads 2a and 2b.

絶縁基板１の搭載部から下面にかけて形成された配線導体２は、半導体素子３の各電極を外部電気回路基板に接続するための導電路として機能し、絶縁基板１の搭載部に露出している部位が半導体素子３の各電極が半田バンプ８を介して接続される電子部品接続用の接続パッド２ａを、絶縁基体１の下面に露出した部位が外部電気回路基板に半田バンプ９を介して接続される外部接続用の接続パッド２ｂを形成している。これらの接続パッド２ａ、２ｂは、絶縁基板１の搭載部および下面において例えば格子状の縦横の並びに配列されており、半導体素子３の電極と接続パッド２ａとが半田バンプ８を介して接続されることにより半導体素子３が絶縁基板１の搭載部にフリップチップ接続により搭載された本発明の半導体装置となり、この半導体装置における接続パッド２ｂを外部電気回路基板の配線導体に半田バンプ９を介して接続することによって半導体素子３が外部電気回路基板に電気的に接続されることとなる。なお、本例の半導体装置においては、絶縁基板１の搭載部と半導体素子３との間にアンダーフィルと呼ばれる保護樹脂１０が充填されている例を示している。保護樹脂１０は絶縁基板１の搭載部に半導体素子３を半田バンプ８を介してフリップチップ接続により搭載した後に、絶縁基板１と半導体素子３との間に未硬化の熱硬化性樹脂ペーストを注入するとともにそのペーストを熱硬化させることにより充填される。なお、絶縁基板１の搭載部に半導体素子３を半田バンプ８を介してフリップチップ接続により搭載するには、接続パッド２ａに半田粉末とフラックスとを含有する半田ペーストをスクリーン印刷法を採用して印刷塗布し、それを２２０〜２６０℃の温度で加熱して半田粉末を溶融させることにより接続パッド２ａ上に半田バンプ８を予め形成しておき、この半田バンプ８と半導体素子３の電極とを接触させた状態で半田バンプ８を溶融させる方法が採用される。   The wiring conductor 2 formed from the mounting portion of the insulating substrate 1 to the lower surface functions as a conductive path for connecting each electrode of the semiconductor element 3 to the external electric circuit substrate, and is exposed to the mounting portion of the insulating substrate 1. A part is connected to the connection pad 2a for connecting an electronic component to which each electrode of the semiconductor element 3 is connected via a solder bump 8. A part exposed on the lower surface of the insulating substrate 1 is connected to an external electric circuit board via a solder bump 9. A connection pad 2b for external connection is formed. These connection pads 2 a and 2 b are arranged in, for example, a lattice shape on the mounting portion and the lower surface of the insulating substrate 1, and the electrodes of the semiconductor element 3 and the connection pads 2 a are connected via the solder bumps 8. Thus, the semiconductor device of the present invention in which the semiconductor element 3 is mounted on the mounting portion of the insulating substrate 1 by flip chip connection, and the connection pad 2b in this semiconductor device is connected to the wiring conductor of the external electric circuit board via the solder bumps 9 is provided. As a result, the semiconductor element 3 is electrically connected to the external electric circuit board. In the semiconductor device of this example, an example in which a protective resin 10 called an underfill is filled between the mounting portion of the insulating substrate 1 and the semiconductor element 3 is shown. After the semiconductor element 3 is mounted on the mounting portion of the insulating substrate 1 via the solder bumps 8 by flip chip connection, the protective resin 10 is injected with an uncured thermosetting resin paste between the insulating substrate 1 and the semiconductor element 3. And the paste is filled by thermosetting. In order to mount the semiconductor element 3 on the mounting portion of the insulating substrate 1 by the flip chip connection via the solder bump 8, a solder paste containing solder powder and flux is applied to the connection pad 2a by a screen printing method. The solder bumps 8 are formed in advance on the connection pads 2a by applying the printing and heating them at a temperature of 220 to 260 ° C. to melt the solder powder, and the solder bumps 8 and the electrodes of the semiconductor element 3 are formed. A method of melting the solder bumps 8 in the contacted state is employed.

そして本発明の配線基板およびこれを用いた半導体装置においては、接続パッド２ａは、図２に上面図で示すように、例えば格子状の並びに縦横に配列されており、そのうち最外周に配列された接続パッド２ａは搭載部の外側に向けて延出する延出部１１が形成されている。延出部１１は、接続パッド２ａと同じ材料により接続パッド２ａと一体的に形成されており、半導体素子３が作動時に発生する熱や使用される環境温度の変化による熱による応力が半導体素子３の外周部に対応する絶縁基板１の上面側に加えられた場合に、その応力が半田バンプ８を支点として最外周に配列された接続パッド２ａの外側の縁に大きく集中して作用するのを防止するための応力分散部材として機能する。このように、縦横の並びに配列された接続パッド２ａのうち最外周に配列された接続パッド２ａに、搭載部の外側に向けて延出する延出部１１が形成されていることから、半導体素子３が作動時に発生する熱や使用される環境温度の変化による熱による応力が半導体素子３の外周部に対応する絶縁基板１の上面側に加えられたとしても、その応力は延出部１１により分散されるので、絶縁基板１やソルダーレジスト層７にクラックが発生することを有効に防止することができる。したがって、本発明の配線基板およびこれを用いた半導体装置によれば、半導体素子３の動作および使用環境温度の変化等により熱が長期間にわたり繰り返し加えられたとしても絶縁基板１やソルダーレジスト層７にクラックが発生することがなく、半導体素子３と配線基板との接続信頼性に優れた半導体装置を提供することができる。   In the wiring board of the present invention and the semiconductor device using the same, the connection pads 2a are arranged in, for example, a grid and vertically and horizontally, as shown in a top view in FIG. The connection pad 2a is formed with an extension portion 11 extending toward the outside of the mounting portion. The extending portion 11 is formed integrally with the connection pad 2a from the same material as that of the connection pad 2a, and the stress caused by the heat generated when the semiconductor element 3 operates or the heat due to the change in the ambient temperature used is applied to the semiconductor element 3. When the stress is applied to the upper surface side of the insulating substrate 1 corresponding to the outer peripheral portion of the solder, the stress acts on the outer edge of the connection pad 2a arranged on the outermost periphery with the solder bump 8 as a fulcrum. It functions as a stress dispersion member for preventing. As described above, since the extending portion 11 extending toward the outside of the mounting portion is formed on the connecting pad 2a arranged on the outermost periphery among the connecting pads 2a arranged vertically and horizontally, the semiconductor element 3, even if stress due to heat generated during operation or due to change in environmental temperature used is applied to the upper surface side of the insulating substrate 1 corresponding to the outer peripheral portion of the semiconductor element 3, the stress is caused by the extension 11. Since it is dispersed, the occurrence of cracks in the insulating substrate 1 and the solder resist layer 7 can be effectively prevented. Therefore, according to the wiring board and the semiconductor device using the same according to the present invention, even if heat is repeatedly applied over a long period of time due to the operation of the semiconductor element 3 and changes in the use environment temperature, the insulating substrate 1 and the solder resist layer 7 Thus, it is possible to provide a semiconductor device that is excellent in connection reliability between the semiconductor element 3 and the wiring board.

なお、延出部１１の幅が接続パッド２ａの幅の５０％未満である場合、半導体素子３が作動時に発生する熱や使用される環境温度の変化による熱による応力が半導体素子３の外周部に対応する絶縁基板１の上面側に加えられた場合に、その応力を延出部１１で良好に分散することが困難となる。したがって、延出部１１の幅は、接続パッド２ａの幅の５０％以上あることが好ましい。また、延出部１１が接続パッド２ａから搭載部の外側に向けて５０μｍ未満の位置まで延出している場合、半導体素子３が作動時に発生する熱や使用される環境温度の変化による熱による応力が半導体素子３の外周部に対応する絶縁基板１の上面側に加えられた場合に、その応力を延出部１１で良好に分散することが困難となる。したがって、延出部１１は、接続パッド２ａから搭載部の外側に向けて５０μｍ以上外側の位置まで延出していることが好ましい。   When the width of the extending portion 11 is less than 50% of the width of the connection pad 2a, the stress caused by the heat generated when the semiconductor element 3 operates or the environmental temperature used is affected by the outer peripheral portion of the semiconductor element 3. When it is applied to the upper surface side of the insulating substrate 1 corresponding to the above, it becomes difficult to disperse the stress in the extended portion 11 well. Therefore, the width of the extension portion 11 is preferably 50% or more of the width of the connection pad 2a. Further, when the extending portion 11 extends from the connection pad 2a toward the outside of the mounting portion to a position of less than 50 μm, the stress caused by the heat generated when the semiconductor element 3 is operated or the heat due to the change in the ambient temperature used. Is applied to the upper surface side of the insulating substrate 1 corresponding to the outer peripheral portion of the semiconductor element 3, it becomes difficult to disperse the stress well in the extending portion 11. Therefore, it is preferable that the extending portion 11 extends from the connection pad 2a toward the outside of the mounting portion to a position outside by 50 μm or more.

なお、本発明の配線基板およびこれを用いた半導体装置は、上述の実施の形態例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。例えば上述の実施の形態例では、延出部１１を最外周に配列された接続パッド２ａの全てについて形成したが、延出部１１は必ずしも最外周に配列された接続パッド２ａの全てについて形成する必要はなく、最外周に配列された接続パッド２ａのうち、応力が最も集中する角部近傍のものにだけ形成してもよい。   The wiring board and the semiconductor device using the wiring board according to the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiment, the extension portion 11 is formed for all the connection pads 2a arranged on the outermost periphery, but the extension portion 11 is not necessarily formed for all the connection pads 2a arranged on the outermost periphery. There is no need, and the connection pads 2a arranged on the outermost periphery may be formed only in the vicinity of the corner where stress is most concentrated.

本発明の配線基板およびこれを用いた半導体装置を実施するための最良の形態例を示す断面図である。It is sectional drawing which shows the best example for implementing the wiring board of this invention, and a semiconductor device using the same. 図１の配線基板の平面図である。It is a top view of the wiring board of FIG.

符号の説明Explanation of symbols

１：絶縁基板
２：配線導体
２ａ：接続パッド
３：半導体素子
８：半田
１１：延出部 1: Insulating substrate 2: Wiring conductor 2a: Connection pad 3: Semiconductor element 8: Solder 11: Extension part

Claims (2)

上面の中央部に半導体素子がフリップチップ接続により搭載される搭載部を有する絶縁基板と、
前記搭載部に縦横に並んで配列された、前記半導体素子の電極が半田を介して接続される複数の接続パッドと、
前記搭載部内に形成され、内部に導体を有するビア孔と、
前記ビア孔を介して前記接続パッドに接続された下層の配線導体と、
を具備する配線基板において、
前記複数の接続パッドのうち最外周に配列された前記各接続パッドは、前記ビア孔内の前記導体に対して前記搭載部内で接続され、且つ該接続部よりも外側に向けて延出する延出部を有し、
前記延出部は、前記搭載部の外側で他の配線と接続されないように前記搭載部の外側に延出されていることを特徴とする配線基板。 An insulating substrate having a mounting portion on which a semiconductor element is mounted by flip chip connection at the center of the upper surface;
A plurality of connection pads, arranged in rows and columns on the mounting portion, to which the electrodes of the semiconductor element are connected via solder;
A via hole formed in the mounting portion and having a conductor inside;
A lower layer wiring conductor connected to the connection pad through the via hole;
In a wiring board comprising:
Wherein each connection pads arranged on the outermost periphery of the plurality of connection pads, which is connected with the mounting portion relative to the conductor in the via hole, and extending extending outward than the connecting portion Has an exit ,
The wiring board is characterized in that the extending portion extends outside the mounting portion so as not to be connected to other wiring outside the mounting portion . 請求項１記載の配線基板の前記搭載部に前記半導体素子をフリップチップ接続により搭載したことを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the semiconductor element is mounted on the mounting portion of the wiring board according to claim 1 by flip chip connection.
JP2003394571A 2003-11-25 2003-11-25 Wiring substrate and semiconductor device using the same Expired - Fee Related JP4439248B2 (en)

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