JP2016127134A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which has excellent electric insulation reliability and in which an electric short circuit never occurs between a pad pattern and a solid pattern surrounding the pad pattern.SOLUTION: A wiring board 20 comprises a via hole conductor 10 which is integrally formed direct under a pad pattern 14 and in which a solid pattern 11 and a pad pattern 14 are formed in a loading part 20A of an insulating substrate 1, and a solder resist layer 3 deposited on the insulating substrate 1 including the solid pattern 11 and the pad pattern 14. The interval W2 with the solid pattern 11 in the pad pattern 14 formed integrally with the via hole conductor 10 located at a corner of the loading part 20A is larger than the thickness of the solder resist layer 3 at least on the center side of the loading part 20A.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a wiring board for mounting a semiconductor element.

  FIG. 5 shows a conventional wiring board 40 used for mounting a semiconductor element S such as a semiconductor integrated circuit element. The wiring substrate 40 includes an insulating substrate 21 formed by laminating a plurality of build-up insulating layers 21b on the upper and lower surfaces of the core insulating layer 21a, and wiring conductors disposed inside and above and below the insulating substrate 21. 22 and a solder resist layer 23 deposited on the upper and lower surfaces of the insulating substrate 21 and the wiring conductor 22 thereon.

  A mounting portion 40 </ b> A is provided at the center of the upper surface of the wiring substrate 40. The mounting portion 40A is a quadrangular region for mounting the semiconductor element S. A large number of semiconductor element connection pads 24 are arranged two-dimensionally on the mounting portion 40A. The semiconductor element connection pad 24 is formed by exposing a part of the wiring conductor 22 deposited on the upper surface of the insulating substrate 21 from an opening provided in the solder resist layer 23. Solder bumps B <b> 1 are welded onto the semiconductor element connection pads 24. Then, the electrode T of the semiconductor element S is connected to the semiconductor element connection pad 24 via the solder bump B1.

  The lower surface of the wiring board 40 is a connection surface with the external electric circuit board. On the lower surface of the wiring board 40, a large number of external connection pads 25 are arranged two-dimensionally over substantially the entire area. The external connection pad 25 is formed by exposing a part of the wiring conductor 22 deposited on the lower surface of the insulating substrate 21 from an opening provided in the solder resist layer 23 on the lower surface side. The external connection pad 25 is connected to a wiring conductor of the external electric circuit board through, for example, a solder ball B2.

  A number of through holes 26 are formed in the insulating layer 21a. A through-hole conductor 27 is deposited in the through-hole 26. The wiring conductors 22 on the upper and lower surfaces of the insulating layer 21a are connected to each other through the through-hole conductor 27.

  A large number of via holes 28 are formed in each insulating layer 21b. A via hole conductor 29 is deposited in the via hole 28. Via the via-hole conductors 29, the wiring conductors 22 positioned above and below are connected with the insulating layer 21b interposed therebetween.

  Here, a top view of the uppermost wiring conductor 22 forming the semiconductor element connection pad 24 is shown in FIG. In FIG. 6, only the main part of the uppermost wiring conductor 22 is shown. In FIG. 6, a region surrounded by a two-dot chain line is a region corresponding to the mounting portion 40A.

  The uppermost wiring conductor 22 has a solid pattern 30 extending from a region corresponding to the mounting portion 40A to the periphery thereof. The solid pattern 30 is provided for grounding or power supply. The solid pattern 30 has a pad forming portion 31 at a position indicated by a broken circle in a region corresponding to the mounting portion 40A. By providing an opening portion of the solder resist layer 23 on the pad forming portion 31, a semiconductor element connection pad 24 for grounding or power supply having the same potential as the solid pattern 30 is formed.

  Further, the solid pattern 30 has a large number of pad openings 32 in a region corresponding to the mounting portion 40A. The pad opening 32 is circular. The diameter of the pad opening 32 is 40 to 200 μm. A pad pattern 33 is formed in the pad opening 32. The pad pattern 33 is used for grounding, power supply, or signal having a potential different from that of the solid pattern 30. The pad pattern 33 is circular. The diameter of the pad pattern 33 is 30 to 150 μm. The pad opening 32 and the pad pattern 33 are arranged concentrically. Therefore, a fixed interval W1 is formed between the pad pattern 33 and the solid pattern 30. Thereby, the solid pattern 30 and the pad pattern 33 are electrically insulated from each other. The interval W1 is 5 to 50 μm. By providing an opening of the solder resist layer 23 on the pad pattern 33, a semiconductor element connection pad 24 for grounding, power supply, or signal having a potential different from that of the solid pattern 30 is formed. Note that in many of the pad patterns 33, a via-hole conductor 29 is integrally formed immediately below. Further, in some of the pad patterns 33, the via-hole conductor 29 is not formed immediately below.

  According to this conventional wiring board 40, as shown in FIG. 7, after the electrodes T of the semiconductor element S are connected to the semiconductor element connection pads 24 via the solder bumps B1, the semiconductor element S, the wiring board 40, The space is filled with a sealing resin U made of a thermosetting resin, and finally a solder ball B2 is welded to the external connection pad 25 to complete a semiconductor device as a product. The sealing resin U is filled by injecting a liquid thermosetting resin between the semiconductor element S and the wiring substrate 40 and then thermosetting the resin.

  However, in the conventional wiring board 40, after the solder ball B <b> 2 is welded to the external connection pad 25, an electrical short circuit may occur between the pad pattern 33 and the solid pattern 30. This short circuit occurs due to voids inherent in the solder resist layer 23. When there is a void between the pad pattern 33 and the solid pattern 30 in the solder resist layer 23, the solder of the solder bump B1 flows into the void, and the solder forms the pad pattern 33 and the solid pattern 30 with the solder. The gap is electrically short-circuited.

This short circuit has the following three characteristics.
Feature 1: It occurs only in the pad pattern 33 located at the corner of the mounting portion 40A.
Feature 2: It occurs only in the pad pattern 33 having the via-hole conductor 29 immediately below.
Feature 3: It occurs only on the side of the pad pattern 33 toward the center of the mounting portion 40A.

  The mechanism of occurrence of this short circuit will be described with reference to FIGS. 8A to 8C. FIG. 8A shows a state in which the gap between the semiconductor element S and the wiring substrate 40 is filled with the sealing resin U after the electrode T of the semiconductor element S is connected to the semiconductor element connection pad 24 via the solder bump B1. . The left side of the figure is the direction toward the center of the mounting portion 40A. The pad pattern 33 shown in FIG. 8A is located at the corner of the mounting portion 40A. A via-hole conductor 29 is located immediately below the pad pattern 33. The pad pattern 33 and the via-hole conductor 29 are integrally formed. In the solder resist layer 23, voids V are inherent. The void V is on the side toward the center of the mounting portion 40 </ b> A in the pad pattern 33. The void V is smaller than the thickness of the solder resist layer 23 and is formed between the pad pattern 33 and the solid pattern 30.

  FIG. 8B shows a state in which the wiring board 40 has returned to room temperature after the sealing resin U is filled. The thermal expansion coefficient of the wiring board 40 is larger than the thermal expansion coefficient of the semiconductor element S. Therefore, the wiring board 40 contracts more than the semiconductor element S in the process of returning to room temperature. As a result, stress is generated by the difference in shrinkage. This stress acts largely concentrated on the side of the pad pattern 33 toward the center of the mounting portion 40A. If the void V is present in this part of the solder resist layer 23, partial peeling occurs between the solder resist layer 23 and the pad pattern 33 with the void V as a starting point. At this time, although there is a void V between the pad pattern 33 and the solid pattern 30, the two are completely electrically insulated.

  FIG. 8C shows a state after the solder ball B <b> 2 is welded to the external connection pad 25. When the solder ball B2 is welded, the solder bump B1 is also remelted by the heat. A part of the solder of the re-melted solder bump B <b> 1 flows into the void V through the peeled portion between the solder resist layer 23 and the pad pattern 33. Since the void V is formed across the pad pattern 33 and the solid pattern 30, the solder V flowing into the void V causes an electrical short circuit between the two.

  Note that, in the pad pattern 33 in which the via-hole conductor 29 is not formed immediately below, the peeling from the solder resist layer 23 as described above does not occur. Since the pad pattern 33 in which the via-hole conductor 29 is not formed is not structurally constrained by the via-hole conductor 29, the degree of freedom of deformation is increased. Therefore, it can be appropriately deformed together with the underlying insulating layer 21b to absorb the stress, and as a result, it does not come off from the solder resist layer 23.

JP 2011-249734 A

  The problem to be solved by the present invention is that an electrical short circuit does not occur between the pad pattern and the solid pattern surrounding the pad pattern even if voids are inherent in the solder resist layer. An object of the present invention is to provide a wiring board having excellent insulation reliability.

  The wiring board of the present invention is formed by laminating a plurality of insulating layers, and has an insulating substrate having a rectangular mounting portion on which a semiconductor element is mounted on the upper surface, and is formed on the mounting portion. A solid pattern having a large number of pad openings arranged, a pad pattern arranged in each pad opening with a space between the solid patterns, and the pad pattern integrated with each other A via hole conductor penetrating through the uppermost insulating layer, and deposited on the insulating substrate including the solid pattern and the pad pattern, and a central portion of the pad pattern. And a solder resist layer having an opening that exposes a part of the solid pattern as a semiconductor element connection pad, wherein the wiring substrate is provided at a corner portion of the mounting portion. The interval in the via hole conductors are integrally formed with the pad pattern is characterized in that greater than a thickness of the solder resist layer in the center side of at least the mounting portion.

  According to the wiring board of the present invention, the gap between the solid pattern in the pad pattern formed integrally with the via-hole conductor located at the corner of the mounting portion is at least the thickness of the solder resist layer on the center side of the mounting portion. Greater than. Since the voids in the solder resist layer do not become larger than the thickness of the solder resist layer, even if the voids are present in the large gap portion, the voids are not the pad pattern and the solid pattern. There is no time in between. Therefore, even if solder flows into the void, the pad pattern and the solid pattern are not electrically short-circuited. As a result, according to the wiring board of the present invention, there is provided a wiring board that is excellent in electrical insulation reliability without causing an electrical short circuit between the pad pattern and the solid pattern surrounding the pad pattern. be able to.

  It should be noted that the portion having a large interval between the pad pattern and the solid pattern may be provided only on the center side of the mounting portion in the pad pattern formed integrally with the via-hole conductor located at the corner of the mounting portion. This is because, in the case where the void is present, only this portion is where stress is greatly concentrated and peeling occurs between the solder resist layer. The space between the pad pattern and the solid pattern in the other part may be smaller than the thickness of the solder resist layer. By doing so, a larger area of the solid pattern can be secured. By increasing the area of the solid pattern, the power supply capability to the semiconductor element is improved, and the semiconductor element can be operated more stably.

FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. FIG. 2 is a schematic top view of a main part in an example of the embodiment of the wiring board of the present invention. FIG. 3 is a schematic cross-sectional view of a semiconductor device using an example of an embodiment of a wiring board according to the present invention. FIG. 4 is a schematic cross-sectional view of a main part of a semiconductor device using an example of an embodiment of a wiring board according to the present invention. FIG. 5 is a schematic cross-sectional view showing a conventional wiring board. FIG. 6 is a schematic top view of a main part of a conventional wiring board. FIG. 7 is a schematic cross-sectional view of a semiconductor device using a conventional wiring board. FIG. 8A is a schematic cross-sectional view of a main part for explaining a problem in a conventional wiring board. FIG. 8B is a schematic cross-sectional view of a main part for explaining problems in the conventional wiring board. FIG. 8C is a schematic cross-sectional view of a main part for explaining problems in the conventional wiring board.

  Next, an example of an embodiment of the wiring board of the present invention will be described in detail with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board 20 of the present invention. In FIG. 1, 1 is an insulating substrate, 2 is a wiring conductor, 3 is a solder resist layer, 4 is a semiconductor element connection pad, and 5 is an external connection pad.

  The wiring board 20 of this example includes an insulating substrate 1 in which a plurality of build-up insulating layers 1b are stacked on the upper and lower surfaces of the core insulating layer 1a, and the upper and lower surfaces of the insulating layer 1a and the insulating layers 1b. The wiring conductor 2 is attached, and the outermost insulating layer 1b and the solder resist layer 3 deposited on the wiring conductor 2 are provided.

  A mounting portion 20 </ b> A is provided at the center of the upper surface of the wiring substrate 20. The mounting portion 20A is a quadrangular region for mounting the semiconductor element S. A large number of semiconductor element connection pads 4 are arranged two-dimensionally on the mounting portion 20A. The semiconductor element connection pad 4 is formed by exposing a part of the wiring conductor 2 deposited on the upper surface of the insulating substrate 1 from an opening provided in the solder resist layer 3. The electrode T of the semiconductor element S is connected to the semiconductor element connection pad 4 by flip chip connection. The diameter of the semiconductor element connection pad 4 is about 20 to 100 μm. The arrangement pitch of the semiconductor element connection pads 4 is about 50 to 200 μm.

  The lower surface of the wiring board 20 is a connection surface with the external electric circuit board. A large number of external connection pads 5 are arranged two-dimensionally on the lower surface of the wiring board 20 over substantially the entire area. The external connection pad 5 is formed by exposing a part of the wiring conductor 2 deposited on the lower surface of the insulating substrate 1 from an opening provided in the solder resist layer 3 on the lower surface side. The external connection pad 5 is connected to the wiring conductor of the external electric circuit board through, for example, a solder ball. The diameter of the external connection pad 5 is about 300 to 600 μm. The arrangement pitch of the external connection pads 5 is about 500 to 1000 μm.

  The insulating layer 1a constituting the insulating substrate 1 is a core member in the wiring substrate 20 of this example. The insulating layer 1a is formed, for example, by impregnating a glass fabric in which glass fiber bundles are woven vertically and horizontally with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The thickness of the insulating layer 1a is about 0.1 to 1 mm. A number of through holes 6 are formed in the insulating layer 1a from its upper surface to its lower surface. The diameter of the through hole 6 is about 0.1 to 1 mm. A through-hole conductor 7 is deposited in the through-hole 6. The wiring conductors 2 on the upper and lower surfaces of the insulating layer 1a are connected to each other through the through-hole conductors 7.

  Such an insulating layer 1a is manufactured by thermally curing an insulating sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then drilling the insulating sheet from the upper surface to the lower surface. The wiring conductors 2 on the upper and lower surfaces of the insulating layer 1a are formed in a predetermined pattern by attaching copper foil to the entire upper and lower surfaces of the insulating sheet for the insulating layer 1a and etching the copper foil after the sheet is cured. The The through-hole conductor 7 in the through-hole 6 is formed by depositing a copper plating film on the inner surface of the through-hole 6 by electroless plating and electrolytic plating after providing the through-hole 6 in the insulating layer 1a.

  Furthermore, the inside of the through hole 6 to which the through hole conductor 7 is attached is filled with a hole filling resin 8. The hole filling resin 8 is made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The hole-filling resin 8 is for making it possible to form the wiring conductor 2 and each insulating layer 1b directly above and below the through-hole 6 by closing the through-hole 6. The hole-filling resin 8 is formed by filling an uncured paste-like thermosetting resin into the through-hole 6 by screen printing, thermally curing it, and then polishing its upper and lower surfaces substantially flatly. The

  Each insulating layer 1b laminated on the upper and lower surfaces of the insulating layer 1a is made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. As for the thickness of the insulating layer 1b, each thickness is about 20-60 micrometers. The insulating layer 1b has a plurality of via holes 9 from the upper surface to the lower surface of each layer. The diameter of the via hole 9 is about 30 to 100 μm. A via hole conductor 10 is filled in the via hole 9. The upper wiring conductor 2 and the lower wiring conductor 2 are connected to each other through the via-hole conductor 10.

  Each such insulating layer 1b is formed by sticking an insulating film made of an uncured thermosetting resin having a thickness of about 20 to 60 μm on the upper or lower surface of the insulating layer 1a or the lower insulating layer 1b, and thermosetting it. And via holes 9 are formed by laser processing. The wiring conductor 2 on the surface of each insulating layer 1b and the via-hole conductor 10 in the via hole 9 are formed by depositing copper plating on the surface of each insulating layer 1b and in the via hole 9 each time each insulating layer 1b is formed. The A well-known semi-additive method is used for copper plating deposition.

  The solder resist layer 3 is made of a thermosetting resin having photosensitivity such as an acrylic-modified epoxy resin. The thickness of the solder resist layer 3 is about 10 to 60 μm. The solder resist layer 3 protects the wiring conductor 2 on the outermost layer and connects the semiconductor element connection pad 4 and the external connection pad 5 to the electrode T of the semiconductor element S and the wiring conductor of the external electric circuit board through the opening. Is possible.

  Such a solder resist layer 3 is formed by applying or sticking a photosensitive resin paste or resin film to the surfaces of the uppermost layer and the lowermost insulating layer 1b and using a photolithography technique to expose and develop a predetermined pattern. Then, it is formed by ultraviolet curing and heat curing.

  Here, a top view of the uppermost wiring conductor 2 forming the semiconductor element connection pads 4 is shown in FIG. In FIG. 2, only the main part of the uppermost wiring conductor 2 is shown. In FIG. 2, a region surrounded by a two-dot chain line is a region corresponding to the mounting portion 20A.

  The uppermost wiring conductor 2 has a solid pattern 11 extending from a region corresponding to the mounting portion 20A to the periphery thereof. The solid pattern 11 is used for grounding or power. The solid pattern 11 has a pad forming portion 12 at a position indicated by a broken circle in a region corresponding to the mounting portion 20A. By providing an opening of the solder resist layer 3 on the pad forming portion 12, a grounding or power supply semiconductor element connection pad 4 having the same potential as the solid pattern 11 is formed.

  In addition, the solid pattern 11 has a large number of pad openings 13a and 13b in a region corresponding to the mounting portion 20A. The pad opening 13a is circular. The pad opening 13b is oval. The pad opening 13b is disposed only at the corner of the mounting portion 20A. The diameter of the pad opening 13a and the short diameter of the pad opening 13b are 40 to 200 μm. The major axis of the pad opening 13b is 50 to 250 μm.

  A pad pattern 14 is formed in each of the pad openings 13a and 13b. The pad pattern 14 is used for grounding, power supply, or signal having a potential different from that of the solid pattern 11. The pad pattern 14 is circular. The pad pattern 14 has a diameter of 30 to 150 μm.

  The pad opening 13a and the pad pattern 14 therein are arranged concentrically. Therefore, in the pad opening 13a, a constant interval W1 is formed between the pad pattern 14 and the solid pattern 11. The interval W1 is 5 to 50 μm. The interval W1 is smaller than the thickness of the soldering resist layer 3.

  The pad opening 13b and the pad pattern 14 in the pad opening 13b are more biased toward the center of the mounting portion 20A than the pad pattern 14 is. Therefore, in the pad opening portion 13b, the pad pattern 14 is spaced from the solid pattern by a space W2 wider than the space W1 on the center side of the mounting portion 20A, and on the opposite side is the same as the pad opening portion 13a. The interval W1. The interval W2 is 10 to 80 μm. The interval W2 is larger than the thickness of the solder resist layer 3.

  Then, by providing an opening of the solder resist layer 3 on these pad patterns 14, a semiconductor element connection pad 4 for grounding, power supply, or signal having a potential different from that of the solid pattern 11 is formed. Note that in many of the pad patterns 14, the via-hole conductor 10 is integrally formed immediately below the pad pattern 14. Further, in some of the pad patterns 14, the via-hole conductor 10 is not formed immediately below. In this example, the via-hole conductor 10 is integrally formed immediately below each of the pad patterns 14 formed in the pad openings 13b. Further, the via hole conductor 10 is not formed immediately below the pad pattern 14 formed in the pad opening 13a at the corner of the outermost periphery.

  According to this conventional wiring board 40, as shown in FIG. 3, after the electrodes T of the semiconductor element S are connected to the semiconductor element connection pads 4 via the solder bumps B1, the semiconductor element S and the wiring board 20 are connected. Is filled with a sealing resin U made of a thermosetting resin, and finally, solder balls B2 are welded to the external connection pads 5 to complete a semiconductor device as a product.

  At this time, as described above, according to the wiring board 20 of the present example, the distance between the pad pattern 14 formed integrally with the via-hole conductor 10 located at the corner of the mounting portion 20A and the solid pattern 11 is small. The distance W2 is larger than the thickness of the solder resist layer 3 at least on the center side of the mounting portion 20A. Since the void existing in the solder resist layer 3 does not become larger than the thickness of the solder resist layer 3, even if the void is present in the portion of the large interval W2, as shown in FIG. V does not straddle between the pad pattern 14 and the solid pattern 11. Therefore, even if the solder of the solder bump B1 flows into the void V, the pad pattern 14 and the solid pattern 11 are not electrically short-circuited. As a result, according to the wiring board 20 of the present example, an electrical short circuit does not occur between the pad pattern 14 and the solid pattern 11 surrounding it, and the wiring board is excellent in electrical insulation reliability. 20 can be provided.

  In addition, the part with a large space | interval of the pattern 14 for pads and the solid pattern 11 is only the center side of the mounting part 20A in the pad pattern 14 formed integrally with the via-hole conductor 10 located in the corner | angular part of the mounting part 20A. Should be provided. This is because, in the case where the void V is inherent, the portion where the stress is greatly concentrated and peeling occurs between the solder resist layer 3 is only this portion. The interval between the pad pattern 14 and the solid pattern 11 in other portions may be an interval W1 smaller than the thickness of the solder resist layer 3. By doing so, a larger area of the solid pattern 11 can be secured. By increasing the area of the solid pattern 11, the power supply capability to the semiconductor element S is improved and the semiconductor element S can be operated more stably.

1 .... Insulating substrate 1a, 1b ... Insulating layer 3 .... Solder resist layer 4 .... Semiconductor element connection pad 10 .... via hole Conductor 11 ... Solid pattern 13 ... Pad opening 14 ... Pad pattern 20 ... Wiring board 20A ... .... Mounting part S ... Semiconductor elements W1, W2 ... Spacing

Claims (1)

  An insulating substrate having a rectangular mounting portion on which a semiconductor element is mounted on an upper surface and a plurality of pads formed in the mounting portion and arranged two-dimensionally. A solid pattern having an opening, a pad pattern disposed in the opening for each pad with a space between the solid pattern, and the pad pattern are integrally formed; A via-hole conductor penetrating through the uppermost insulating layer, and deposited on the insulating substrate including the solid pattern and the pad pattern; and a central portion of the pad pattern and one of the solid patterns A solder resist layer having an opening that exposes a portion as a semiconductor element connection pad, wherein the via hole is located at a corner of the mounting portion Wiring board the distance in the body are integrally formed with the pad pattern, which being greater than the thickness of the solder resist layer in the center side of at least the mounting portion.

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