JP4227502B2 - Wiring substrate and semiconductor device using the same - Google Patents
Wiring substrate and semiconductor device using the same Download PDFInfo
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- JP4227502B2 JP4227502B2 JP2003396929A JP2003396929A JP4227502B2 JP 4227502 B2 JP4227502 B2 JP 4227502B2 JP 2003396929 A JP2003396929 A JP 2003396929A JP 2003396929 A JP2003396929 A JP 2003396929A JP 4227502 B2 JP4227502 B2 JP 4227502B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Description
本発明は、半導体素子を搭載するために用いられる配線基板およびこれを用いた半導体装置に関する。 The present invention relates to a wiring board used for mounting a semiconductor element and a semiconductor device using the wiring board.
近年、マイクロプロセッサやＡＳＩＣ（Application Specific Integrated Circuit）等に代表される半導体素子を小型、高密度配線の配線基板上に搭載して成る半導体装置においては、半導体素子の高集積化に伴い、半導体素子の搭載方法として、素子および半導体装置の小型化に対応できるフリップチップ接続による搭載が多用されるようになってきている。 2. Description of the Related Art In recent years, in semiconductor devices in which semiconductor elements typified by microprocessors, ASICs (Application Specific Integrated Circuits), and the like are mounted on a small-sized, high-density wiring substrate, As a mounting method, mounting by flip chip connection, which can cope with the miniaturization of elements and semiconductor devices, has been increasingly used.
このフリップチップ接続による搭載は、半導体素子の電極を半導体素子の下面に格子状の並びに多数配列するとともに、この半導体素子を搭載するための配線基板の上面に半導体素子の電極に対応した配列の接続パッドを設けておき、半導体素子の電極と配線基板の接続パッドとを互いに対向させて半田接続したものである。 Mounting by flip chip connection is performed by arranging a large number of electrodes of the semiconductor element in a lattice form on the lower surface of the semiconductor element, and connecting the array corresponding to the electrode of the semiconductor element on the upper surface of the wiring board for mounting the semiconductor element. Pads are provided, and the electrodes of the semiconductor element and the connection pads of the wiring board are soldered to face each other.
半導体素子が搭載される配線基板としては、主に樹脂製の配線基板が用いられる。この樹脂製の配線基板は、例えばガラス−エポキシ板等から成る絶縁層やエポキシ樹脂等から成る樹脂層を複数層積層して成る絶縁基板の内部および表面に銅箔や銅めっき膜等の導体層から成る配線導体を設けて成る。 As the wiring board on which the semiconductor element is mounted, a resin wiring board is mainly used. This resin wiring board is made of, for example, a conductive layer such as a copper foil or a copper plating film on the inside and the surface of an insulating board formed by laminating a plurality of insulating layers made of glass-epoxy board or the like or a resin layer made of epoxy resin or the like. The wiring conductor which consists of is provided.
配線導体の一部は絶縁基板の上面に露出して半導体素子の電極に接続される半導体素子接続用の接続パッドを形成しているとともに絶縁基板の下面に露出して外部電気回路基板の配線導体に接続される外部接続用の接続パッドを形成している。さらに絶縁基板の表面には接続パッドの中央部を露出させる開口部を有するソルダーレジスト層が被着されている。ソルダーレジスト層は接続パッド間の電気的な絶縁を良好に保つとともに接続パッドを絶縁基体に強固に密着させるための保護層である。そして、ソルダーレジスト層の開口部内に露出した半導体素子接続用の接続パッドと半導体素子の電極とを半田を介して接続することにより半導体素子がフリップチップ接続により配線基板上に搭載されて半導体装置となり、この半導体装置における外部接続用の接続パッドを外部電気回路基板の配線導体に半田を介して接続することによって配線基板上の半導体素子が外部電気回路に電気的に接続されることとなる。 A part of the wiring conductor is exposed on the upper surface of the insulating substrate to form a connection pad for connecting a semiconductor element to be connected to the electrode of the semiconductor element, and is exposed on the lower surface of the insulating substrate to be a wiring conductor of the external electric circuit board A connection pad for external connection connected to is formed. Further, a solder resist layer having an opening exposing the central portion of the connection pad is deposited on the surface of the insulating substrate. The solder resist layer is a protective layer for maintaining good electrical insulation between the connection pads and firmly attaching the connection pads to the insulating substrate. Then, by connecting the connection pad for connecting the semiconductor element exposed in the opening of the solder resist layer and the electrode of the semiconductor element through solder, the semiconductor element is mounted on the wiring board by flip chip connection to become a semiconductor device. By connecting the connection pads for external connection in this semiconductor device to the wiring conductor of the external electric circuit board via solder, the semiconductor elements on the wiring board are electrically connected to the external electric circuit.
このような配線基板における配線導体は、用途によって信号用と接地用と電源用の配線導体に機能化されている。このうち、信号用の配線導体は、半導体素子の電極と外部電気回路基板との間で電気信号を伝播させるための導電路として機能し、絶縁層の層間を絶縁基板の中央部から外周部に向けて延びるように配設された複数の細い帯状の導体パターンを有している。 Wiring conductors in such a wiring board are functionalized into wiring conductors for signals, grounds, and power supplies depending on applications. Of these, the signal wiring conductor functions as a conductive path for propagating an electric signal between the electrode of the semiconductor element and the external electric circuit board, and the interlayer of the insulating layer extends from the central portion to the outer peripheral portion of the insulating substrate. It has a plurality of thin strip-like conductor patterns arranged so as to extend.
また、接地用の配線導体や電源用の配線導体は、配線基板に搭載される半導体素子にそれぞれ接地電位や電源電位を供給するための供給路としての機能を有しているとともに信号用の配線導体に対する電磁シールド機能や特性インピーダンスの調整機能を有しており、絶縁層を挟んで信号用の導体パターンに対向するように配設された広面積の導体パターンを有している。なお、このような広面積の導体パターンは、互いに異なる電位に接続される複数の導体パターンが同じ絶縁層間に隣接して配設されることがある。このような場合、隣接する導体パターン同士は、両者の隣接する縁が平行な直線状の辺で構成されている。
しかしながら、上述のように樹脂製の配線基板に半導体素子をフリップチップ接続により搭載した半導体装置においては、配線基板の剛性が低く変形しやすいことから、配線基板の同じ絶縁層間に複数の広面積の導体パターンが隣接するように配設されている場合、配線基板に半導体素子との熱膨張係数の差に起因する応力が加えられると、その応力が隣接して配設された広面積の導体パターンの隣接する縁と絶縁層との間に集中して作用し、そこを起点として絶縁層およびその上の配線導体にクラックが発生してしまい、その結果、配線導体が断線して半導体素子と配線基板との電気的な接続信頼性が損なわれてしまうという問題点を有していた。 However, in a semiconductor device in which a semiconductor element is mounted on a resin wiring board as described above by flip-chip connection, the rigidity of the wiring board is low and easily deformed. Therefore, a plurality of wide areas are formed between the same insulating layers of the wiring board. When conductor patterns are arranged adjacent to each other, if a stress caused by the difference in thermal expansion coefficient from the semiconductor element is applied to the wiring board, the large area conductor pattern arranged adjacent to the stress. Acts concentrically between the adjacent edges of the insulating layer and the insulating layer, and cracks occur in the insulating layer and the wiring conductor on the insulating layer, and the wiring conductor is disconnected as a result. There has been a problem that the reliability of electrical connection with the substrate is impaired.
本発明は、上記のような問題に鑑み案出されたものであり、その目的は、半導体素子の動作および使用環境温度の変化等により熱が長期間にわたり繰り返し加えられたとしても絶縁基板にクラックが発生することがなく、半導体素子と配線基板との電気的な接続信頼性に優れた半導体装置を提供することにある。 The present invention has been devised in view of the above problems, and its purpose is to crack the insulating substrate even if heat is repeatedly applied over a long period of time due to the operation of the semiconductor element and changes in the operating environment temperature. An object of the present invention is to provide a semiconductor device that is excellent in electrical connection reliability between a semiconductor element and a wiring board.
本発明の配線基板は、複数の絶縁層が積層されて成り、半導体素子が搭載される搭載部を有する絶縁基板と、前記絶縁層の層間に、互いに間隙が形成されるように隣接する第１導体パターン及び第２導体パターンと、を有し、前記第１導体パターン及び前記第２導体パターンの前記間隙に、前記絶縁層の一部が充填されている配線基板であって、前記第１導体パターン及び前記第２導体パターンは、両者の隣接する縁が交互に相手側に入り込む波形であるとともに、前記絶縁層の前記一部との境界部において、その平面形状が丸みを帯びた凸部及び凹部を有するように形成されていることを特徴とするものである。 Wiring board of the present invention, Ri formed by a plurality of insulating layers are laminated, an insulating substrate having a mounting portion on which a semiconductor element is mounted, between the layers of the insulating layer, the second adjacent such that a gap to each other are formed A wiring board having a first conductive pattern and a second conductive pattern, wherein the gap between the first conductive pattern and the second conductive pattern is filled with a part of the insulating layer. The conductor pattern and the second conductor pattern have a waveform in which adjacent edges of the conductor pattern alternately enter the other side, and at the boundary portion with the part of the insulating layer, the planar shape has a rounded convex portion. And it is formed so that it may have a recessed part.
また本発明の半導体装置は、上記の配線基板と、前記配線基板の前記搭載部に搭載されている前記半導体素子と、を有することを特徴とするものである。 According to another aspect of the present invention, there is provided a semiconductor device including the above-described wiring board and the semiconductor element mounted on the mounting portion of the wiring board .
本発明の配線基板およびこれを用いた半導体装置によれば、第１導体パターン及び第２導体パターンは、両者の隣接する縁が交互に相手側に入り込む波形であるとともに、その間隙に充填された絶縁層の一部との境界部において、その平面形状が丸みを帯びた凸部及び凹部を有するように形成されていることから、配線基板と半導体素子との熱膨張係数の差に起因する応力が隣接して配設された広面積の導体パターンと絶縁層の一部との境界部に作用したとしても、その応力は丸みを帯びた凸部及び凹部により良好に分散される。その結果、絶縁層にクラックが発生することが有効に防止され、半導体素子と配線基板との電気的な接続信頼性に優れる半導体装置を提供することができる。
According to the wiring board of the present invention and the semiconductor device using the same, the first conductor pattern and the second conductor pattern have a waveform in which adjacent edges alternately enter the other side, and the gap is filled. The stress caused by the difference in thermal expansion coefficient between the wiring board and the semiconductor element because the planar shape is formed to have rounded convex portions and concave portions at the boundary with a part of the insulating layer. Even if it acts on the boundary between a conductor pattern with a large area and a part of the insulating layer disposed adjacent to each other, the stress is well dispersed by the rounded convex portions and concave portions. As a result, the occurrence of cracks in the insulating layer is effectively prevented, and a semiconductor device having excellent electrical connection reliability between the semiconductor element and the wiring board can be provided.
次ぎに、本発明の配線基板およびこれを用いた半導体装置を添付の図面に基づき詳細に説明する。 Next, a wiring board of the present invention and a semiconductor device using the same will be described in detail with reference to the accompanying drawings.
図１は、本発明の配線基板およびこれに用いた半導体装置の実施の形態例を示す断面図である。図１において１は絶縁基板、２は配線導体であり、主としてこれらで本発明の配線基板が構成され、この配線基板上に半導体素子３が搭載されることにより本発明の半導体装置が構成される。
FIG. 1 is a cross-sectional view showing an embodiment of a wiring board of the present invention and a semiconductor device used therefor. In FIG. 1,
絶縁基板１は、例えばガラス繊維を縦横に織り込んだガラス織物にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させて成る板状の絶縁層１ａの上下面にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る絶縁層１ｂをそれぞれ複数層ずつ積層して成り、その上面の中央部に半導体素子３がフリップチップ接続により搭載される搭載部を有している。そして、その搭載部から下面にかけて銅箔や銅めっき膜等の導体層から成る複数の配線導体２が形成されている。
The
絶縁基板１を構成する絶縁層１ａは、厚みが０．３〜１．５ｍｍ程度であり、その上面から下面にかけて直径が０．２〜１．０ｍｍ程度の複数の貫通孔４を有している。そして、その上下面および各貫通孔４の内面には配線導体２の一部が被着されており、上下面の配線導体２が貫通孔４の内部を介して電気的に接続されている。
The insulating layer 1a constituting the
このような絶縁層１ａは、ガラス織物に未硬化の熱硬化性樹脂を含浸させたシートを熱硬化させた後、これに上面から下面にかけてドリル加工を施すことにより製作される。なお、絶縁層１ａ上下面の配線導体２は、絶縁層１ａ用のシートの上下全面に厚みが５〜５０μｍ程度の銅箔を貼着しておくとともに、この銅箔をシートの硬化後にエッチング加工することにより所定のパターンに形成される。また、貫通孔４内面の配線導体２は、絶縁層１ａに貫通孔４を設けた後に、この貫通孔４内面に無電解めっき法および電解めっき法により厚みが５〜５０μｍ程度の銅めっき膜を析出させることにより形成される。 Such an insulating layer 1a is manufactured by thermally curing a sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then drilling the sheet from the upper surface to the lower surface. In addition, the wiring conductor 2 on the upper and lower surfaces of the insulating layer 1a has a copper foil having a thickness of about 5 to 50 μm adhered to the entire upper and lower surfaces of the sheet for the insulating layer 1a, and this copper foil is etched after the sheet is cured. By doing so, a predetermined pattern is formed. The wiring conductor 2 on the inner surface of the through hole 4 is provided with a copper plating film having a thickness of about 5 to 50 μm by electroless plating and electrolytic plating on the inner surface of the through hole 4 after the through hole 4 is provided in the insulating layer 1a. Formed by precipitation.
さらに、絶縁層１ａは、その貫通孔４の内部にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る樹脂柱５が充填されている。樹脂柱５は、貫通孔４を塞ぐことにより貫通孔４の直上および直下に絶縁層１ｂを形成可能とするためのものであり、未硬化のペースト状の熱硬化性樹脂を貫通孔４内にスクリーン印刷法により充填し、これを熱硬化させた後、その上下面を略平坦に研磨することにより形成される。そして、この樹脂柱５を含む絶縁層１ａの上下面に絶縁層１ｂが積層されている。 Further, the insulating layer 1a is filled with a resin column 5 made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin in the through hole 4 thereof. The resin pillar 5 is for making it possible to form the insulating layer 1b directly above and below the through-hole 4 by closing the through-hole 4, and an uncured paste-like thermosetting resin is placed in the through-hole 4. After filling with a screen printing method and thermosetting it, the upper and lower surfaces thereof are polished to be substantially flat. And the insulating layer 1b is laminated | stacked on the upper and lower surfaces of the insulating layer 1a containing this resin pillar 5. FIG.
絶縁層１ａの上下面に積層された絶縁層１ｂは、それぞれの厚みが２０〜５０μｍ程度であり、各層の上面から下面にかけて直径が３０〜１００μｍ程度の複数のビア孔６を有している。これらの絶縁層１ｂは、配線導体２を高密度に配線するための絶縁間隔を提供するためのものであり、絶縁層１ｂにはその表面およびビア孔６内に配線導体２の一部が被着されている。そして、上層の配線導体２と下層の配線導体２とをビア孔６の内部を介して電気的に接続することにより高密度配線を立体的に形成可能としている。 The insulating layer 1b laminated on the upper and lower surfaces of the insulating layer 1a has a thickness of about 20 to 50 μm, and has a plurality of via holes 6 having a diameter of about 30 to 100 μm from the upper surface to the lower surface of each layer. These insulating layers 1b are provided to provide an insulating interval for wiring the wiring conductors 2 at a high density. The insulating layer 1b is covered with a part of the wiring conductors 2 on the surface and in the via holes 6. It is worn. A high-density wiring can be formed three-dimensionally by electrically connecting the upper wiring conductor 2 and the lower wiring conductor 2 via the inside of the via hole 6.
このような絶縁層１ｂは、厚みが２０〜５０μｍ程度の未硬化の熱硬化性樹脂フィルムを絶縁層１ａの上下面に貼着し、これを熱硬化させるとともにレーザ加工によりビア孔６を穿孔し、さらにその上に同様にして次の絶縁層１ｂを順次積み重ねることによって形成される。なお、各絶縁層１ｂ表面およびビア孔６内に被着された配線導体２は、各絶縁層１ｂを形成する毎に各絶縁層１ｂの表面およびビア孔６内に５〜５０μｍ程度の厚みの銅めっき膜を公知のセミアディティブ法やサブトラクティブ法等のパターン形成法により所定のパターンに被着させることによって形成される。 For such an insulating layer 1b, an uncured thermosetting resin film having a thickness of about 20 to 50 μm is stuck on the upper and lower surfaces of the insulating layer 1a, and this is thermoset, and via holes 6 are drilled by laser processing. Further, it is formed by sequentially stacking the next insulating layer 1b in the same manner. The wiring conductor 2 deposited on the surface of each insulating layer 1b and the via hole 6 has a thickness of about 5 to 50 μm on the surface of each insulating layer 1b and the via hole 6 every time each insulating layer 1b is formed. It is formed by depositing a copper plating film in a predetermined pattern by a pattern forming method such as a known semi-additive method or subtractive method.
さらに、最表層の絶縁層１ｂ上にはソルダーレジスト層７が被着されている。ソルダーレジスト層７は、例えばアクリル変性エポキシ樹脂にシリカやタルク等の無機物粉末フィラーを３０〜７０質量％程度分散させた絶縁材料から成り、表層の配線導体２同士の電気的絶縁信頼性を高めるとともに、後述する接続パッド２ａ、２ｂの絶縁基板１への接合強度を大きなものとする作用をなす。
Further, a solder resist layer 7 is deposited on the outermost insulating layer 1b. The solder resist layer 7 is made of an insulating material in which, for example, an inorganic powder filler such as silica or talc is dispersed in an acrylic-modified epoxy resin in an amount of about 30 to 70% by mass, and improves the electrical insulation reliability between the wiring conductors 2 on the surface layer. The function is to increase the bonding strength of the connection pads 2a and 2b described later to the
このようなソルダーレジスト層７は、その厚みが１０〜５０μｍ程度であり、感光性を有するソルダーレジスト層７用の未硬化樹脂ペーストをロールコーター法やスクリーン印刷法を採用して最表層の絶縁層１ｂ上に塗布し、これを乾燥させた後、露光および現像処理を行なって接続パッド２ａ、２ｂを露出させる開口部を形成した後、これを熱硬化させることによって形成される。あるいは、ソルダーレジスト層７用の未硬化の樹脂フィルムを最上層の絶縁層１ｂ上に貼着した後、これを熱硬化させ、しかる後、接続パッド２ａ、２ｂに対応する位置にレーザ光を照射し、硬化した樹脂フィルムを部分的に除去することによって接続パッド２ａ、２ｂを露出させる開口部を有するように形成される。 Such a solder resist layer 7 has a thickness of about 10 to 50 μm, and an uncured resin paste for the solder resist layer 7 having photosensitivity is applied to the outermost insulating layer by using a roll coater method or a screen printing method. It is formed by applying on 1b and drying it, then performing exposure and development processes to form openings that expose the connection pads 2a, 2b, and then thermally curing them. Alternatively, after an uncured resin film for the solder resist layer 7 is stuck on the uppermost insulating layer 1b, it is thermally cured, and then irradiated with laser light at positions corresponding to the connection pads 2a and 2b. Then, the cured resin film is partially removed to form openings that expose the connection pads 2a and 2b.
絶縁基板１の搭載部から下面にかけて形成された配線導体２は、用途によって信号用と接地用と電源用の配線導体に機能化されている。このうち、信号用の配線導体２は、半導体素子３の電極と外部電気回路基板との間で電気信号を伝播させるための導電路として機能し、絶縁層１ｂの層間を絶縁基板の中央部から外周部に向けて延びるように配設された複数の細い帯状の導体パターンを有している。
The wiring conductor 2 formed from the mounting portion of the insulating
また、接地用の配線導体や電源用の配線導体２は、配線基板に搭載される半導体素子３にそれぞれ接地電位や電源電位を供給するための供給路としての機能を有しているとともに信号用の配線導体２に対する電磁シールド機能や特性インピーダンスの調整機能を有しており、絶縁層１ｂを挟んで信号用の導体パターンに対向するように絶縁層１ｂの層間に配設された広面積の導体パターンを有している。このように接地用や電源用の広面積の導体パターンを信号用の導体パターンと対向するように配設することにより、信号用の配線導体２が電磁的にシールドされるとともに所定の特性インピーダンスに調整される。なお、本例においては、このような広面積の導体パターンは、図２に平面図で示すように、互いに異なる電位に接続される第１の導体パターン２ａおよび第２の導体パターン２ｂが絶縁層１ｂの層間に隣接して配設されており、これらの導体パターン２ａおよび２ｂは、両者の隣接する縁が交互に相手側に入り込む正弦波形状の波形をしている。 In addition, the wiring conductor for grounding and the wiring conductor for power supply 2 have a function as a supply path for supplying a ground potential and a power supply potential to the semiconductor element 3 mounted on the wiring board, respectively, and for signal use. A large-area conductor disposed between the layers of the insulating layer 1b so as to oppose the signal conductor pattern with the insulating layer 1b interposed therebetween, having an electromagnetic shielding function and a characteristic impedance adjusting function for the wiring conductor 2 Has a pattern. Thus, by arranging the large conductor pattern for grounding or power supply so as to oppose the signal conductor pattern, the signal wiring conductor 2 is electromagnetically shielded and has a predetermined characteristic impedance. Adjusted. In this example, as shown in the plan view of FIG. 2, the first conductor pattern 2a and the second conductor pattern 2b, which are connected to different potentials, are formed in such a large area conductor pattern. The conductor patterns 2a and 2b are arranged adjacent to each other between the layers 1b and have a sinusoidal waveform in which the adjacent edges of the two alternately enter the other side.
また、配線導体２は、絶縁基板１の搭載部に露出している部位が半導体素子３の各電極が半田８を介して接続される電子部品接続用の接続パッド２ｃを、絶縁基体１の下面に露出した部位が外部電気回路基板に半田９を介して接続される外部接続用の接続パッド２ｄを形成している。これらの接続パッド２ｃ、２ｄは、絶縁基板１の搭載部および下面において例えば格子状の並びに配列されており、半導体素子３の電極と接続パッド２ｃとが半田８を介して接続されることにより半導体素子３が絶縁基板１の搭載部にフリップチップ接続により搭載された本発明の半導体装置となり、この半導体装置における接続パッド２ｄを外部電気回路基板の配線導体に半田９を介して接続することによって半導体素子３が外部電気回路基板に電気的に接続されることとなる。なお、本例の半導体装置においては、絶縁基板１の搭載部と半導体素子３との間にアンダーフィルと呼ばれる保護樹脂１０が充填されている例を示している。保護樹脂１０は絶縁基板１の搭載部に半導体素子３を半田８を介してフリップチップ接続により搭載した後に、絶縁基板１と半導体素子３との間に未硬化の熱硬化性樹脂ペーストを注入するとともにそのペーストを熱硬化させることにより充填される。なお、絶縁基板１の搭載部に半導体素子３を半田８を介してフリップチップ接続により搭載するには、接続パッド２ｃに半田粉末とフラックスとを含有する半田ペーストをスクリーン印刷法を採用して印刷塗布し、それを２２０〜２６０℃の温度で加熱して半田粉末を溶融させることにより接続パッド２ｃ上に半田バンプ８を予め形成しておき、この半田バンプ８と半導体素子３の電極とを接触させた状態で半田バンプ８を溶融させる方法が採用される。
In addition, the wiring conductor 2 has a portion exposed to the mounting portion of the insulating
そして本発明の配線基板およびこれを用いた半導体装置においては、図２に示すように、絶縁層１ｂの層間に隣接して配設された第１の導体パターン２ａおよび第２の導体パターン２ｂは、両者の隣接する縁が交互に相手側に入り込む波形をしており、そのことが重要である。このように、本発明の配線基板およびこれを用いた半導体装置は、絶縁層１ｂの層間に隣接して配設された第１の導体パターン２ａおよび第２の導体パターン２ｂの隣接する縁が交互に相手側に入り込む波形とされていることから、配線基板と半導体素子３との熱膨張係数の差に起因する応力が第１の導体パターン２ａおよび第２の導体パターン２ｂの隣接する縁と絶縁層１ｂとの間に集中して作用したとしても、その応力は交互に相手側に入り込んだ波形の縁により良好に分散される。その結果、絶縁層１ｂにクラックが発生することが有効に防止され、半導体素子３と配線基板との電気的な接続信頼性に優れる半導体装置を提供することができる。 In the wiring board and the semiconductor device using the same according to the present invention, as shown in FIG. 2, the first conductor pattern 2a and the second conductor pattern 2b arranged adjacent to each other between the insulating layers 1b are It is important that the adjacent edges of both of them have a waveform that alternately enters the other side. Thus, in the wiring board of the present invention and the semiconductor device using the same, the adjacent edges of the first conductor pattern 2a and the second conductor pattern 2b arranged adjacent to each other between the insulating layers 1b are alternately arranged. The stress due to the difference in thermal expansion coefficient between the wiring board and the semiconductor element 3 is insulated from the adjacent edges of the first conductor pattern 2a and the second conductor pattern 2b. Even if acting in a concentrated manner with the layer 1b, the stress is well distributed by the wavy edges that alternately enter the other side. As a result, the generation of cracks in the insulating layer 1b is effectively prevented, and a semiconductor device having excellent electrical connection reliability between the semiconductor element 3 and the wiring board can be provided.
なお、絶縁層１ｂの層間に隣接して配設された第１の導体パターン２ａおよび第２の導体パターン２ｂの隣接する縁における波形は、その山と谷とが丸みを帯びた形状であると、導体パターン２ａおよび２ｂの隣接する縁と絶縁層１ｂとの間に作用する応力を丸みにより極めて良好に分散させることができる。したがって、絶縁層１ｂの層間に隣接して配設された第１の導体パターン２ａおよび第２の導体パターン２ｂの隣接する縁における波形は、その山と谷とが丸みを帯びた形状であることが好ましい。 It should be noted that the waveform at the adjacent edges of the first conductor pattern 2a and the second conductor pattern 2b disposed adjacent to each other between the insulating layers 1b is such that the peaks and valleys are rounded. The stress acting between the adjacent edges of the conductor patterns 2a and 2b and the insulating layer 1b can be dispersed very well by roundness. Therefore, the waveforms at the adjacent edges of the first conductor pattern 2a and the second conductor pattern 2b disposed adjacent to each other between the insulating layers 1b are rounded at the peaks and valleys. Is preferred.
また、絶縁層１ｂの層間に隣接して配置された第１の導体パターン２ａおよび第２の導体パターン２ｂの隣接する縁同士の間隔が５０μｍ未満であると、隣接する導体パターン２ａと２ｂとの電気的な絶縁信頼性が低いものとなってしまい、１００μｍを超えると、絶縁層１ｂの層間に十分な面積の導体パターン２ａおよび２ｂを確保することが困難となる。したがって、絶縁層１ｂの層間に隣接して配置された第１の導体パターン２ａおよび第２の導体パターン２ｂの隣接する縁同士の間隔は５０〜１００μｍの範囲が好ましい。 Moreover, when the space | interval of the adjacent edges of the 1st conductor pattern 2a arrange | positioned adjacent between the layers of the insulating layer 1b and the 2nd conductor pattern 2b is less than 50 micrometers, between the adjacent conductor patterns 2a and 2b The electrical insulation reliability is low, and if it exceeds 100 μm, it is difficult to ensure the conductor patterns 2a and 2b having a sufficient area between the insulating layers 1b. Therefore, the distance between adjacent edges of the first conductor pattern 2a and the second conductor pattern 2b arranged adjacent to each other between the insulating layers 1b is preferably in the range of 50 to 100 μm.
さらに、絶縁層１ｂの層間に隣接して配設された第１の導体パターン２ａおよび第２の導体パターン２ｂの隣接する縁における波形の繰り返し長さが１５０μｍ未満であると、隣接する縁を交互に相手側に入り込ませることが困難となり、６００μｍを超えると、交互に相手方に入り込んだ波形の縁により応力を良好に分散することが困難となる。したがって、絶縁層１ｂの層間に隣接して配設された第１の導体パターン２ａおよび第２の導体パターン２ｂの隣接する縁における波形の繰り返し長さは、１５０〜６００μｍの範囲が好ましい。 Furthermore, when the repetition length of the waveform at the adjacent edges of the first conductor pattern 2a and the second conductor pattern 2b disposed adjacent to each other between the insulating layers 1b is less than 150 μm, the adjacent edges are alternated. It is difficult to get into the other side, and when it exceeds 600 μm, it becomes difficult to disperse the stress satisfactorily by the corrugated edges that alternately enter the other side. Therefore, the repetition length of the waveform at the adjacent edges of the first conductor pattern 2a and the second conductor pattern 2b disposed adjacent to each other between the insulating layers 1b is preferably in the range of 150 to 600 μm.
また、絶縁層１ｂの層間に隣接して配設された第１の導体パターン２ａおよび第２の導体パターン２ｂの隣接する縁における波形の高さが１５０μｍ未満であると、交互に相手方に入り込んだ波形の縁により応力を良好に分散することが困難となり、６００μｍを超えると、第１の導体パターン２ａおよび第２の導体パターン２ｂを効率よく配設することが困難となる。したがって、絶縁層１ｂの層間に隣接して配設された第１の導体パターン２ａおよび第２の導体パターン２ｂの隣接する縁における波形の高さは、１５０〜６００μｍの範囲が好ましい。 In addition, when the height of the waveform at the adjacent edges of the first conductor pattern 2a and the second conductor pattern 2b disposed adjacent to each other between the insulating layers 1b is less than 150 μm, it alternately enters the other party. It becomes difficult to disperse the stress satisfactorily due to the corrugated edges, and when it exceeds 600 μm, it becomes difficult to efficiently dispose the first conductor pattern 2a and the second conductor pattern 2b. Therefore, the height of the waveform at the adjacent edges of the first conductor pattern 2a and the second conductor pattern 2b disposed adjacent to each other between the insulating layers 1b is preferably in the range of 150 to 600 μm.
なお、本発明の配線基板およびこれを用いた半導体装置は、上述の実施の形態例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。例えば上述の実施の形態例では、互いに隣接して配置された第１の導体パターン２ａおよび第２の導体パターン２ｂの相対向する辺は正弦波形状であったが、これらの辺は三角波形状や矩形波形状等の他の形状であってもよい。また、上述の実施の形態例では、第１の導体パターン２ａを第２の導体パターンが取り囲むように配置されていたが、必ずしも一方の導体パターンが他方の導体パターンを取り囲むように配置される必要はない。また、上述の実施の形態例では、同じ絶縁層１ｂ間に２つの導体パターン２ａ、２ｂを配置したが３つ以上の導体パターンを配置してもよい。 The wiring board and the semiconductor device using the wiring board according to the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiment, the opposing sides of the first conductor pattern 2a and the second conductor pattern 2b arranged adjacent to each other have a sine wave shape, but these sides have a triangular wave shape or Other shapes such as a rectangular wave shape may be used. In the above-described embodiment, the first conductor pattern 2a is disposed so as to surround the second conductor pattern, but one conductor pattern is necessarily disposed so as to surround the other conductor pattern. There is no. In the above-described embodiment, the two conductor patterns 2a and 2b are arranged between the same insulating layers 1b. However, three or more conductor patterns may be arranged.
１：絶縁基板
１ｂ：絶縁層
２ａ：第１の導体パターン
２ｂ：第２の導体パターン
３：半導体素子
1: Insulating substrate 1b: Insulating layer 2a: First conductor pattern 2b: Second conductor pattern 3: Semiconductor element
Claims (2)
前記第１導体パターン及び前記第２導体パターンは、両者の隣接する縁が交互に相手側に入り込む波形であるとともに、前記絶縁層の前記一部との境界部において、その平面形状が丸みを帯びた凸部及び凹部を有するように形成されていることを特徴とする配線基板。 Ri plurality of forming the insulating layer are laminated, an insulating substrate having a mounting portion on which a semiconductor element is mounted, between the layers of the insulating layer, the first conductor pattern and the second conductor adjacent to the gap to each other are formed A wiring board in which a part of the insulating layer is filled in the gap between the first conductor pattern and the second conductor pattern,
The first conductor pattern and the second conductor pattern have a waveform in which adjacent edges alternately enter the other side , and the planar shape is rounded at the boundary with the part of the insulating layer. A wiring board characterized in that the wiring board is formed to have a convex portion and a concave portion.
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