JP2014123592A - Process of manufacturing printed wiring board and printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board having high connection reliability.SOLUTION: Neighboring opening 71fc for a pad and opening 71fo for a pad are displaced in an axial direction of a wiring part and are disposed so that an opening adjacent to an opening 1 does not exist in a direction perpendicular to the axial direction. Being disposed apart in terms of distance, a short circuit is hardly generated between the neighboring opening 71fc for a pad and opening 71fo for a pad, and connection reliability with an IC chip may be enhanced.

Description

The present invention relates to a printed wiring board on which a semiconductor element is mounted on an upper surface and a printed wiring board is mounted.

In a small electronic device typified by a portable communication terminal, a mounting space for components constituting an electronic circuit is limited. For this reason, a processing circuit, a control circuit, and the like of an electronic device are generally configured by a wiring board on which a plurality of circuit patterns are formed and electronic components mounted on the wiring board.
For this type of electronic equipment, there is an ever-increasing demand for higher functionality and multi-functionality. Various techniques have been proposed.

  Patent Document 1 discloses a wiring board in which a wide pad is formed at the center of a conductor exposed from an opening of a solder resist layer. In this wiring board, when the electronic component is mounted, the bump of the electronic component can be easily positioned on the pad formed on the conductor.

JP 2000-77471 A

  In Patent Document 1, since the conductor pattern of the wiring board is fine, the liquid underfill material does not spread sufficiently between the electronic component and the wiring board during the coating process with the underfill material, and the electronic component and the wiring A void is generated in the underfill material filled between the plates, and in the vicinity of the void, for example, tin (Sn) melted during reflow is connected in the void, and the conductor patterns may be short-circuited. .

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board having high connection reliability with an IC chip and a manufacturing method thereof.

The printed wiring board of the present invention includes an interlayer resin insulation layer, a first conductor pattern and a second conductor pattern that are arranged adjacent to each other on the interlayer resin insulation layer, the interlayer conductor insulation layer, and the first conductor. A solder resist layer provided on the pattern and on the second conductor pattern;
A first opening provided in the solder resist layer and exposing a part of the first conductor pattern; and a second opening provided in the solder resist layer and exposing a part of the second conductor pattern. A printed wiring board,
The first conductor pattern includes a first pad portion exposed from the first opening, and a first wiring portion extending from the first pad portion,
The second conductor pattern includes a second pad portion exposed from the second opening, and a second wiring portion extending from the second pad portion,
The width of the first pad portion and the width of the first wiring portion are substantially the same,
The width of the second pad part and the width of the second wiring part are substantially the same,
The second opening is not present in a region where the first opening is projected in a direction perpendicular to the direction in which the first wiring portion extends.

The method for producing a printed wiring board of the present invention includes: providing an interlayer resin insulation layer; providing a first conductor pattern and a second conductor pattern adjacent to each other on the interlayer resin insulation layer; A solder resist layer is provided on the resin insulating layer, the first conductor pattern, and the second conductor pattern, and a first opening that exposes a part of the first conductor pattern is provided inside the solder resist layer. And providing a second opening that exposes a part of the second conductor pattern inside the solder resist layer, and a method of manufacturing a printed wiring board comprising:
The first conductor pattern includes a first pad portion exposed from the first opening, and a first wiring portion extending from the first pad portion,
The second conductor pattern includes a second pad portion exposed from the second opening, and a second wiring portion extending from the second pad portion,
The width of the first pad portion and the width of the first wiring portion are substantially the same,
The width of the second pad part and the width of the second wiring part are substantially the same,
The second opening is not formed in a region where the first opening is projected in a direction perpendicular to a direction in which the first wiring portion extends.

  In the printed wiring board of the present invention, the opening of the pad is provided so that the opening adjacent to one opening does not exist in the direction perpendicular to the extending direction of the conductor pattern, and the opening of each pad does not communicate ( Opening is not connected). Therefore, when filling the underfill material, even if a void is generated, a short circuit hardly occurs between adjacent pads, and the connection reliability with the IC chip can be improved.

Process drawing which shows the manufacturing method of the printed wiring board which concerns on 1st Embodiment of this invention. Process drawing which shows the manufacturing method of the printed wiring board of 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board of 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board of 1st Embodiment. Sectional drawing of the printed wiring board of 1st Embodiment. Sectional drawing of the printed wiring board of 1st Embodiment. The top view in the manufacturing process of the printed wiring board which concerns on 1st Embodiment. The top view in the manufacturing process of the printed wiring board which concerns on 1st Embodiment. The bottom view of an IC chip. The partial expanded sectional view of the printed wiring board concerning a 1st embodiment. The partial expanded sectional view of the printed wiring board concerning a 1st embodiment. The partial expanded sectional view of the printed wiring board concerning a 1st embodiment. The partial expanded sectional view of the printed wiring board concerning a 1st embodiment. The top view of the pad of the printed wiring board which concerns on 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board which concerns on 2nd Embodiment. Sectional drawing of the printed wiring board which concerns on 2nd Embodiment. The top view of the printed wiring board which concerns on 2nd Embodiment. The top view of the pad of the printed wiring board which concerns on 3rd Embodiment. The top view of the pad of the printed wiring board which concerns on the 2nd modification of 3rd Embodiment.

[First embodiment]
As shown in FIG. 5, the printed wiring board 10 of the first embodiment has a core substrate 30. The core substrate includes an insulating substrate 20z having a first surface F and a second surface S opposite to the first surface, a first conductor layer 34F formed on the first surface F of the insulating substrate, and the insulating substrate. It has the 2nd conductor layer 34S formed on the 2nd surface. The core substrate further includes a through-hole conductor 36 that connects the first conductor layer 34F and the second conductor layer 34S. The through-hole conductor 36 is formed in the through hole 31 that penetrates the insulating substrate. The shape of the through-hole 31 and the shape of the through-hole conductor 36 are such that each opening having an opening on each surface of the first surface F and the second surface S of the core substrate is tapered toward the center and connected at the center. It is an hourglass shape. The core substrate shown in FIG. 5 is manufactured by a method disclosed in US77786390, for example. The conductor layer of the core substrate includes a plurality of conductor circuits and through-hole lands formed around the through-hole conductors 36. The first surface of the printed wiring board and core substrate and the first surface of the insulating substrate are the same surface, and the second surface of the printed wiring board and core substrate and the second surface of the insulating substrate are the same surface.

  An interlayer resin insulation layer 50F is formed on the first surface F of the core substrate 30 and the first conductor layer 34F. Conductive pattern 58F and first pad portion 59c are formed on interlayer resin insulation layer 50F. The conductor pattern 58F and the first pad portion 59c are connected to the first conductor layer 34F and the through-hole conductor 36 by a via conductor 60F that penetrates the interlayer resin insulating layer 50F. A build-up layer 55F on the first surface side is formed by the interlayer resin insulating layer 50F, the conductor pattern 58F, the first pad portion 59c and the via conductor 60F.

  An interlayer resin insulation layer 50S is formed on the second surface S of the core substrate 30 and the second conductor layer 34S. Conductive pattern 58S is formed on interlayer resin insulation layer 50S. The conductor pattern 58S and the second conductor layer 34S and the through-hole conductor 36 are connected by a via conductor 60S that penetrates the interlayer resin insulating layer 50S. The interlayer resin insulation layer 50S, the conductor pattern 58S, and the via conductor 60S form a buildup layer 55S on the second surface side.

  A solder resist layer 70F is formed on the build-up layer on the first surface side, and a solder resist layer 70S is formed on the build-up layer on the second surface side. The solder resist layer 70F on the first surface side includes a solder bump opening 71F that exposes the upper surface of the conductor pattern 58F and the via conductor (via land) 60F, a recess 70TM for mounting the semiconductor element 90, and a bottom surface 70FM of the recess 70TM. A first opening 71fc is formed to open a part and expose the first pad portion 59c. The solder resist layer 70S on the second surface side has bump openings 71S exposing the upper surfaces of the conductor pattern 58S and the via conductor (via land) 60S.

  The plane of the printed wiring board whose cross section is shown in FIG. 5 is shown in FIG. The printed wiring board 10 is provided on the interlayer resin insulating layer 50F on the first surface side, and includes a first pad portion 59c and a second pad portion 59o for mounting the semiconductor element 90, the first pad portion 59c and the first pad portion 59c. The first opening 71 fc and the second opening 71 fo exposing the surface and part of the side surface of the two-pad portion 59 o and a solder resist layer 70 F having a recess 70 TM for accommodating the semiconductor element 90 therein. The first opening 71 fc and the second opening 71 fo are openings that expose the first pad portion 59 c and the second pad portion 59 o for connection to the pads 92 of the semiconductor element 90, and therefore are recessed portions for accommodating the semiconductor element 90. It exists inside 70TM. Solder plating layers 77 for bonding to the pads 92 of the semiconductor element 90 are formed on the exposed surface and side surfaces of the first pad portion 59c and the second pad portion 59o (FIG. 5). Since the semiconductor element 90 is accommodated in the recess 70TM, the underfill material 96 for fixing the semiconductor element 90 does not flow out from the surface of the printed wiring board 10.

  The conductor pattern 58F formed on the interlayer resin insulation layer 50F includes a first conductor pattern 58Ff1 and a second conductor pattern pattern 58Ff2 which are disposed adjacent to each other. The first conductor pattern 58Ff1 and the second conductor pattern 58Ff2 are arranged in parallel and alternately, and are arranged in the vertical direction toward each side of the printed wiring board (FIG. 7A). The first conductor pattern 58Ff1 and the second conductor pattern 58Ff2 do not necessarily have to be parallel. A solder resist layer 70F is provided on the interlayer resin insulation layer 50F, the first conductor pattern, and the second conductor pattern. In the solder resist layer 70F, a first opening 71fc for exposing a part of the first conductor pattern 58Ff1 and a second opening 71fo for exposing a part of the second conductor pattern 58Ff2 are formed. The first conductor pattern 58Ff1 includes a first pad portion 59c exposed from the first opening 71fc and a first wiring portion 59Ff1 extending from the first pad portion 59c, and the second conductor pattern 58Ff2 The second pad portion 59o exposed from the two openings 71fo and the second wiring portion 59Ff2 extending from the second pad portion 59o are configured (FIG. 7B). Preferably, the width of the first pad portion 59c and the width of the first wiring portion 59Ff1 are substantially the same, and the width of the second pad portion 59o and the width of the second wiring portion 59Ff2 are substantially the same. If the width of the pad portion is increased, the possibility of short-circuiting with an adjacent wiring at the time of IC mounting increases. On the other hand, when the width of the pad portion is reduced, the amount of solder formed on the surface is reduced and connection reliability may be reduced.

  It is desirable that the second opening 71fo does not exist in a region where the first opening 71fc is projected in a direction perpendicular to the extending direction of the first wiring portion 59Ff1. That is, the openings of adjacent pads are not adjacent to each other in the lateral direction, but are spaced apart from each other so as to be displaced in the axial direction (FIGS. 7B, 8B, and 14). . Therefore, even if a plurality of conductor patterns are formed at a fine pitch, the first opening 71fc and the second opening 71fo do not communicate with each other. Short circuiting is unlikely to occur between the first pad portion 59c and the second pad portion 59o, and connection reliability with the IC chip can be improved.

  FIG. 14 shows a plan view of a printed wiring board with an enlarged pad portion. The first opening 71fc and the second opening 71fo have a maximum diameter in the direction perpendicular to the direction in which the first conductor pattern extends, c μm, and a maximum diameter in the direction in which the first conductor pattern extends, d μm. The width of the exposed first conductor pattern is a μm and the distance between the first conductor pattern and the second conductor pattern adjacent to one side; b1 μm; the first conductor pattern and the second conductor pattern adjacent to the other side When the interval is b2 μm, it is desirable to satisfy the relationship of c <d and c <a + b1 + b2. Since only one conductor pattern exists in one opening, it is necessary to satisfy the relationship c <a + b1 + b2. If a plurality of conductor patterns are exposed in one opening, it is presumed that when a void communicating between the conductors is generated when the underfill material is filled, a short circuit of the wiring is caused.

  The shape of the opening is preferably a substantially rectangular or elliptical shape in plan view that satisfies c <d. It is presumed that the connection reliability between the IC chip and the bump is improved by forming the large opening area. Further, it is desirable that the opening has a substantially rectangular shape in a plan view and has four corners in an arc shape (FIG. 14). It seems that when the underfill material is filled, the generation of voids at the corners of the opening can be suppressed.

  The shortest distance between the first opening 71fc and the second opening 71fo; e is preferably 20 μm or more. If the thickness is less than 20 μm, the adhesion area between the solder resist layer 70F and the lower interlayer resin insulation layer 50F between the first opening 71fc and the second opening 71fo is reduced, and it is assumed that peeling occurs (FIG. 14). ).

FIG. 18A shows that the first openings 71fc and the second openings 71fo are regularly arranged in a staggered manner. On the other hand, FIG. 18C shows that the first openings 71fc and the second openings 71fo are irregularly arranged. Even if the first opening 71fc and the second opening 71fo are regularly or irregularly arranged, the shortest distance between the first opening 71fc and the second opening 71fo is 20 μm or more. The first opening 71fc and the second opening 71fo do not communicate with each other, and the solder resist layer 70F and the lower interlayer resin insulation layer 50F do not peel off. The IC chip connected to the first pad portion 59c and the second pad portion 59o exposed in a staggered pattern has pads 92 arranged in a staggered pattern as shown in the bottom view in FIG.

  Only the first conductor pattern 58Ff1 and the second conductor pattern 58Ff2 are exposed at the bottoms of the first opening 71fc and the second opening 71fo, respectively, and the first pad portion 59c and the second pad portion 59o are respectively provided. It is desirable to form. That is, it is desirable that only one conductor pattern is exposed in one opening. If a plurality of conductor patterns are exposed in one opening, it is presumed that when a void communicating between the conductors is generated when the underfill material is filled, a short circuit of the wiring is caused (FIGS. 7B and 8B). ), FIG. 14).

  FIG. 12 shows a cross section of the pad portion. The opening diameter c of the opening is preferably larger than the width of the first pad portion 59c and the second pad portion 59o; Since the first pad portion 59c and the second pad portion 59o expose not only the surface of the conductor pattern but also part or all of the side surfaces, the amount of solder plating formed on the pad surface can be increased and the connection reliability can be improved. . On the other hand, when the opening diameter; c is smaller than the widths of the first pad portion 59c and the second pad portion 59o; the exposed area of the pad portion is small, the amount of solder plating formed on the pad surface is small. Therefore, it is presumed that the connection reliability between the IC chip and the bump is lowered.

The bottom of each of the first opening 71fc and the second opening 71fo is formed from a pad exposing a part of the surface and side surfaces of the first conductor pattern 58Ff1 and the second conductor pattern 58Ff2, and a solder resist layer 70F. It is desirable. FIG. 12 is a cross-sectional view of FIG. The first pad 59c exposed to the first opening 71fc is partially exposed on the surface and side surfaces of the first pad 59c and is filled with a solder resist layer 70F. Therefore, even if a void is generated when the underfill material is filled, it is considered that a short circuit of the wiring due to the void is suppressed (FIG. 13).
Respective bottom portions of the first opening 71fc and the second opening 71fo are pads formed by exposing all surfaces and side surfaces of the first conductor pattern 58Ff1 and the first conductor pattern 58Ff1, respectively. It may be formed from the surface of interlayer resin insulation layer 50F. In FIGS. 15A, 15B, and 16, the first pad portion 59c has the entire surface and side surfaces of the first pad 59c exposed. Since the exposed area of the pad is large, it is possible to increase the amount of solder formed on the surface, and it seems that reliable connection with the terminals of the IC chip is achieved. Even if a void is generated in the first opening 71fc when the underfill material is filled, it is considered that a short circuit of the wiring due to the void is suppressed.

  In FIG. 19, only one opening 71s exists on the signal conductor pattern 58Ffs. It is desirable that only one opening 71s exists on the signal conductor pattern 58Ffs. On the other hand, a plurality of openings 71e and openings 71p exist on the power supply conductor pattern 58Ffp and the ground conductor pattern 58Ffe, respectively. A plurality of openings may be formed on the ground conductor pattern 58Ffe and the power supply conductor pattern 58Ffp. Since a single conductor pattern can be connected to bumps of an IC chip by a plurality of pads, it is considered that the degree of freedom in wiring design is increased. However, when a plurality of pads are formed on one conductor pattern, the pads are preferably the same net.

  The exposed portions of the first pad portion 59c and the second pad portion 59o are at least one selected from the group consisting of Sn plating, Ni / Au plating, Ni / Pd / Au plating, Pd / Ag plating, and OSP film. It is desirable to coat from. An OSP (Organic Solderability Preservative) film can prevent oxidation of exposed portions of the first pad portion 59c and the second pad portion 59o until solder mounting. When the solder is mounted, the OSP layer is removed and does not hinder the electrical connectivity.

[Method for Manufacturing Printed Wiring Board of First Embodiment]
The manufacturing method of the printed wiring board 10 of 1st Embodiment is shown by FIGS.
(1) A double-sided copper-clad laminate 20 comprising a first surface F and an insulating substrate 20z having a second surface S opposite to the first surface and copper foils 22 and 22 laminated on both sides is prepared. (FIG. 1 (A)). ELC4785TH-G manufactured by Sumitomo Bakelite Co., Ltd. can be used as the double-sided copper-clad laminate.

  The insulating substrate 20z is formed of a resin and a reinforcing material, and examples of the reinforcing material include glass cloth, aramid fiber, and glass fiber. Examples of the resin include an epoxy resin and a BT (bismaleimide triazine) resin.

(2) The double-sided copper-clad laminate is processed to complete the core substrate 30 including the through-hole conductor 36, the first conductor layer 34F, and the second conductor layer 34S (FIG. 1B). The first surface of the core substrate 30 and the first surface of the insulating substrate 20z are the same surface, and the second surface of the core substrate 30 and the second surface of the insulating substrate 20z are the same surface. The core substrate 30 is manufactured by the method disclosed in US77786390.

(3) On the first surface F and the second surface S of the core substrate 30, a prepreg containing inorganic fibers, inorganic particles such as silica, and a thermosetting resin such as epoxy, and a copper foil 48 are sequentially laminated. Thereafter, the interlayer resin insulation layer 50F and the interlayer resin insulation layer 50S are formed from the prepreg by heating press, and the copper foil 48 is bonded to the interlayer resin insulation layer (FIG. 1C). Here, an interlayer resin insulation layer including inorganic fibers is laminated, but an interlayer resin insulation layer not including a core material can also be used.

(4) Next, via conductor openings 51F and 51S are formed in the interlayer resin insulation layers 50F and 50S by a CO2 gas laser, respectively (FIG. 1D).

(5) Electroless copper plating layers 52 and 52 are formed on the copper foil 48 and on the inner walls of the openings 51F and 51S (FIG. 2A).

(6) A plating resist 54 is formed on the electroless copper plating layer 52 (FIG. 2B).

(7) An electrolytic copper plating layer 56 is formed on the electroless copper plating layer 52 exposed from the plating resist 54 (FIG. 2C).

(8) The plating resist 54 is removed. By removing the electroless copper plating layer 52 and the copper foil 48 between the electrolytic copper plating layers 56 by etching, the first conductor pattern 58Ff1, the second conductor pattern 58Ff2, the conductor patterns 58F, 58S and the vias having a layer thickness of 18 μm are formed. Conductors 60F and 60S are formed (FIG. 2D). The first conductor pattern 58Ff1 and the second conductor pattern 58Ff2 each have a pattern width of 15 μm, and the two patterns are alternately formed at equal intervals of 25 μm (FIG. 7A). The via conductors 60F and 60S include via lands 60FR and 60SR. Build-up layers 55F and 55S on the first surface side and the second surface side are formed. A plan view of the printed wiring board of FIG. 2D is shown in FIG. FIG. 2D corresponds to the X1-X1 cross section in FIG. A part of the first conductor pattern 58Ff1 and the second conductor pattern 58Ff2 is exposed from the solder resist layer 70F to be coated in a later process, and the first pad portion 59c, the second pad portion 59o, the first wiring portion 59Ff1, and the second conductor pattern 58Ff2 are exposed. The wiring portion 59Ff2 is configured.

(9) The solder resist composition 70F on the first surface F side is formed on the buildup layer on the first surface F side, and the solder resist composition on the second surface S side is formed on the buildup layer on the second surface S side. 70S is formed (FIG. 3A). The solder resist composition 70F is made of, for example, an epoxy resin that can be multistaged and disclosed in JP2011-71406A.

(10) The first exposure mask 80 is placed on the solder resist composition 70F, and exposure is performed (FIG. 3B). The first exposure mask is provided with black spots 80a corresponding to uncured portions (FIG. 3B). By the exposure using the first exposure mask, the solder resist layer 70F covering the via conductor 60F and the via land 60FR at the peripheral edge of the printed wiring board 10 is cured into a frame shape, and the upper portion of the pad for connection with the memory mounting board is It becomes uncured without being exposed (FIG. 3B). Although not shown, the solder resist composition 70S on the second surface side is similarly cured. In addition, you may use the exposure method which scans a light source and does not use an exposure mask and irradiates an unhardened soldering resist composition for exposure.

(11) A first opening step is performed in which the uncured solder resist compositions 70F and 70S that are not cured by the exposure in the previous step are etched by the etchant. At this time, the concave surface 70TM, the concave bottom surface 70FM, the opening 71F, and the uppermost surface 70FT of the portion cured by exposure are formed on the first surface F side (FIG. 3C). The depth of the recess 70TM and the opening of the opening 71F is adjusted by the etching time. As the etching solution, for example, the one disclosed in JP2011-71406A is used.

(12) The second exposure mask 82 is placed on the solder resist composition 70F, and exposure is performed. The second exposure mask is provided with black spots 82a corresponding to uncured portions (FIG. 3D). The positions of the black spots 82a of the second exposure mask are above the opening 71F and above the planned opening position for arranging the first opening 71fc and the second opening 71fo in a staggered manner as shown in FIG. 7B. Correspond. By the exposure using the second exposure mask, the solder resist composition 70F of the recess bottom surface 70FM other than the opening 71F and the first opening 71fc and the second opening 71fo is cured. That is, the solder resist composition 70F above the first wiring portion 59Ff1 and the second wiring portion 59Ff2 is cured.

  In the first embodiment, the first conductor pattern 58Ff1 and the second conductor pattern 58Ff2 are formed so that the pattern width is 15 μm and the two patterns are alternately present at equal intervals of 25 μm. The first opening 71fc and the second opening 71fo are formed to have a diameter in a direction perpendicular to the extending direction of the first conductor pattern 58Ff1 and the second conductor pattern 58Ff2; c: 40 μm, a diameter in the extending direction; d: 60 μm Has been. The opening shape is substantially rectangular in plan view, and the four corners are arc-shaped. Further, the shortest distance e between the first opening 71fc and the second opening 71fo is 30 μm. The shortest distance is preferably 20 μm or more. If the thickness is less than 20 μm, the adhesion area between the interlayer resin insulation layer 50F and the solder resist layer 70F is small, and peeling due to stress may occur.

  The first pad portion and the second pad portion exposed in the first opening 71fc and the second opening 71fo, respectively, adjust the etching time of the etching solution so that the surface portion and part of both side surfaces of the wiring are exposed. (FIG. 4 (A)). By exposing a part of the surface and both side surfaces, it becomes possible to deposit a lot of Sn plating formed on the surface of the exposed portion. Here, in the printed wiring board of the first embodiment, the maximum diameter in the direction perpendicular to the direction in which the conductor pattern extends; c μm, the maximum diameter in the direction in which the conductor pattern extends; d, the conductor pattern exposed through the opening. Width: a μm and the distance between the first conductor pattern and the second conductor pattern adjacent to one side; b1 μm, the distance between the first conductor pattern and the second conductor pattern adjacent to the other side; b2 μm , C <d and c <a + b1 + b2.

(13) A second opening process is performed in which the uncured solder resist composition 70F that is not cured by the exposure in the previous process is etched by the etching solution (FIG. 4A). At this time, a concave bottom surface 70FM, a first opening 71fc, and a second opening 71fo (not shown) cured by exposure are formed on the first surface side, and a first pad portion 59c and a second pad portion 59o (not shown) are formed. )) And a part of the side surface are exposed. At this time, the surface of the first pad portion 59c and the second pad portion 59o (not shown) and the entire side surface may be exposed, and at the same time, the surface of the interlayer resin insulating layer 50F may be exposed (FIGS. 15 and 16). At the same time, openings 71F for solder bumps are formed on the uppermost surface 70FT to expose the pads 71FO, and openings 71S are formed in the solder resist layer 70S on the second surface side to expose the pads 71SO (FIG. 4A). Then, the solder resist composition is heated and cured to form solder resist layers 70F and 70S. A plan view of the printed wiring board of FIG. 4A is shown in FIG. 4A corresponds to the X2-X2 cross section of FIG. Thereby, the solder resist layer 70F having the recess 70TM, the first opening 71fc, the second opening 71fo (not shown), the uppermost surface 70FT, and the recess bottom surface 70FM is completed.

(14) A nickel plating layer 72 is formed on the exposed portions of the pad 71FO and the pad 71SO, and a gold plating layer 74 is formed on the nickel plating layer 72 (FIG. 4B). Instead of the nickel-gold layer (Ni / Au), Sn plating, nickel-palladium-gold layer (Ni / Pd / Au), Pd / Ag plating, OSP (Organic Solderability Preservative) film may be formed.

(15) Solder plating 77 is formed on the surfaces of the pad portions 59c and 59o (not shown) (FIG. 4). As the solder plating 77, Sn plating is selected. As the solder plating 77, Sn plating, nickel-gold layer (Ni / Au), nickel-palladium-gold layer (Ni / Pd / Au), and OSP film may be formed.

(16) Solder balls are mounted on the pads 71FO of the solder resist layer 70F and the pads 71SO of the solder resist layer 70S, and solder bumps 76F and 76S are formed by reflow to complete the printed wiring board (FIG. 5).

The semiconductor element 90 is mounted via the first pad portion 59c and the second pad portion 59o. As shown in FIG. 12B, a conductor post 92 is formed on the lower surface of the semiconductor element 90, and solder 94 is provided at the tip of the conductor post 92.

  As shown in FIG. 10B in which the Y1-Y1 cross section in FIGS. 12C and 12C is enlarged, a conductor post 92, a first pad portion 59c, and a second pad portion 59o (not shown). Are connected via the solder plating 77 and the solder 94, and the semiconductor element 90 is mounted.

  As shown in FIG. 6, an underfill material 96 is filled between the semiconductor element 90 and the solder resist layer 70F. In the first embodiment, the first pad portion 59c and the second pad portion 59o (not shown) are arranged in a staggered manner (FIGS. 7B and 8B), and therefore the underfill material 96 Even if voids occur when filling the wire, it is considered that the short circuit of the wiring due to the voids is suppressed.

  The printed wiring board 110 is mounted via the solder bumps 76F. Then, the printed wiring board 10 is mounted on the mother board 120 via the solder bumps 76S (FIG. 6). A plan view of FIG. 6 is shown in FIG. 6 corresponds to the X3-X3 cross section in FIG.

[Second Embodiment]
FIG. 16 is a cross-sectional view of a printed wiring board according to the second embodiment, and FIG. 17 is a plan view of the printed wiring board.
In the printed wiring board of the second embodiment, the first opening 71fc and the second opening 71fo formed in the solder resist layer 70F penetrate through the solder resist layer 70F and part of the surface of the first interlayer resin insulation layer 50F. Exposed. The first openings 71fc and the second openings 71fo are arranged in a staggered manner as in the first embodiment.

FIG. 15 shows a manufacturing process of the printed wiring board according to the second embodiment.
The first opening 71fc and the second opening 71fo that are manufactured in the same manner as the printed wiring board of the first embodiment shown in FIGS. 1 to 3 and reach the surface of the first interlayer resin insulation layer 50F are formed in the solder resist layer 70F. It is formed (FIG. 15A). The subsequent manufacturing process is the same as that of the first embodiment. Since the printed wiring board of the second embodiment removes without leaving the solder resist composition 70F at the bottom in the exposure / development process of the first opening 71fc and the second opening 71fo, as in the first embodiment. The step of curing the solder resist composition 70F at the bottom of the first opening 71fc and the second opening 71fo can be omitted. Further, since both side surfaces of the first pad portion and the second pad portion are all exposed, it is possible to form a large number of plating layers on the surfaces of the first pad portion and the second pad portion, and the reliability is high. Implementation is possible.

[Third embodiment]
FIG. 18B shows pad openings formed in the solder resist layer 70F according to the third embodiment. In the first and second embodiments, as shown in FIG. 18A, the first pad portion 59c and the second pad portion 59o are arranged in a two-stage zigzag pattern. In contrast, in the third embodiment, the pad openings are displaced along the first wiring portion 59Ff1 and the second wiring portion 59Ff2 in three stages.

[First Modification of Third Embodiment]
FIG. 18C shows pad openings formed in the solder resist layer 70F according to the first modification of the third embodiment. In the first modified example of the third embodiment, the pad opening is randomly displaced along the first wiring portion 59Ff1 and the second wiring portion 59Ff2.

  FIG. 19 shows a pad opening formed in the solder resist layer (70F) according to the second modification of the third embodiment. In the third embodiment, a signal wiring portion 58Ffs, a ground wiring portion 58Ffe, and a power supply wiring portion 58Ffp are provided. One pad opening 71s is provided in the signal wiring portion 58Ffs. One or more pad openings 71e and 71p are provided in the ground wiring portion 58Ffe and the power supply wiring portion 58Ffp.

In the above-described embodiment, an example in which the configuration of the present invention is applied to a build-up multilayer board is illustrated, but the configuration of the present invention can be applied to various printed wiring boards.

30 core substrate 50F first interlayer resin insulation layer 50S second interlayer resin insulation layer 58F first conductor pattern 58Ff pad pattern 59c, 59o pad 70F solder resist layer 70TM recess 71fc, 71fo pad opening 71F opening 76F solder bump 77 solder 90 semiconductor element

Claims (20)

An interlayer resin insulation layer;
On the interlayer resin insulation layer, a first conductor pattern and a second conductor pattern arranged adjacent to each other;
A solder resist layer provided on the interlayer resin insulation layer, on the first conductor pattern and on the second conductor pattern;
A first opening provided in the solder resist layer and exposing a part of the first conductor pattern;
A printed wiring board provided in the solder resist layer and having a second opening exposing a part of the second conductor pattern,
The first conductor pattern includes a first pad portion exposed from the first opening, and a first wiring portion extending from the first pad portion,
The second conductor pattern includes a second pad portion exposed from the second opening, and a second wiring portion extending from the second pad portion,
The width of the first pad portion and the width of the first wiring portion are substantially the same,
The width of the second pad part and the width of the second wiring part are substantially the same,
The printed wiring board, wherein the second opening does not exist in a region where the first opening is projected in a direction perpendicular to a direction in which the first wiring portion extends. The printed wiring board according to claim 1,
Only the first conductor pattern is exposed at the bottom of the first opening. The printed wiring board according to claim 1,
The diameter of the first opening is larger than the width of the first pad portion. The printed wiring board according to claim 1 or claim 2,
A maximum diameter in a direction perpendicular to the direction of extension of the first conductor pattern; c μm, a maximum diameter in a direction of extension of the first conductor pattern; d, a width of the first conductor pattern exposed by the opening; When the distance between the first conductor pattern and the second conductor pattern adjacent to one side is b1 μm, the distance between the first conductor pattern and the second conductor pattern adjacent to the other side is b2 μm,
c <d and c <a + b1 + b2
Satisfy the relationship. The printed wiring board according to claim 1,
The opening is substantially rectangular or elliptical in plan view. The printed wiring board according to claim 4,
The opening has a substantially rectangular shape in plan view and has four corners in an arc shape. The printed wiring board according to claim 1,
The distance between the opening 1 and the opening 2 is 20 μm or more. The printed wiring board according to claim 1,
There are a plurality of the first openings. The printed wiring board according to claim 7,
The first conductor pattern is a power supply conductor or a ground conductor. The printed wiring board according to claim 1,
There is only one first opening. The printed wiring board according to claim 9,
The first conductor pattern is a signal conductor. The printed wiring board according to claim 1,
The bottom of the first opening is formed of a pad formed by exposing a part of the surface and side surfaces of the first conductor pattern, and a solder resist layer. The printed wiring board according to claim 1,
The bottom of the first opening is formed from a pad formed by exposing all of the surface and side surfaces of the first conductor pattern and the surface of the interlayer resin insulation layer. The printed wiring board according to claim 1,
The exposed portion of the first pad portion is covered with at least one selected from the group consisting of Sn plating, Ni / Au plating, Ni / Pd / Au plating, Pd / Ag plating, and OSP film. Providing an interlayer resin insulation layer;
Providing the first conductor pattern and the second conductor pattern disposed adjacent to each other on the interlayer resin insulation layer;
Providing a solder resist layer on the interlayer resin insulation layer, on the first conductor pattern and on the second conductor pattern;
Providing a first opening for exposing a part of the first conductor pattern inside the solder resist layer;
Providing a second opening exposing a part of the second conductor pattern inside the solder resist layer;
A printed wiring board manufacturing method comprising:
The first conductor pattern includes a first pad portion exposed from the first opening, and a first wiring portion extending from the first pad portion,
The second conductor pattern includes a second pad portion exposed from the second opening, and a second wiring portion extending from the second pad portion,
The width of the first pad portion and the width of the first wiring portion are substantially the same,
The width of the second pad part and the width of the second wiring part are substantially the same,
The second opening is not formed in a region where the first opening is projected in a direction perpendicular to a direction in which the first wiring portion extends. A method for producing a printed wiring board according to claim 14,
When providing the first opening, at least a part of the surface and the side surface of the first conductor pattern is exposed. A method for producing a printed wiring board according to claim 14,
When providing the first opening, only the surface and part of the side surface of the first conductor pattern are exposed, and the surface of the interlayer insulating layer is not exposed. A method for producing a printed wiring board according to claim 14,
The solder resist layer in the opening is exposed and cured. A method for producing a printed wiring board according to claim 14,
When providing the first opening, the surface of the interlayer insulating layer is exposed. A method for producing a printed wiring board according to claim 14,
The surface of the first pad portion exposed from the first opening is at least one selected from the group consisting of Sn plating, Ni / Au plating, Ni / Pd / Au plating, Pd / Ag plating, and OSP film. Cover.

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