JPS58182430U - Flat package integrated circuit mounting equipment - Google Patents

Flat package integrated circuit mounting equipment

Info

Publication number
JPS58182430U
JPS58182430U JP7839682U JP7839682U JPS58182430U JP S58182430 U JPS58182430 U JP S58182430U JP 7839682 U JP7839682 U JP 7839682U JP 7839682 U JP7839682 U JP 7839682U JP S58182430 U JPS58182430 U JP S58182430U
Authority
JP
Japan
Prior art keywords
integrated circuit
flat package
package integrated
circuit mounting
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7839682U
Other languages
Japanese (ja)
Inventor
豊沢　正夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP7839682U priority Critical patent/JPS58182430U/en
Publication of JPS58182430U publication Critical patent/JPS58182430U/en
Pending legal-status Critical Current

Links

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のフラットパッケージ集積回路数　　　　
−付装置の平面図、第２図はフラットパッケージ集積回
路をはんだ付した断面図、第３図ははんだ付を説明する
部分拡大平面図、第４図はこの考案の一実施例を示す平
面図、第５図ははんだ付を説明する部分拡大平面図であ
る。 図中、１１は取付装置、１２は基板、１５ははんだ付ラ
ンド、１６はレジスト膜、１７は集積回路、１８はリー
ド端子である。Figure 1 shows the number of conventional flat package integrated circuits
- A plan view of the attachment device; Fig. 2 is a sectional view of a flat package integrated circuit soldered; Fig. 3 is a partially enlarged plan view illustrating soldering; and Fig. 4 is a plan view showing an embodiment of the invention. , FIG. 5 is a partially enlarged plan view illustrating soldering. In the figure, 11 is a mounting device, 12 is a substrate, 15 is a soldering land, 16 is a resist film, 17 is an integrated circuit, and 18 is a lead terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板に設けたはんだ付ランドにフラットパッケージ集積
回路のリード端子をはんだ付するフラットパッケージ集
積回路取付装置において、前記はんだ付ランドの幅を前
記リード端子の幅よりも広くし、かつ隣接する前記はん
だ付ランドを所定間隔離間して千鳥状に配設したことを
特徴とするフラットパッケージ集積回路取付装置。In a flat package integrated circuit mounting device for soldering lead terminals of a flat package integrated circuit to soldering lands provided on a board, the width of the soldering land is made wider than the width of the lead terminal, and the width of the soldering land is made wider than the width of the lead terminal, and A flat package integrated circuit mounting device characterized in that lands are arranged in a staggered manner with lands separated by predetermined intervals.
JP7839682U 1982-05-29 1982-05-29 Flat package integrated circuit mounting equipment Pending JPS58182430U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7839682U JPS58182430U (en) 1982-05-29 1982-05-29 Flat package integrated circuit mounting equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7839682U JPS58182430U (en) 1982-05-29 1982-05-29 Flat package integrated circuit mounting equipment

Publications (1)

Publication Number Publication Date
JPS58182430U true JPS58182430U (en) 1983-12-05

Family

ID=30087614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7839682U Pending JPS58182430U (en) 1982-05-29 1982-05-29 Flat package integrated circuit mounting equipment

Country Status (1)

Country Link
JP (1) JPS58182430U (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61186227U (en) * 1985-05-13 1986-11-20
JPH0623278U (en) * 1992-07-02 1994-03-25 小島プレス工業株式会社 Printed wiring board
JP2001120501A (en) * 1999-10-28 2001-05-08 Olympus Optical Co Ltd Solid image pickup device
JP2014123592A (en) * 2012-12-20 2014-07-03 Ibiden Co Ltd Process of manufacturing printed wiring board and printed wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61186227U (en) * 1985-05-13 1986-11-20
JPH0623278U (en) * 1992-07-02 1994-03-25 小島プレス工業株式会社 Printed wiring board
JP2001120501A (en) * 1999-10-28 2001-05-08 Olympus Optical Co Ltd Solid image pickup device
JP2014123592A (en) * 2012-12-20 2014-07-03 Ibiden Co Ltd Process of manufacturing printed wiring board and printed wiring board

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