JP2009043845A - Wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board for which an electric test can be easily and securely conducted by connecting a probe for the electric test. <P>SOLUTION: The wiring board 10 has: a plurality of beltlike wiring conductors 5a arranged in parallel on an outermost insulating layer 4; a conductive projection 12 for a flip chip, which is formed on part of each beltlike wiring conductor 5a and has the same width with that of the beltlike wiring conductor 5a; and a solder resist layer 6 for exposing at least a top surface of the conductive projection 12 for the flip chip, the resist layer 6 being formed covering the outermost insulating layer 4 and beltlike wiring conductors 5a, A conductive projection 13 for the test, to which the probe for the electric test is to be connected, is formed at part on each beltlike wiring conductor 5a, the conductive projection 13 having the same width as that of the beltlike wiring conductor 5a while shifting in position from an adjacent conductive projection 13 for the test, and a top surface of each conductive projection 13 for the test is exposed from the solder resist layer 6. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wiring board, and more particularly to a wiring board suitable for mounting, for example, a peripheral type semiconductor integrated circuit element by flip chip connection.

  2. Description of the Related Art Conventionally, as a semiconductor integrated circuit element, there is a so-called peripheral type semiconductor integrated circuit element in which a large number of electrode terminals are arranged along the outer periphery of one main surface thereof. As a method of mounting such a semiconductor integrated circuit element on a wiring board, there is a method of connecting by flip chip connection. Flip-chip connection means that a part of a wiring conductor for connecting a semiconductor element provided on a wiring board is exposed corresponding to the arrangement of electrode terminals of a semiconductor integrated circuit element, and an exposed portion of the wiring conductor for connecting a semiconductor element is exposed. And the electrode terminal of the semiconductor integrated circuit element are opposed to each other and are electrically connected through conductive bumps such as solder.

  FIG. 8 is a schematic cross-sectional view showing a conventional wiring board on which peripheral type semiconductor integrated circuit elements are mounted by flip-chip connection, and FIG. 9 is a plan view showing the wiring board of FIG. As shown in FIGS. 8 and 9, the conventional wiring board 120 includes an insulating layer 104 and a second wiring conductor 105 on the upper and lower surfaces of the insulating board 103 on which the first wiring conductor 102 is disposed from the upper surface to the lower surface. Are alternately laminated, and a protective solder resist layer 106 is deposited on the outermost surface.

  A plurality of through holes 107 are formed from the upper surface to the lower surface of the insulating substrate 103, and the first wiring conductor 102 is attached to the upper and lower surfaces of the insulating substrate 103 and the inner surface of the through hole 107. Is filled with embedded resin 108. A plurality of via holes 109 are respectively formed in the insulating layer 104, and second wiring conductors 105 are formed on the surface of each insulating layer 104 and the inner surface of the via hole 109, respectively.

  A part of the plurality of second wiring conductors 105 deposited on the outermost insulating layer 104 on the upper surface side of the wiring board 120 is connected to the electrode terminals of the semiconductor integrated circuit element 101 via the conductive bumps 110. A strip-shaped wiring conductor 105a for connecting a semiconductor element electrically connected to each other is configured, and the electrode terminal of the semiconductor integrated circuit element 101 is soldered or exposed to an exposed portion of the strip-shaped wiring conductor 105a exposed from the solder resist layer 106. They are electrically connected via conductive bumps 110 made of gold or the like. In addition, a part of the lower surface side of the wiring board 120 that is deposited on the outermost insulating layer 104 constitutes a wiring conductor 105b for external connection that is electrically connected to the wiring conductor of the external electric circuit board, Of the wiring conductor 105b for external connection, the wiring conductor of the external electric circuit board is electrically connected to the exposed portion exposed from the solder resist layer 106 through the solder ball 111.

  The solder resist layer 106 protects the outermost second wiring conductor 105 and defines the exposed portions of the strip-shaped wiring conductor 105a and the wiring conductor 105b. Such a solder resist layer 106 is formed by laminating a photosensitive thermosetting resin paste or film on the outermost insulating layer 104 on which the second wiring conductor 105 is formed, and then forming the strip-shaped wiring conductor 105a or the wiring conductor. It is formed by exposing, developing and curing so as to have an opening for exposing the exposed portion in 105b. For this reason, the exposed part in the strip-shaped wiring conductor 105 a is located recessed from the surface of the solder resist layer 106. As shown in FIG. 9, the solder resist layer 106 on the upper surface side has a slit-shaped opening 106a that exposes the exposed portion of the strip-shaped wiring conductor 105a.

  Then, after electrically connecting the electrode terminal of the semiconductor integrated circuit element 101 and the exposed portion of the strip-shaped wiring conductor 105a via the conductive bump 110, an epoxy resin is formed in the gap between the semiconductor integrated circuit element 101 and the wiring board 120. The semiconductor integrated circuit element 101 is mounted on the wiring substrate 120 by filling a filling resin 112 called an underfill made of a thermosetting resin such as the like.

  Recently, the integration density of the semiconductor integrated circuit element 101 has rapidly increased, and the pitch of the electrode terminals in the semiconductor integrated circuit element 101 has become narrower. With this, the width of the strip-shaped wiring conductor 105a has also increased. It is getting narrower. When the width of the strip-shaped wiring conductor 105a is narrowed, the conductive bump 110 formed on the exposed portion of the strip-shaped wiring conductor 105a must be small, and the exposed portion of the strip-shaped wiring conductor 105a and the conductive bump 110 are reduced. Connection reliability decreases. Further, when the semiconductor integrated circuit element 101 is mounted through the small conductive bumps 110, the gap between the semiconductor integrated circuit element 101 and the solder resist layer 106 is narrowed. As a result, the filling property of the filling resin 112 decreases and voids are easily generated in the filled resin 112.

  Therefore, the present applicant has previously developed a wiring board as described in Patent Document 1. This wiring board is provided with conductive protrusions for flip-chip on a part of a plurality of strip-shaped wiring conductors arranged side by side on the outermost insulating layer with a width that matches the width of the strip-shaped wiring conductor, and the upper surface of each conductive protrusion. A solder resist layer is deposited so as to be exposed. According to this wiring board, the conductive protrusion is excellent in connection reliability between the conductive protrusion and the conductive bump formed on the surface of the conductive protrusion, and the height difference between the conductive protrusion and the solder resist layer is reduced, so that the filling resin is filled. It is possible to flip-chip mount a semiconductor integrated circuit element having excellent characteristics and electrode terminals with a narrow pitch through minute conductive bumps.

  On the other hand, the manufactured wiring board is subjected to an electrical test using an electrical test probe. For example, in the wiring board described in Patent Document 1, an electrical test is performed by connecting a probe for electrical testing to each conductive protrusion. However, as described above, with the narrow pitch of the electrode terminals in the semiconductor integrated circuit element, the width of the conductive protrusions (that is, the band-shaped wiring conductor) and the interval between the adjacent conductive protrusions (that is, between the band-shaped wiring conductors) are also narrowed. Yes.

  In general, the diameter of the probe used for the electrical test is larger than the width of the strip-shaped wiring conductor and is almost the same as the interval between the adjacent strip-shaped wiring conductors. For this reason, there is a problem that connection failure occurs between the probe for electrical test and the conductive protrusion on the wiring board. Moreover, probes are brought into contact with each other and short circuit failures frequently occur, and a yield reduction due to a so-called pseudo failure, which is a defective product even if it is an acceptable product, is increasing. Note that it is very difficult to minimize the probe diameter for electrical testing and to improve the position accuracy.

  Patent Document 2 describes a printed wiring board in which a predetermined region on a plurality of electronic device connection pads arranged in parallel is exposed from a solder resist layer to form a predetermined electrical inspection region.

  However, since the pads constituting the electrical inspection region described in this document are exposed from the solder resist layer, when the pad width and the interval between adjacent pads are narrow, As described above, poor connection occurs between the probe for electrical testing and the pad, and the probes come into contact with each other, resulting in frequent short circuits.

JP 2006-344664 A JP-A-9-191169

  The subject of this invention is providing the wiring board which can perform an electrical test simply and reliably by connecting the probe for an electrical test.

  As a result of intensive studies to solve the above problems, the present inventors have conducted a test in which a probe for electrical testing is connected to a part of each of the strip-shaped wiring conductors arranged in parallel on the outermost insulating layer. When the conductive protrusions for testing are formed in a width that matches the strip-shaped wiring conductor and shifted from the position of the adjacent conductive protrusions for testing, and the upper surface of each conductive conductive protrusion is exposed from the solder resist layer, Since the gap between the electrical test probes connected to the protrusions is widened, the probe can be securely attached to the test conductive protrusions even when the width of the band-shaped wiring conductors and the distance between adjacent band-shaped wiring conductors are narrow. The present inventors have found a new finding that they can be connected, and that an electrical test can be performed while preventing a short circuit failure caused by contact between probes. The present invention has been completed.

That is, the wiring board in the present invention has the following configuration.
(1) Insulating layers and wiring conductors are alternately stacked, and a plurality of strip-like wiring conductors for connecting semiconductor elements are arranged in parallel on the outermost insulating layer, and a part of each strip-like wiring conductor A flip-chip conductive protrusion to which the electrode terminal of the semiconductor element is flip-chip connected is formed with a width matching the width of the strip-shaped wiring conductor, and the flip is formed on the outermost insulating layer and on the strip-shaped wiring conductor. A wiring board on which a solder resist layer that exposes at least the upper surface of the chip conductive protrusion is deposited, and a test conductive protrusion to which a probe for electrical testing is further connected to a part of each of the strip-shaped wiring conductors The width of the test conductive protrusion is equal to the width of the strip-shaped wiring conductor and shifted from the adjacent test conductive protrusion, and the upper surface of each test conductive protrusion is exposed from the solder resist layer. Wiring board, characterized in that it is.
(2) The wiring board according to (1), wherein the test conductive protrusions are formed by alternately shifting positions on both sides of the flip chip conductive protrusions.
(3) The wiring board according to (1) or (2), wherein a width of the strip-shaped wiring conductor is 30 μm or less, and a distance between adjacent strip-shaped wiring conductors is 45 μm or less.
(4) The wiring board according to any one of (1) to (3), wherein an upper surface of the test conductive protrusion and an upper surface of the solder resist layer around the conductive protrusion are substantially the same height.
(5) The wiring board according to any one of (1) to (4), wherein an upper surface of the flip-chip conductive protrusion and an upper surface of the solder resist layer around the flip-chip conductive protrusion have substantially the same height.
(6) The wiring board according to any one of (1) to (5), wherein a length of the flip-chip conductive protrusion is longer than a width of the flip-chip conductive protrusion.

According to the present invention, a test conductive protrusion to which an electrical test probe is connected to a part of each of the strip-like wiring conductors arranged in parallel on the outermost insulating layer has a width that matches the strip-like wiring conductor. In addition, since the upper surface of each test conductive protrusion is exposed from the solder resist layer, it is easy to connect a general electric test probe to the conductive protrusion. In addition, there is an effect that an electrical test can be performed reliably.
In particular, when the width of the strip-shaped wiring conductor is 30 μm or less and the interval between the adjacent strip-shaped wiring conductors is 45 μm or less as in (3), the usefulness of the wiring board according to the present invention is further improved. improves.

  Hereinafter, an embodiment of a wiring board according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing a wiring board according to the present embodiment on which peripheral type semiconductor integrated circuit elements are mounted by flip-chip connection. FIG. 2 is a plan view showing the wiring board of FIG.

  As shown in FIGS. 1 and 2, the wiring substrate 10 according to the present embodiment includes an insulating layer 4 and a second wiring on the upper and lower surfaces of the insulating substrate 3 on which the first wiring conductor 2 is disposed from the upper surface to the lower surface. Conductors 5 are alternately stacked, and a protective solder resist layer 6 is deposited on the outermost surface.

  The insulating substrate 3 has a thickness of about 0.1 to 1.5 mm. For example, an electrically insulating material obtained by impregnating a glass cloth in which glass fiber bundles are woven vertically and horizontally with a thermosetting resin such as bismaleimide triazine resin or epoxy resin. And functions as a core member of the wiring board 10.

  A plurality of through holes 7 having a diameter of about 0.05 to 0.3 mm are formed from the upper surface to the lower surface of the insulating substrate 3, and the first wiring conductor is formed on the upper and lower surfaces of the insulating substrate 3 and the inner surface of the through hole 7. 2 is attached. The first wiring conductor 2 is mainly formed of copper foil on the upper and lower surfaces of the insulating substrate 3, and is formed of electroless copper plating and electrolytic copper plating thereon on the inner surface of the through hole 7.

  The through hole 7 is filled with an embedding resin 8 made of a thermosetting resin such as an epoxy resin, and the first wiring conductors 2 formed on the upper and lower surfaces of the insulating substrate 3 are connected to the first inside the through hole 7. The wiring conductor 2 is electrically connected.

  Such an insulating substrate 3 is formed by, for example, bonding a copper foil for the first wiring conductor 2 on the upper and lower surfaces of a sheet of glass fabric impregnated with an uncured thermosetting resin, and then thermosetting the sheet. This is manufactured by drilling the through hole 7 from the upper surface to the lower surface.

  In the first wiring conductor 2, copper foil having a thickness of about 3 to 50 μm is stuck on the entire upper and lower surfaces of the sheet for the insulating substrate 3 as described above, and through the copper foil and the insulating substrate 3. After the hole 7 is drilled, electroless copper plating and electrolytic copper plating are sequentially applied to the inner surface of the through hole 7 and the copper foil surface, and then the inside of the through hole 7 is filled with the embedded resin 8. The foil and copper plating are formed on the upper and lower surfaces of the insulating substrate 3 and the inner surface of the through hole 7 by etching into a predetermined pattern using, for example, a photolithography technique.

  The embedded resin 8 is used to form the insulating layer 4 immediately above and below the through hole 7 by closing the through hole 7, and an uncured paste-like thermosetting resin is placed in the through hole 7. After filling with a screen printing method and thermosetting it, the upper and lower surfaces thereof are polished to be substantially flat.

  The insulating layers 4 laminated on the upper and lower surfaces of the insulating substrate 3 each have a thickness of about 20 to 60 μm. Similarly to the insulating substrate 3, an electric insulating material in which a glass cloth is impregnated with a thermosetting resin, or an epoxy It consists of an electrically insulating material in which an inorganic filler such as silicon oxide is dispersed in a thermosetting resin such as a resin. Each insulating layer 4 is formed with a plurality of via holes 9 having a diameter of about 30 to 100 μm.

  A second wiring conductor 5 made of electroless copper plating and electrolytic copper plating thereon is deposited on the surface of each insulating layer 4 and the inner surface of the via hole 9. Then, the wiring conductor 5 located in the upper layer and the wiring conductor 5 located in the lower layer are electrically connected via the wiring conductor 5 in the via hole 9 with the insulating layer 4 interposed therebetween, thereby forming a high-density wiring in three dimensions. Is done.

  Among the plurality of second wiring conductors 5, a part of the second wiring conductor 5 deposited on the outermost insulating layer 4 on the upper surface side of the wiring substrate 10 is electrically conductive bumps 110 such as electrodes and solder of the semiconductor integrated circuit element 101, which will be described later. A strip-like wiring conductor 5a for connecting a semiconductor element, which is electrically connected via a flip-chip conductive protrusion 12 to be formed, is formed. On the other hand, a portion of the lower surface of the wiring board 10 that is deposited on the outermost insulating layer 4 is electrically connected to the wiring conductor of the external electric circuit board via the solder balls 111. A conductor 5b is formed.

  Such a second wiring conductor 5 is formed by, for example, a method called a semi-additive method. In the semi-additive method, for example, first, a base metal layer for electrolytic plating is formed on the surface of the insulating layer 4 in which the via hole 9 is formed by electroless copper plating, and an opening corresponding to the second wiring conductor 5 is formed thereon. A plating resist layer having the following is formed. Next, electrolytic copper plating is performed on the base metal layer exposed from the opening using the base metal layer as a power supply electrode to form the second wiring conductor 5, and after removing the plating resist, the exposed base metal layer is etched. In this method, the second wiring conductors 5 are made electrically independent by removing them.

  As shown in FIG. 2, the strip-shaped wiring conductor 5a for connecting the semiconductor element extends at a position corresponding to the outer peripheral portion of the semiconductor integrated circuit element 101 in a direction perpendicular to the outer periphery of the semiconductor integrated circuit element 101. A plurality of flip-chip conductive protrusions 12 connected to the conductive bumps 110 are arranged on the plurality of lines at a predetermined pitch and corresponding to the electrode terminals of the semiconductor integrated circuit element 101. It is formed with a matching width.

  Since the flip-chip conductive protrusion 12 is formed with a width that matches the width of the strip-shaped wiring conductor 5a, the flip-chip conductive protrusion 12 does not protrude from the strip-shaped wiring conductor 5a and secures a sufficient width for connection to the conductive bump 110. can do. Therefore, the wiring substrate 10 is excellent in the electrical insulation reliability between the adjacent strip-shaped wiring conductors 5a, and is excellent in the connection reliability between the flip-chip conductive protrusions 12 and the conductive bumps 110.

  Further, the flip-chip conductive protrusion 12 is formed to have a length that is, for example, 50 μm or longer than the width of the conductive protrusion 12. Thereby, for example, even when the formation position of the flip-chip conductive protrusion 12 is slightly shifted in the length direction of the strip-shaped wiring conductor 5a, the position of the electrode terminal of the semiconductor integrated circuit element 101 and the flip-chip conductive protrusion 12 is Therefore, the two can be accurately connected via the conductive bump 110. The length of the flip-chip conductive protrusion 12 is preferably about 70 to 100 μm.

  A solder resist layer 6 is deposited on the outermost insulating layer 4 and the second wiring conductor 5 thereon. The solder resist layer 6 is a protective film for protecting the outermost second wiring conductor 5 from heat and the external environment. The solder resist layer 6 on the upper surface side exposes the upper surface of the flip chip conductive protrusion 12. In addition, the solder resist layer 6 on the lower surface side is deposited so as to expose the wiring conductor 5b for external connection.

  Further, the upper surface of the flip-chip conductive protrusion 12 and the upper surface of the surrounding solder resist layer 6 are formed at substantially the same height. Thus, when the electrode terminal of the semiconductor integrated circuit element 101 is connected to the flip-chip conductive protrusion 12 via the conductive bump 110, the conductive bump 110 is interposed between the solder resist layer 6 and the semiconductor integrated circuit element 101. A gap corresponding to the height of the resin is secured, and the gap can be filled with the filling resin 112 with good fillability and without generating voids. The upper surface of the flip chip conductive protrusion 12 and the upper surface of the surrounding solder resist layer 6 do not have to be completely the same height, and there may be a height difference of 5 μm or less between the two.

  Here, on a part of each strip-shaped wiring conductor 5a, a test conductive projection 13 to which a probe for electrical testing is further connected has a width that matches the strip-shaped wiring conductor 5a, like the flip-chip conductive projection 12. Further, it is formed so as to be displaced from the adjacent test conductive protrusion 13. More specifically, the test conductive projections 13 are formed so as to be alternately shifted on both sides of the flip chip conductive projections 12 (that is, in a staggered arrangement). The upper surface of each test conductive protrusion 13 is exposed from the solder resist layer 6. Thus, when the adjacent test conductive protrusions 13 and 13 are alternately shifted and arranged in a staggered manner, the interval between the electrical test probes connected to the test conductive protrusions 13 is widened. Even when the width of 5a and the interval between the adjacent strip-like wiring conductors 5a and 5a are narrow, the probe can be reliably connected to the test conductive protrusion 13 and is generated when the probes come into contact with each other. The electrical test can be performed while preventing the short circuit failure.

  In particular, the width of the strip-shaped wiring conductor 5a is 30 μm or less, preferably 20 to 30 μm, and the interval between the strip-shaped wiring conductors 5a and 5a adjacent to each other is 45 μm or less, preferably 40 μm or less. The length of the test conductive protrusion 13 is preferably about 70 to 100 μm. The distance between the test conductive protrusion 13 and the flip-chip conductive protrusion 12 located on one strip-shaped wiring conductor 5a is preferably about 220 to 260 μm.

  Further, the upper surface of the test conductive protrusion 13 and the upper surface of the surrounding solder resist layer 6 are configured to have substantially the same height. As a result, the electrical test probe can be reliably connected to the test conductive protrusion 13. On the other hand, when the upper surface of the test conductive protrusion 13 is lower than the upper surface of the surrounding solder resist layer 6, it is difficult to connect the probe to the test conductive protrusion 13. As with the flip-chip conductive protrusions 12, the upper surface of the test conductive protrusion 13 and the upper surface of the surrounding solder resist layer 6 do not have to be completely the same height, and the distance between them is 5 μm or less. There may be a difference in height.

  Next, a method for manufacturing the wiring board 10 will be described in detail with reference to the drawings. FIGS. 3A to 3C, FIGS. 4D to 5F, and FIGS. 5G to 5J are schematic explanatory views showing a method for manufacturing a wiring board according to the present embodiment.

  First, as shown in FIGS. 3A and 3B, a base metal layer 51 for electrolytic plating is deposited on the surface of the outermost insulating layer 4 on the upper surface side by electroless plating. As the electroless plating for forming the base metal layer 51, electroless copper plating is preferable.

  Next, as shown in FIG. 3C, a first resist layer R <b> 1 is formed on the surface of the base metal layer 51. The first resist layer R1 has a first opening A1 having a shape corresponding to the strip-shaped wiring conductor 5a, and a photo-sensitive alkaline developing dry film resist is stuck on the base metal layer 51 and photolithography is applied thereto. By performing exposure and development using a technique, a pattern having a first opening A1 having a shape corresponding to the strip-shaped wiring conductor 5a is formed. The thickness of the first resist layer R1 is preferably slightly larger than the total thickness of the strip-shaped wiring conductor 5a and the flip-chip conductive protrusions 12 and the test conductive protrusions 13 formed thereon.

  As shown in FIG. 4D, a strip-shaped wiring conductor 5a is deposited on the underlying metal layer 51 exposed in the first opening A1 of the first resist layer R1 by electrolytic plating. As electrolytic plating for forming the strip-shaped wiring conductor 5a, electrolytic copper plating is preferable. The thickness of the strip-shaped wiring conductor 5a is thinner than the thickness of the first resist layer R1. Specifically, the thickness of the strip-shaped wiring conductor 5a is 8 to 20 μm, preferably 10 to 15 μm.

  As shown in FIG. 4E, a second resist layer R2 is formed on the surfaces of the first resist layer R1 and the strip-shaped wiring conductor 5a. The second resist layer R2 includes a second opening A2 that crosses the first opening A1 and has a width corresponding to the length of the flip chip conductive protrusion 12 at a position where the flip chip conductive protrusion 12 is formed, and a test conductive film. A third opening A3 is formed at a position where the protrusion 13 is formed, and has a width corresponding to the length of the test conductive protrusion 13 and crosses the first opening A1 directly to the side.

  Such a second resist layer R2 is formed by sticking a photosensitive alkali developing dry film resist on the first resist layer R1 and the strip-shaped wiring conductor 5a, and exposing and developing the same using a photolithography technique. Thus, a pattern having a second opening A2 and a third opening A3 is formed. At this time, the third openings A3 are formed so as to be alternately shifted on both sides of the second opening A2 with the second opening A2 interposed therebetween (that is, in a staggered arrangement). In addition, it is preferable that the thickness of 2nd resist layer R2 is more than the thickness of 1st resist layer R1.

  As shown in FIG. 4F, the flip-chip conductive protrusion 12 is surrounded by the first opening A1 and the third opening A3 on the strip-shaped wiring conductor 5a surrounded by the first opening A1 and the second opening A2. Test conductive protrusions 13 are respectively formed on the strip-shaped wiring conductor 5a by electrolytic plating. As a result, the flip-chip conductive protrusion 12 and the test conductive protrusion 13 thus formed have the same potential. As the electrolytic plating for forming the flip chip conductive protrusion 12 and the test conductive protrusion 13, electrolytic copper plating is preferable. The height of the flip-chip conductive protrusion 12 and the test conductive protrusion 13 is preferably slightly lower than the upper surface of the first resist layer R1.

  At this time, since the flip-chip conductive protrusion 12 is formed on the strip-shaped wiring conductor 5a surrounded by the first opening A1 and the second opening A2, the width is defined as the width defined by the first opening A1, that is, the strip shape. The wiring conductor 5a is formed to have a width that matches the width of the wiring conductor 5a, and the length is defined by the second opening A2. Similarly, since the test conductive protrusion 13 is formed on the strip-shaped wiring conductor 5a surrounded by the first opening A1 and the third opening A3, it is formed with a width that matches the width of the strip-shaped wiring conductor 5a. At the same time, the length is defined by the width defined by the third opening A3.

  Further, since the second opening A2 and the third opening A3 are formed so as to cross the first opening A1, respectively, the second opening A2 is caused by an alignment error in forming the second resist layer R2. Even if the position of A2 and the third opening A3 is shifted in the width direction of the strip-shaped wiring conductor 5a, the exposed width of the strip-shaped wiring conductor 5a does not change. The width of 13 is not affected.

  If the width of the second opening A2 is formed to be, for example, 50 μm or more wider than the width of the first opening A1, the length of the flip-chip conductive protrusion 12 is increased accordingly. Even if the position of the second opening A2 is shifted by, for example, about 25 μm in the length direction of the strip-like wiring conductor 5a due to the alignment error when forming the second resist layer R2, the flip-chip conductive protrusion 12 is In addition, since it is possible to secure a region that accurately faces the electrode terminal of the semiconductor integrated circuit element 101, the electrode terminal of the semiconductor integrated circuit element 101 and the flip-chip conductive protrusion 12 are accurately connected via the conductive bump 110. be able to. Therefore, it is preferable that the width of the second opening A2 is, for example, 50 μm or more wider than the width of the first opening A1.

  As shown in FIG. 5G, the first resist layer R1 and the second resist layer R2 are removed. The removal of the first resist layer R1 and the second resist layer R2 is performed by immersion in an alkaline aqueous solution such as an aqueous sodium hydroxide solution.

  As shown in FIG. 5H, the base metal layer 51 other than the portion where the strip-like wiring conductor 5a is formed is removed. As a result, the adjacent strip-shaped wiring conductors 5a are electrically independent. At this time, the flip-chip conductive protrusions 12 and the test conductive protrusions 13 formed on the strip-shaped wiring conductor 5a are formed with a width that matches the strip-shaped wiring conductor 5a, and protrude from the strip-shaped wiring conductor 5a. Therefore, the electrical insulation between the adjacent strip-shaped wiring conductors 5a is kept good. In order to remove the base metal layer 51 other than the portion where the strip-shaped wiring conductor 5a is formed, after removing the first resist layer R1 and the second resist layer R2, the exposed base metal layer 51 is replaced with, for example, chloride chloride. A method of etching away with an etching solution containing dicopper can be employed.

  As shown in FIG. 5I, the outermost insulating layer 4, the strip-shaped wiring conductor 5a, the flip chip conductive protrusion 12 and the test conductive protrusion 13 are covered with the resin 6a for the solder resist layer. As the resin 6a for the solder resist layer, various known resins that function as a solder resist layer for protecting the surface of the wiring board can be employed. For example, an inorganic powder filler such as silica or talc is added to 30 to 30 epoxy resin or the like. A thermosetting resin made of an insulating material dispersed in an amount of about 70% by mass is preferable, and the resin is preferably cured after coating.

  As shown in FIG. 5J, the solder resist layer resin 6a is polished until the upper surfaces of the flip chip conductive protrusions 12 and the test conductive protrusions 13 are exposed to form the solder resist layer 6, and the flip chip Thus, the wiring board 10 is obtained in which the upper surfaces of the conductive conductive protrusions 12 and the test conductive protrusions 13 are exposed in substantially the same plane as the upper surface of the surrounding solder resist layer 6. For the polishing, various known mechanical polishing methods, laser scribing methods, and the like can be employed. The thickness of the solder resist layer 6 includes the upper surface of the solder resist layer 6, the flip-chip conductive protrusions 12, and the test conductive. A thickness at which the height difference from the upper surface of the protrusion 13 is 5 μm or less is preferable.

  Since the obtained wiring board 10 is arranged in a staggered manner by alternately shifting adjacent test conductive protrusions 13, 13, a general electric test probe is connected to the test conductive protrusion 13. Therefore, an electrical test can be performed easily and reliably. As the diameter of the probe, for example, a probe having a diameter of 40 μm or more can be used.

  Then, as shown in FIG. 1, the electrode terminals of the peripheral type semiconductor integrated circuit element 101 and the flip-chip conductive protrusions 12 formed on the strip-like wiring conductor 5a are electrically connected via the conductive bumps 110 ( By performing flip chip connection, the electrode terminals of the semiconductor integrated circuit element 101 and the strip-shaped wiring conductor 5a are electrically connected. Next, the gap between the semiconductor integrated circuit element 101 and the wiring substrate 10 is filled with the filling resin 112, and the semiconductor integrated circuit element 101 is mounted on the wiring substrate 10.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to the above embodiment, A various improvement and change are possible within the range described in the claim. For example, in the above-described embodiment, the second opening A2 and the third opening A3 are formed in directions orthogonal to the first opening A1, respectively, but according to the shape of the flip chip conductive protrusion 12 and the test conductive protrusion 13, You may form 2nd opening A2 and 3rd opening A3 in arbitrary directions.

One flip-chip conductive protrusion 12 is formed on the surface of one strip-shaped wiring conductor 5a. By combining a plurality of first openings A1 and second openings A2, one strip-shaped wiring conductor 5a is formed. A plurality of flip-chip conductive protrusions 12 may be formed on the surface of the substrate.
The test conductive protrusions 13 need only be formed so as to be displaced from the adjacent test conductive protrusions 13, and may be formed in a staggered arrangement as shown in FIG. 6, for example.

  When the solder resist layer 6 is formed by polishing the solder resist layer resin 6a until the upper surfaces of the flip chip conductive protrusions 12 and the test conductive protrusions 13 are exposed (FIGS. 5I and 5J). 7), for example, as shown in FIG. 7, only the regions corresponding to the flip chip conductive protrusions 12 and the corresponding regions of the test conductive protrusions 13 are selectively polished in a band shape for flip chip use. The upper surfaces of the conductive protrusions 12 and the test conductive protrusions 13 may be exposed, and the solder resist layer resin 6a in other regions may be left thick. As a result, the area to be polished can be reduced, so that the polishing is facilitated and the solder resist layer 6 in the region that has not been polished remains thick, so that the conductor integrated circuit element 101 is protected from heat and the external environment when mounted. Ability can be made higher. Other configurations are the same as those of the above-described embodiment.

1 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present invention on which peripheral type semiconductor integrated circuit elements are mounted by flip-chip connection. It is a top view which shows the wiring board of FIG. (A)-(c) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning one Embodiment of this invention. (D)-(f) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning one Embodiment of this invention. (G)-(j) is a schematic explanatory drawing which shows the manufacturing method of the wiring board concerning one Embodiment of this invention. It is a top view which shows the wiring board concerning other embodiment of this invention. It is a schematic explanatory drawing which shows the wiring board concerning further another embodiment of this invention. It is a schematic sectional drawing which shows the conventional wiring board. It is a top view which shows the wiring board of FIG.

Explanation of symbols

2 First wiring conductor 3 Insulating substrate 4 Insulating layer 5 Second wiring conductor 5a Band-shaped wiring conductor 5a for connecting semiconductor elements 5b Wiring conductor for external connection 6 Solder resist layer 6a Resin for solder resist layer 7 Through hole 8 Embedding Resin 9 Via hole 10 Wiring board 12 Conductive protrusion for flip chip 13 Conductive protrusion for test 51 Underlying metal layer 101 Semiconductor integrated circuit element 110 Conductive bump 111 Solder ball 112 Filling resin A1 First opening A2 Second opening A3 Third opening R1 First Resist layer R2 Second resist layer

Claims (6)

Insulating layers and wiring conductors are laminated alternately,
A plurality of strip-like wiring conductors for connecting semiconductor elements are arranged in parallel on the outermost insulating layer, and conductive protrusions for flip-chip, in which electrode terminals of the semiconductor elements are flip-chip connected to a part of each strip-like wiring conductor, It is formed with a width that matches the width of the strip-shaped wiring conductor,
And a wiring board on which a solder resist layer that exposes at least an upper surface of the flip-chip conductive protrusion is deposited on the outermost insulating layer and the strip-shaped wiring conductor,
A test conductive protrusion to which an electrical test probe is further connected is formed on a part of each of the strip-shaped wiring conductors so as to have a width matching the strip-shaped wiring conductor and shifted from the adjacent test conductive protrusion. And a top surface of each test conductive protrusion is exposed from the solder resist layer.   2. The wiring board according to claim 1, wherein the test conductive protrusions are formed so as to be alternately shifted on both sides of the flip chip conductive protrusion.   The wiring board according to claim 1 or 2, wherein a width of the strip-shaped wiring conductor is 30 µm or less, and a distance between adjacent strip-shaped wiring conductors is 45 µm or less.   The wiring board according to claim 1, wherein an upper surface of the test conductive protrusion and an upper surface of the solder resist layer around the test conductive protrusion have substantially the same height.   The wiring board according to claim 1, wherein an upper surface of the flip-chip conductive protrusion and an upper surface of the solder resist layer around the flip-chip conductive protrusion have substantially the same height.   The wiring board according to claim 1, wherein a length of the flip-chip conductive protrusion is longer than a width of the flip-chip conductive protrusion.

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