JP6510349B2 - Wiring board - Google Patents

Description

  The present invention relates to, for example, a wiring board used to inspect a semiconductor element.

  5 to 7 show a conventional wiring substrate 40 used to inspect a semiconductor element. FIG. 5 is a schematic cross-sectional view taken along the line B-B in FIG. FIG. 6 is a schematic top view of the wiring substrate 40. As shown in FIG. FIG. 7 is a plan view of the main part of the wiring board 40. FIG. The wiring board 40 is configured by the core portion 21 and the buildup portion 22.

  The core portion 21 is constituted by the insulating layer 23, the via conductor 24 and the conductor layer 25. In each insulating layer 23, a plurality of via holes 23a are formed. The via conductor 24 fills the inside of the via hole 23 a of each insulating layer 23. The conductor layer 25 is embedded in the surface of the insulating layer 23. A part of the conductor layer 25 is connected to the via conductor 24. Thus, the conductor layers 25 located above and below the insulating layer 23 are electrically connected via the via conductor 24.

  The buildup portion 22 is configured by the insulating layer 26, the conductor layer 27, and the solder resist layer 28. In each insulating layer 26, a plurality of via holes 26a are formed. A portion of the via hole 26 a is formed on the conductor layer 25 of the core portion 21. The conductor layer 27 is deposited on the surface of each insulating layer 26 so as to fill the via hole 26a. Thus, the conductor layers 27 and the conductor layers 25 and the conductor layers 27 which are positioned above and below are electrically connected to each other through the via holes 26a.

  Furthermore, the solder resist layer 28 is attached to the surfaces of the outermost insulating layer 26 and the conductor layer 27 in the buildup section 22. The solder resist layer 28 has an opening that exposes a portion of the conductor layer 27.

  A portion of the conductor layer 27 exposed from the opening of the solder resist layer 28 on the upper surface side forms a main substrate connection pad 29. The size of the main substrate connection pad 29 is about 400 μm in diameter. Main substrate connection pad 29 is connected to a main substrate (not shown). The main board is a parent board for electrically connecting the wiring board 40 with the electrical inspection equipment for inspecting the semiconductor element, and is formed of, for example, a printed board. Further, a part of the conductor layer 27 exposed from the opening of the solder resist layer 28 on the upper surface side forms a component connection pad 30. The size of the component connection pad 30 is equal to or larger than that of the main substrate connection pad 29. An electronic component E is mounted on the component connection pad 30. The electronic component E is, for example, a capacitor element.

  A part of the conductor layer 27 exposed from the opening of the solder resist layer 28 on the lower surface side forms a pin connection pad 31. Contact pins P for testing semiconductor elements are connected to the pin connection pads 31. The contact pins P are held to be connected to the pin connection pads 31 by holding means (not shown). By bringing the contact pins P into contact with the electrodes of the semiconductor element formed on the wafer, an electrical inspection of the semiconductor element is performed.

  When mounting the electronic component E on the component connection pad 30 in such a wiring board 40, an automatic machine equipped with an image recognition device is used. Therefore, a recognition mark 32 for recognizing the mounting position of the electronic component E is provided on the upper surface of the wiring board 40. The recognition mark 32 is formed by the outermost conductor layer 27 on the upper surface side. The recognition mark 32 is formed of a circular independent small pattern, and is formed by exposing the central portion thereof from an opening provided in the solder resist layer 28. The recognition mark 32 is recognized by the image recognition device, and the electronic component E is positioned and mounted on a predetermined component connection pad 30 based on the position information.

  Here, a part of the outermost conductor layer 27 on the upper surface side including the recognition mark 32 is shown in FIG. In FIG. 7, the position of the opening of the solder resist layer 28 is indicated by a dotted line. The conductor layer 27 on the top surface side has a solid pattern 27a, a large circular pattern 27b having a major axis of about 500 μm, a rectangular pattern 27c having a side length of about 500 μm, and a small circular pattern having a diameter of 200 μm or less And 27d. A part of the solid pattern 27 a and the large circular pattern 27 b form a main substrate connection pad 29. Part of the solid pattern 27 a and the square pattern 27 c form a component connection pad 30. The small circular pattern 27 d forms the recognition mark 32. A gap of about 50 to 200 μm in width is provided between the solid pattern 27a and the other patterns 27b, 27c, and 27d. The solid pattern 7a and the other patterns 27b, 27c and 27d are electrically independent of each other.

  By the way, in the wiring substrate 40, a plated metal layer made of nickel, palladium, gold or the like is deposited on the surfaces of the main substrate connection pad 29, the component connection pad 30, the pin connection pad 31, and the recognition mark 32. By depositing such a plated metal layer, oxidation corrosion of the main substrate connection pad 29, the component connection pad 30, the pin connection pad 31, and the recognition mark 32 is prevented. As a result, the connection reliability of each connection pad 29, 30, 31 is improved. Further, the contrast between the recognition mark 32 and the periphery thereof is increased, and the recognition of the recognition mark 32 is improved. When a plated metal layer is deposited on the surface of each of the connection pads 29, 30, 31 and the recognition mark 32, an electroless plating method is preferably employed. In the electroless plating method, there is no need to provide a lead wire for plating, which is advantageous in the case of a recent wiring substrate which has been made into fine wiring and high density wiring.

  However, high precision is also required for the alignment of the electronic component E in the recent wiring board in which fine wiring and high density wiring are realized. Therefore, an image recognition apparatus that recognizes the recognition mark 32 is also adopted as one with a high magnification. In accordance with that, the size of the pattern for forming the recognition mark 32 is also small, for example, 200 μm or less in diameter. If the size of the pattern forming the recognition mark 32 is small and electrically independent with a diameter of 200 μm or less, the plated metal layer can not be satisfactorily deposited on the surface of the recognition mark 32. This is because the deposition reaction of plating is concentrated on the main substrate connection pad 29 and the component connection pad 30 of a much larger area than that for the recognition mark 32, and the deposition reaction of plating is performed on the small recognition mark 32 in the same area. It is because it is difficult to proceed.

  When the plated metal layer is not deposited well on the surface of the recognition mark 32, the recognition mark 32 is easily oxidized and corroded, and the recognition of the recognition mark 32 is degraded. As a result, it becomes difficult to accurately and favorably mount the electronic component E on the component connection pad 30 by an automatic machine equipped with an image recognition device.

JP, 2013-172137, A JP, 2013-004937, A

  The problem to be solved by the present invention is that, even if the recognition mark is formed by a small pattern having a diameter of 200 μm or less, the plated metal layer by electroless plating is satisfactorily deposited on the surface of the recognition mark, whereby the recognition mark It is an object of the present invention to provide a wiring board in which the oxidation corrosion of the metal is effectively prevented and the recognition of the recognition mark is high.

The wiring board of the present invention is formed by alternately laminating a plurality of insulating layers and conductor layers, and has a solid pattern which is a part of the conductive layer on the upper surface, and a plurality of connection pads including a part of the solid pattern. And a recognition mark which is located with a gap between the solid pattern and has a smaller area than the connection pad, and the surface of the connection pad and the recognition mark is plated by electroless plating. A wiring board on which a metal layer is deposited, wherein the identification mark is electrically connected to at least one of the connection pads via the solid pattern .

  According to the wiring board of the present invention, since the recognition mark is electrically connected to at least one of the connection pads having an area larger than the recognition mark, the recognition mark has the same potential as the connection pad. Therefore, although the area of the recognition mark is smaller than that of the connection pad, the plated metal layer by electroless plating is favorably deposited on the surface of the recognition mark. Therefore, the oxidation corrosion of the recognition mark is effectively prevented, and the recognition of the recognition mark is high.

FIG. 1 is a schematic cross-sectional view showing an example of the embodiment of the wiring board of the present invention. FIG. 2 is a schematic top view of the wiring board shown in FIG. FIG. 3 is a plan view of relevant parts of the wiring board shown in FIGS. 1 and 2. FIG. 4 is a schematic cross-sectional view showing another example of the embodiment of the wiring board of the present invention. FIG. 5 is a schematic cross-sectional view of a conventional wiring board. FIG. 6 is a schematic top view of the wiring board shown in FIG. FIG. 7 is a plan view of an essential part of the wiring board shown in FIG. 5 and FIG.

  Next, an example of the embodiment of the wiring board of the present invention will be described. The wiring board 20 of this example is shown in FIGS. FIG. 1 is a schematic cross-sectional view taken along the line A-A of FIG. FIG. 2 is a schematic top view of the wiring substrate 20. As shown in FIG. FIG. 3 is an enlarged plan view of the main part of the wiring substrate 20. As shown in FIG. The wiring board 20 is configured by the core portion 1 and the buildup portion 2.

  The core portion 1 is composed of the insulating layer 3, the via conductor 4 and the conductor layer 5. The thickness of the insulating layer 3 is about 100 to 200 μm. Via holes 3 a are formed in each insulating layer 3. The diameter of the via hole 3a is about 100 to 200 μm. The insulating layer 3 is made of a cured product of an insulating sheet obtained by impregnating a heat resistant fiber substrate such as glass cloth with a thermosetting resin such as allyl-modified polyphenylene ether resin. The via hole 3 a is formed by performing laser processing on the insulating sheet for the insulating layer 3.

  The via conductor 4 fills the inside of the via hole 3 a of each insulating layer 3. The via conductor 4 is made of, for example, a silver-coated copper powder, a solder powder of a tin-silver-bismuth-copper alloy, and a cured product of a conductive paste containing a thermosetting resin. The via conductor 4 is formed by filling the conductive paste for the via conductor 4 in the via hole 3a formed in the insulating sheet for the insulating layer 3 and thermally curing the conductive paste together with the insulating sheet for the insulating layer 3 .

  The conductor layer 5 is embedded in the surface of each insulating layer 3. The thickness of the conductor layer 5 is about 5 to 25 μm. The conductor layer 5 is made of copper foil. Conductor layer 5 is embedded in the surface of insulating layer 3 such that a portion thereof is connected to via conductor 4. Thus, the conductor layers 5 positioned above and below the insulating layer 3 are electrically connected to each other through the via conductor 4. The conductor layer 5 is embedded in the surface of the insulating layer 3 by the transfer method. In the transfer method, the conductor layer 5 releasably adhered on a transfer film made of a heat resistant resin such as polyethylene terephthalate is embedded by thermal compression using a heat press on the surface of the insulating sheet for the insulating layer 3. It is a method of removing the transfer film after The transfer of the conductor layer 5 is performed on the insulating sheet in which the conductive paste is filled in the via hole 3a. The core portion 1 is formed by laminating the whole of the insulating sheet for the insulating layer 3 to which the conductor layer 5 has been transferred up and down, and then thermally curing the insulating sheet and the conductive paste.

  The buildup portion 2 is configured of an insulating layer 6, a conductor layer 7 and a solder resist layer 8. The thickness of the insulating layer 6 is about 10 to 50 μm. A large number of via holes 6 a are formed in each insulating layer 6. A portion of the via hole 6 a is formed on the conductor layer 5 of the core portion 1. The diameter of the via hole 6a is about 30 to 100 μm. The insulating layer 6 is made of a cured product of an insulating film in which an inorganic insulating filler such as silica is dispersed in a thermosetting resin such as an epoxy resin. The insulating layer 6 is formed by laminating a resin film for the insulating layer 6 on the lower insulating layer 3 and the conductor layer 5 or on the insulating layer 6 and the conductive layer 7 and then thermally curing it. The via holes 6 a are formed by applying laser processing to the hardened insulating layer 6.

  The conductor layer 7 is deposited on the surface of the insulating layer 6 and in the via hole 6 a so as to completely fill the inside of the via hole 6 a. Thus, the conductor layers 7 and the conductor layers 5 and the conductor layers 7 which are positioned above and below are electrically connected to each other through the via holes 6a. The thickness of the conductor layer 7 on the insulating layer 6 is about 5 to 25 μm. The conductor layer 7 is made of a copper plating layer. The conductor layer 7 is formed by a known semi-additive method.

  The solder resist layer 8 is formed on the outermost insulating layer 6 and the conductor layer 7. The solder resist layer 8 has an opening for exposing a part of the conductor layer 7. The thickness of the solder resist layer 8 is about 5 to 25 μm on the outermost conductor layer 7. The solder resist layer 8 is made of a cured product of a photosensitive thermosetting resin such as an acrylic modified epoxy resin. The solder resist layer 8 applies a photosensitive resin paste for the solder resist layer 8 onto the outermost insulating layer 6 and the conductor layer 7, and after exposing and developing it to a predetermined pattern, it is cured by ultraviolet light and thermally. It is formed by

  A part of the conductor layer 7 exposed from the opening of the solder resist layer 8 on the upper surface side forms the main substrate connection pad 9. The size of the main substrate connection pad 9 is about 400 μm in diameter. Main substrate connection pad 9 is connected to a main substrate (not shown). The main substrate is a parent substrate for electrically connecting the wiring board 20 and the electrical inspection device for inspecting the semiconductor element, and is formed of, for example, a printed circuit board.

  Further, a part of the conductor layer 7 exposed from the opening of the solder resist layer 8 on the upper surface side forms a component connection pad 10. The size of the component connection pad 10 is equal to or larger than that of the main substrate connection pad 9. The electronic component E is mounted on the component connection pad 10. The electronic component E is, for example, a capacitor element.

  Furthermore, a part of the conductor layer 7 exposed from the opening of the solder resist layer 8 on the upper surface side forms a recognition mark 11. The recognition mark 11 is for recognizing the mounting position of the electronic component E. An automatic machine equipped with an image recognition device is used to mount the electronic component E. The recognition mark 11 is recognized by the image recognition device of the automatic machine, and the electronic component E is automatically positioned and mounted on the predetermined component connection pad 10 based on the position information.

  A part of the conductor layer 7 exposed from the opening of the solder resist layer 8 on the lower surface side forms a pin connection pad 12. Contact pins P for testing semiconductor elements are connected to the pin connection pads 12. The contact pin P is held to be connected to the pin connection pad 12 by holding means (not shown). By bringing the contact pins P into contact with the electrodes of the semiconductor element formed on the wafer, an electrical inspection of the semiconductor element is performed.

  In the wiring substrate 20, a plated metal layer made of nickel, palladium, gold or the like is adhered by electroless plating on the surfaces of the main substrate connection pad 9, the component connection pad 10, the recognition mark 11 and the pin connection pad 12. It is done. By depositing such a plated metal layer, oxidation corrosion of the main substrate connection pad 9, the component connection pad 10, the recognition mark 11, and the pin connection pad 12 is prevented. Thereby, the connection reliability of each connection pad 9, 10, 12 is improved. Further, the contrast between the recognition mark 11 and the periphery thereof is increased, and the recognition of the recognition mark 11 is improved.

  Here, a part of the outermost conductor layer 7 on the upper surface side is shown in FIG. In FIG. 3, the position of the opening of the solder resist layer 8 is indicated by a dotted line. The conductor layer 7 on the top surface side has a solid pattern 7a, a large circular pattern 7b having a major axis of about 500 μm, a rectangular pattern 7c having a side length of about 500 μm, and a small circular pattern having a diameter of 200 μm or less And 7d. A part of the solid pattern 7 a and the large circular pattern 7 b form a main substrate connection pad 9. Part of the solid pattern 7 a and the square pattern 7 c form a component connection pad 10. The small circular pattern 7 d forms the recognition mark 11. A gap of about 50 to 200 μm is provided between the solid pattern 7a and the other patterns 7b, 7c and 7d. The solid pattern 7a, the large circular pattern 7b and the square pattern 7c are electrically independent of each other. The solid pattern 7a and the small circular pattern 7d are electrically connected to each other by a strip-shaped connection pattern 7e. As a result, the recognition mark 11 is electrically connected to the main substrate connection pad 9 and the component connection pad 10 which are a part of the solid pattern 7a.

  As described above, according to the wiring substrate 20 of the present example, since the recognition mark 11 is electrically connected to at least one of the connection pads 9 and 10 having a larger area than the recognition mark 11, the connection The pads 9 and 10 have the same potential. Therefore, although the area of the recognition mark 11 is smaller than that of the connection pads 9 and 10, a plated metal layer by electroless plating is satisfactorily deposited on the surface of the recognition mark 11. Therefore, the oxidation corrosion of the recognition mark 11 is effectively prevented, and the recognition of the recognition mark 11 is high.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. For example, in one example of the above-described embodiment, the pattern 7d for forming the recognition mark 11 is connected to at least one of the connection pads 9 and 10 by connecting to the solid pattern 7a, as shown in FIG. The mark 11 may be electrically connected to at least one of the connection pads 9 and 10 by connecting the mark 11 to the conductor layer 7 located in the lower layer via the via hole 6a.

3, 6 · · · insulating layer 5, 7 · · · conductor layer 9, 10 · · · connection pad 11 · · · recognition mark

Claims (1)

A plurality of insulating layers and a plurality of conductive layers are alternately stacked , and a solid pattern which is a part of the conductive layer on the upper surface, a plurality of connection pads including a part of the solid pattern, and the solid pattern And a recognition mark having a smaller area than the connection pad and a plating metal layer by electroless plating is deposited on the surface of the connection pad and the recognition mark. The wiring board according to claim 1, wherein the identification mark is electrically connected to at least one of the connection pads through the solid pattern .

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