WO2014073126A1 - Wiring board - Google Patents

Abstract

The purpose of the present invention is to provide a wiring board with which the degree of freedom of wiring layout is improved. This wiring board is provided with a stacked body having, stacked therein, at least one insulation layer and at least one conductor layer. The wiring board is characterized by being provided with a plurality of wires formed upon the stacked body, and a columnar connection terminal formed directly upon at least one wire from among the plurality of wires. The wiring board is further characterized in that the width of the at least one wire in a location where the connection terminal is formed is less than the length of the connection terminal in the width direction.

Description

Wiring board

The present invention relates to a wiring board having connection terminals for connecting a semiconductor chip to a main surface.

Usually, terminals (hereinafter referred to as bumps) for connection to a semiconductor chip are formed on the main surface (front surface) of the wiring board. The bumps are formed of solder on a circular or square copper foil called a land having a size (area) larger than the opening area of the solder resist so that the upper end is positioned higher than the solder resist. *

By the way, in recent years, the density of the bumps has been increased, and it is required to narrow the interval (pitch) between the arranged bumps. However, in order to form the bump as described above, it is necessary to provide a land larger than the bump in the base wiring. For this reason, it is difficult to increase the density of the bumps. *

Moreover, since it is necessary to route the wiring around the land, the layout of the wiring is limited. For this reason, it is necessary to provide an extra wiring layer in order to form a wiring that cannot be routed. Thus, it has been proposed to obtain high-density wiring by forming bumps directly on the underlying wiring without providing lands (see Patent Document 1).

JP 2003-347334 A

However, the technique proposed in Patent Document 1 has a problem that the connection reliability with the semiconductor chip is lowered because the bump diameter is smaller than the wiring width. In addition, when the bump diameter is increased, the wiring width becomes thick, and thus there is a problem that the degree of freedom of wiring layout is limited. *

The present invention has been made in response to the above-described circumstances, and an object thereof is to provide a wiring board capable of improving the degree of freedom of wiring layout.

In order to achieve the above object, the wiring board of the present invention is a wiring board having a laminate in which one or more insulating layers and conductor layers are laminated, and a plurality of wirings formed on the laminate, Columnar connection terminals formed directly on at least some of the plurality of wires, and the width of the at least some of the wires at the position where the connection terminals are formed is the width of the connection terminals It is less than the length in the direction. *

According to the present invention, since the connection terminal is directly formed on the wiring, it is not necessary to provide a land for the connection terminal, and the degree of freedom of the wiring layout is improved. In addition, the width of the wiring at the position where the connection terminal is formed is less than the length of the connection terminal in the direction that coincides with the width direction of the wiring, so that the connection terminal can be prevented from being reduced and the connection reliability from being lowered. . *

Note that in one embodiment of the present invention, the width of the wiring at the position where the connection terminal is formed is 0.5 to 1.0 times the length of the connection terminal in the direction matching the width direction of the wiring. It is characterized by that. By making the width of the wiring at the position where the connection terminal is formed 0.5 times or more and less than 1.0 times the length of the connection terminal in the width direction of the connection terminal, the connection terminal becomes smaller and connection reliability is lowered. In addition, it is possible to prevent the connection terminal from becoming too large compared to the wiring width, and the connection terminal from tilting or falling. *

Another aspect of the present invention is characterized in that the connection terminal is formed at a position where a first thick portion having a wide wiring width is provided. By having the first thick portion where the wiring width is increased at the position where the connection terminal is formed, the connection terminal having a large diameter can be directly formed on the wiring. Further, the connection reliability between the connection terminal and the wiring forming the conductor layer is improved. *

In another aspect of the present invention, the length of the first thick portion in the extending direction of the wiring is not less than 0.5 times and not more than 2.0 times the length of the connection terminal in the extending direction. It is characterized by. By setting the length of the first thick portion in the direction of extension of the wiring to be not less than 0.5 times and not more than 2.0 times the length of the connection terminal in the direction coinciding with the direction of extension of the wiring, the first width It can be suppressed that the thick portion becomes too long in the extending direction and the degree of freedom of the wiring layout is reduced. *

Another aspect of the present invention is characterized by further comprising a solder resist layer that covers the plurality of wirings and exposes at least part of the connection terminals. By providing the solder resist layer that exposes at least a part of the connection terminal, the connection terminal is hardly peeled off. *

In another aspect of the present invention, at least a part of the connection terminal protrudes from the surface of the solder resist layer. By projecting the connection terminal from the surface of the solder resist layer, the connection with the counterpart terminal is facilitated. *

Further, in another aspect of the present invention, the connection terminals are arranged as a plurality of signal connection terminals only on the outer periphery of a rectangular component mounting region set on the laminate, and the central portion of the component mounting region A plurality of connection pads for power and ground are arranged. *

Since multiple connection terminals are arranged only at the outer periphery of the component mounting area, wiring can be made easier by using the signal connection terminals that are difficult to route because the wiring length is long and the wiring layout is flexible. Can be improved. Further, by arranging a plurality of power supply and ground connection pads in the center of the component mounting area, the power supply and ground wiring length can be shortened.

In another aspect of the present invention, the laminate is formed by alternately laminating a plurality of the conductor layers and the plurality of insulating layers, and directly forming the laminate on the plurality of wirings forming the conductor layers. And a via conductor that connects the conductor layers through the insulating layer, and the width of the wiring forming the conductor layer at the position where the via conductor is formed is the length of the via conductor in the width direction. 0.5 times to less than 1.0 times. *

By reducing the width of the wiring forming the conductor layer at the position where the via conductor is formed to 0.5 to 1.0 times the length in the width direction of the via conductor, the pitch between the via conductors is reduced. This makes it possible to improve the flexibility of the wiring layout. Moreover, it can suppress that connection reliability with a via conductor and the wiring which forms a conductor layer falls. *

In another aspect of the present invention, the wiring forming the conductor layer has a second thick portion having a thick wiring width at a position where the via conductor is formed. By having the second wide portion where the wiring width is thick at the position where the via conductor is formed, a via conductor having a large diameter can be formed directly on the wiring. Further, the connection reliability between the via conductor and the wiring forming the conductor layer is improved. *

Furthermore, in another aspect of the present invention, the length in the extending direction of the wiring forming the conductor layer of the second thick portion is 0.5 times or more the length in the extending direction of the via conductor. It is characterized by being 2.0 times or less. By setting the length in the extending direction of the wiring forming the second thick layer conductor layer to be not less than 0.5 times and not more than 2.0 times the length in the extending direction of the via conductor, It can be suppressed that the portion becomes too long in the extending direction and the degree of freedom of the wiring layout is reduced.

As described above, according to the present invention, it is possible to provide a wiring board capable of improving the degree of freedom of wiring layout.

The top view (surface side) of the wiring board which concerns on 1st Embodiment. 1 is a partial cross-sectional view of a wiring board according to a first embodiment. The block diagram of the connecting terminal of the surface side of the wiring board which concerns on 1st Embodiment. The top view of the connection terminal and wiring by the side of the surface of the wiring board which concern on 1st Embodiment. The manufacturing process figure (core board | substrate process) of the wiring board which concerns on 1st Embodiment. The manufacturing process figure (build-up process) of the wiring board which concerns on 1st Embodiment. The manufacturing process figure (convex plating layer formation process) of the wiring board which concerns on 1st Embodiment. The manufacturing process figure (filling process) of the wiring board which concerns on 1st Embodiment. It is explanatory drawing of the 4th filling method. The manufacturing process figure (solder resist layer process) of the wiring board which concerns on 1st Embodiment. The manufacturing process figure (plating process) of the wiring board which concerns on 1st Embodiment. The partial cross section figure of the wiring board which concerns on the modification of 1st Embodiment. The top view of the wiring and via conductor of the wiring board which concern on the modification of 1st Embodiment. The enlarged plan view of the wiring of the wiring board which concerns on the modification of 1st Embodiment, and a via conductor. The manufacturing process figure (build-up process) of the wiring board which concerns on the modification of 1st Embodiment. The manufacturing process figure (build-up process) of the wiring board which concerns on the modification of 1st Embodiment. The top view (surface side) of the wiring board which concerns on 2nd Embodiment. The top view (surface side) of the wiring board which concerns on 3rd Embodiment. The partial cross section figure of the wiring board which concerns on 3rd Embodiment. The top view (surface side) of the wiring board which concerns on 4th Embodiment. The partial enlarged view of the wiring board which concerns on 5th Embodiment. The figure which shows the upper surface shape of the filling member of the wiring board which concerns on other embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the embodiment of the present invention will be described by taking a wiring board in which a buildup layer is formed on a core board as an example, but any wiring board in which a plurality of connection terminals are formed may be used. A wiring board having no core board may be used. *

First Embodiment FIG. 1 is a plan view (front side) of a wiring board 100 according to a first embodiment. FIG. 2 is a partial cross-sectional view of the wiring board 100 taken along line II in FIG. FIG. 3 is a configuration diagram of the connection terminal T <b> 1 formed on the front surface side of the wiring substrate 100. FIG. 3A is a top view of the connection terminal T1. FIG. 3B is a cross-sectional view taken along line II-II in FIG. In the following description, a side to which a semiconductor chip (component) is connected is referred to as a front side, and a side to which a mother board, a socket or the like (hereinafter referred to as a mother board or the like) is connected is referred to as a back side. *

(Configuration of Wiring Substrate 100) The wiring substrate 100 shown in FIGS. 1 to 3 is a build in which a plurality of connection terminals T1 between the core substrate 2 and a semiconductor chip (not shown) are formed and stacked on the surface side of the core substrate 2. The up layer 3 (surface side), the filling member 4 laminated on the buildup layer 3 and filling between the plurality of connection terminals T1, and the opening 5a laminated on the filling member 4 and exposing the connection terminal T1 were formed. A plurality of connection terminals T11 are formed between the solder resist layer 5 and a mother board (not shown), the buildup layer 13 (back side) stacked on the back side of the core substrate 2, and the buildup layer 13 are stacked. And a solder resist layer 14 in which an opening 14a exposing at least a part of the connection terminal T11 is formed. *

The core substrate 2 is a plate-shaped resin substrate made of a heat resistant resin plate (for example, bismaleimide-triazine resin plate), a fiber reinforced resin plate (for example, glass fiber reinforced epoxy resin), or the like. Core conductor layers 21 and 22 forming metal wirings L1 and L11 are formed on the front surface and the back surface of the core substrate 2, respectively. The core substrate 2 is formed with a through-hole 23 drilled by a drill or the like, and a through-hole conductor 24 for connecting the core conductor layers 21 and 22 to each other is formed on the inner wall surface thereof. Further, the through hole 23 is filled with a resin hole filling material 25 such as an epoxy resin. *

(Configuration on the Front Side) On the front side of the wiring substrate 100, a lid plating layer 41 that is electrically connected to the core conductor layer 21 is formed. The lid plating 41 and the conductor layer 32 that constitutes the metal wiring L2 are filled vias. 42 is electrically connected. The filled via 42 has a via hole 42a and a via conductor 42b filled in the via hole 42a by plating. *

The connection terminal T1 formed on the conductor layer 32 of the wiring board 100 is a connection terminal with the semiconductor chip. The semiconductor chip is mounted on the wiring board 100 by being electrically connected to the connection terminal T1. The connection terminals T1 are arranged at substantially equal intervals over the entire semiconductor chip mounting area (component mounting area). The connection terminal T <b> 1 has a columnar shape that is circular when viewed from above, and is formed directly on the conductor layer 32 with the upper portion protruding from the surface of the filling member 4. Since the connection terminal T1 is formed directly on the conductor layer 32, it is not necessary to provide a land for the connection terminal T1, and the degree of freedom in wiring layout is improved.

FIG. 4 is a plan view of the connection terminal T1 and the metal wiring L2. FIG. 4A is a plan view of the metal wiring L2 that does not have the thick portion L2a in which the wiring width is increased at the position where the connection terminal T1 is formed. FIG. 4B is a plan view of the metal wiring L2 having a thick portion (first wide portion) L2a in which the wiring width is increased at a position where the connection terminal T1 is formed. *

As shown in FIG. 4A, the width W of the metal wiring L2 at the position where the connection terminal T1 is formed is less than the length (diameter) W1 of the connection terminal T1 in the direction coinciding with the width direction of the metal wiring L2. It is preferable that By setting the width W of the metal wiring L2 at the position where the connection terminal T1 is formed to be less than the length (diameter) W1 of the connection terminal T1 in the direction matching the width direction of the metal wiring L2, the width of the connection terminal T1 This is because it is possible to prevent the connection reliability with the semiconductor chip from being lowered. *

Further, the width W of the metal wiring L2 at the position where the connection terminal T1 is formed is not less than 0.5 times and less than 1.0 times the length W1 of the connection terminal T1 in the direction coinciding with the width direction of the metal wiring L2. Preferably there is. By making the width W of the metal wiring L2 at the position where the connection terminal T1 is formed 0.5 times or more and less than 1.0 times the length W1 in the width direction of the connection terminal T1, the connection terminal T1 is thinned. Therefore, it is possible to prevent the connection reliability with the semiconductor chip from being lowered, and the length W1 in the width direction of the connection terminal T1 is too long compared to the wiring width W, and is formed on the metal wiring L2. It is possible to prevent the connecting terminal T <b> 1 from tilting or falling. *

Further, when the metal wiring L2 is thin and the connection terminal T1 is formed directly on the metal wiring L2, the connection terminal T1 may be tilted or tilted as shown in FIG. 4B. A thick width portion L2a having a thick wiring width W can be provided at a position where the connection terminal T1 is formed. By having the thick portion L2a where the wiring width is increased at the position where the connection terminal T1 is formed, the metal wiring L2 has a narrow line width, or the connection terminal T1 has a long length W1 in the width direction. Even when the diameter of the connection terminal T1 is large, the connection terminal T1 can be formed directly on the metal wiring L2. *

Further, the length W2 in the extending direction of the thick portion L2a of the metal wiring L2 is 0.5 times or more and 2.0 times or less of the length W1 of the connection terminal T1 in the direction coinciding with the extending direction of the metal wiring L2. It is preferable to do. By making the length W2 of the thick portion L2a in the extending direction of the metal wiring L2 0.5 times or more and 2.0 times or less of the length W1 of the connection terminal T1 in the extending direction of the metal wire L2, the wide portion It can suppress that L2a becomes long in the extending | stretching direction and the freedom degree of wiring layout falls. *

Also, for the metal wiring L2 provided with the thick portion L2a, the width W at the position where the connection terminal T1 of the metal wiring L2 is formed is the length of the connection terminal T1 in the direction matching the width direction of the metal wiring L2. The length (diameter) is preferably less than L1, and more preferably 0.5 times or more and less than 1.0 times the length of the connection terminal T1 in the direction coinciding with the width direction of the metal wiring L2. *

The surface of each connection terminal T1 is roughened in order to improve the adhesion with the filling member 4. The surface of the connection terminal T1 can be roughened by, for example, processing with an etching solution such as MEC etch bond (manufactured by MEC). *

Even when the surface of each connection terminal T1 is not roughened, any one metal element of Sn (tin), Ti (titanium), Cr (chromium), and Ni (nickel) is coated on the surface of each connection terminal T1. Then, after forming the metal layer, the adhesion to the filling member 4 may be improved by applying a coupling agent treatment on the metal layer. *

Further, as shown in FIG. 3B, each connection terminal T1 has a step L formed on the outer periphery of the first main surface F, and an exposed surface of the connection terminal T1 including the step L is formed on the metal plating layer M. Covered by. When the semiconductor chip is mounted on the wiring substrate 100, the connection terminal of the semiconductor chip and the connection terminal T1 are electrically connected by reflowing the solder coated on the connection terminal of the semiconductor chip. The metal plating layer M is, for example, a single layer or a plurality of layers selected from metal layers such as a Ni layer, a Sn layer, an Ag layer, a Pd layer, and an Au layer (for example, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer). *

Further, instead of the metal plating layer M, an OSP (Organic Solderability Preservative) treatment for rust prevention may be performed. Further, the exposed surface of the connection terminal T1 including the step L may be coated with solder. Further, after the exposed surface of the connection terminal T1 including the step L is covered with the metal plating layer M, the metal plating layer M is soldered. May be coated. A method for coating the exposed surface of the connection terminal T1 with solder will be described later. *

The filling member 4 is filled between the connection terminals T1 in close contact with the side surfaces of the connection terminals T1 formed on the surface layer of the buildup layer 3. The thickness D2 of the filling member 4 is thinner than the thickness (height) D1 of the connection terminal T1. The filling method of the filling member 4 will be described later. *

The solder resist layer 5 covers the surface side of the wiring pattern connected to the connection terminal T1, and exposes the connection terminals T1 arranged at substantially equal intervals in the semiconductor chip mounting region, and a chip capacitor mounting. And an opening 5b for exposing the pad P1. The opening 5a of the solder resist layer 5 has an NSMD (non-solder mask-defined) shape in which a plurality of connection terminals T1 are arranged in the same opening. An alignment mark AM is formed on the solder resist layer 5. The alignment mark AM is not always necessary. *

(Configuration of Back Side) A lid plating layer 141 that is electrically connected to the core conductor layer 22 is formed on the back side of the wiring substrate 100, and the lid plating 141 and the conductor layer 132 are electrically connected by the filled via 142. Has been. The filled via 142 has a via hole 142a and a via conductor 142b filled in the via hole 142a by plating. Further, on the conductor layer 132, a connection terminal T11 to a mother board or the like (not shown) is directly formed without vias. *

The connection terminal T11 is used as a back surface land (PGA pad, BGA pad) for connecting the wiring board 100 to a mother board or the like, and is formed in an outer peripheral region excluding a substantially central portion of the wiring board 100. It is arranged in a rectangular shape so as to surround the central portion. Further, at least a part of the surface of the connection terminal T11 is covered with the metal plating layer M. *

The solder resist layer 14 is formed by laminating a film-like solder resist on the surface of the buildup layer 13. The solder resist layer 14 is formed with an opening 14a exposing a part of the surface of each connection terminal T11. For this reason, each connection terminal T11 is in a state in which a part of the surface is exposed from the solder resist layer 14 through the opening 14a. That is, the opening 14a of the solder resist layer 14 has an SMD shape in which a part of the surface of each connection terminal T11 is exposed. Unlike the opening 5a of the solder resist layer 5, the opening 14a of the solder resist layer 14 is formed for each connection terminal T11. *

In the opening 14a, for example, a solder ball B made of solder that does not substantially contain Pb, such as Sn—Ag, Sn—Cu, Sn—Ag—Cu, Sn—Sb, is connected to the connection terminal T11 via the metal plating layer M. It is formed so as to be electrically connected to. When the wiring board 100 is mounted on a mother board or the like, the connection terminals T11 are electrically connected to the connection terminals such as the mother board by reflowing the solder balls B of the wiring board 100. *

(Manufacturing Method of Wiring Board) FIGS. 2, 5 to 11 are diagrams showing manufacturing steps of the wiring board 100 according to the first embodiment. Hereinafter, a method for manufacturing the wiring substrate 100 will be described with reference to FIGS. 2 and 5 to 11. *

(Core substrate process: FIG. 5) A copper clad laminate having a copper foil attached to the front and back surfaces of a plate-shaped resin substrate is prepared. Further, a drilling process is performed on the copper-clad laminate using a drill, and a through hole that becomes the through hole 23 is formed in advance at a predetermined position. Then, by performing electroless copper plating and electrolytic copper plating according to a conventionally known method, a through-hole conductor 24 is formed on the inner wall of the through-hole 23, and a copper plating layer is formed on both surfaces of the copper-clad laminate (FIG. 5A). )reference). *

Thereafter, the inside of the through-hole conductor 24 is filled with a resin hole filling material 25 such as an epoxy resin. Further, electrolytic copper plating is performed according to a conventionally known method to form the lid plating layer 41. Next, the copper plating (including the lid plating layer 41) formed on the copper foils on both sides of the copper clad laminate is etched into a desired shape, and the metal wirings L1 and L11 are formed on the front and back surfaces of the copper clad laminate. The core conductor layers 21 and 22 to be formed are respectively formed to obtain the core substrate 2 (see FIG. 5B). In addition, it is desirable to perform the desmear process which removes the smear of a process part after the through-hole 23 formation process.

(Build-up process: FIG. 6) On the front and back surfaces of the core substrate 2, film-like insulating resin materials mainly composed of epoxy resin to be the resin insulating layers 31 and 131 are arranged so as to overlap each other. And this laminated body is pressurized and heated with a vacuum press-bonding hot press machine, and it crimps | bonds, heat-curing a film-form insulating resin material. Next, laser irradiation is performed using a conventionally known laser processing apparatus to form via holes 42a and 142a in the resin insulating layers 31 and 131, respectively (see FIG. 6A). *

Subsequently, after the surfaces of the resin insulating layers 31 and 131 are roughened, electroless plating is performed to form an electroless copper plating layer on the resin insulating layers 31 and 131 including the inner walls of the via holes 42a and 142a. Next, a photosensitive resin is laminated on the electroless copper plating layer formed on the resin insulating layers 31 and 131, and exposure and development are performed to form resin masks MR1 and MR11 in desired shapes. Thereafter, copper is plated by electrolytic plating using the resin masks MR1 and MR11 as a mask to obtain a desired copper plating pattern (metal wirings L2 and L12) (see FIG. 6B). *

(Convex plating layer forming step: FIG. 7) Next, without peeling off the resin masks MR1 and MR11, a photoresist is laminated, and exposure and development are performed to form the resin masks MR2 and MR12 in desired shapes. Thereafter, copper is plated by electrolytic plating using the resin masks MR2 and MR12 as a mask to obtain a desired copper plating pattern (see FIG. 7A). *

Next, the resin masks MR1, MR2, MR11, MR12 are peeled off, the electroless copper plating layer existing under the resin masks MR1, MR11 is removed, and the connection terminals T1, pads P1 are formed on the conductor layers 32, 132. And a conductor layer 134 having a connection terminal T11 are formed (see FIG. 7B). *

(Filling step: FIG. 8) Next, the space between the plurality of connection terminals T1 forming the surface layer of the buildup layer 3 is filled with the filling member 4 to a position lower than the main surface F of the connection terminal T1. In order to fill the space between the connection terminals T1 with the filling member 4, it is preferable to roughen the surface (particularly the side surface) of the connection terminal T1. The surface of the connection terminal T1 can be roughened by, for example, processing with an etching solution such as MEC etch bond (manufactured by MEC). Further, instead of roughening the surface of each connection terminal T1, any one metal element of Sn (tin), Ti (titanium), Cr (chromium), and Ni (nickel) is coated on the surface of each connection terminal T1. Then, after forming the metal layer, a coupling agent treatment may be performed on the metal layer to improve the adhesion to the filling member 4. *

Various methods can be adopted as a method of filling the filling member 4 between the connection terminals T1. Hereinafter, a filling method for filling the filling member 4 between the connection terminals T1 will be described. In the following first to fourth filling methods, various methods such as printing, laminating, roll coating, spin coating and the like can be used as a method for coating the insulating resin to be the filling member 4.

(First Filling Method) In this first filling method, the surface of the build-up layer 3 having the connection terminals T1 formed on the surface layer is thinly coated with a thermosetting insulating resin and thermally cured, and then cured. The filling member 4 is filled between the connection terminals T1 by polishing the insulating resin until it becomes lower than the connection terminals T1. *

(Second Filling Method) In this second filling method, the surface of the build-up layer 3 having the connection terminals T1 formed on the surface layer is thinly coated with a thermosetting insulating resin, and then the insulating resin is melted. After the excess insulating resin covering the upper surface of the connection terminal T1 is removed with a solvent, the filling member 4 is filled between the connection terminals T1 by thermosetting. *

(Third filling method) In this third filling method, the surface of the build-up layer 3 having the connection terminals T1 formed on the surface layer is coated with a thick thermosetting insulating resin and thermally cured, and then the semiconductor. The area other than the element mounting area is masked and the insulating resin is dry-etched by RIE (Reactive Ion Etching) or the like until it becomes lower than the connection terminal T1, thereby filling the filling member 4 between the connection terminals T1. When the filling member 4 is filled between the connection terminals T1 by this third filling method, the filling member 4 and the solder resist layer 5 are integrally formed. *

(Fourth Filling Method) FIG. 9 is an explanatory diagram of the fourth filling method. Hereinafter, the fourth filling method will be described with reference to FIG. In the fourth filling method, after the surface of the build-up layer 3 having the wiring conductor T1 formed on the surface layer is coated thickly with a photocurable insulating resin (see FIG. 9A), the opening of the solder resist layer is later formed. The insulating resin is exposed and developed while masking the inner region of the region to be 5a, and the insulating resin to be the outer region of the opening 5a is photocured (see FIG. 9B). Next, the wiring substrate 100 being manufactured is immersed in an aqueous solution of sodium carbonate (concentration of 1% by weight) for a short time (a time that the insulating resin surface of the unexposed portion is slightly swollen) (see FIG. 9C). ). Then, the insulating resin swollen by washing with water is emulsified (see FIG. 9D). Next, the swollen and emulsified insulating resin is removed from the wiring substrate 100 in the process of manufacture (see FIG. 9E). The above immersion and water washing are repeated once each or several times until the position of the upper end of the insulating resin that has not been photocured is lower than the upper end of each wiring conductor T1. Thereafter, the insulating resin is cured by heat or ultraviolet rays. When the filling member 4 is filled between the connection terminals T1 by the fourth filling method, the filling member 4 and the solder resist layer 5 are integrally formed. *

(Solder Resist Layer Step: FIG. 10) Film-like solder resist is pressed and laminated on the surfaces of the filling member 4 and the buildup layer 13, respectively. The laminated film-like solder resist is exposed and developed, and a part of the surface of each connection terminal T11 is formed with a solder resist layer 5 having an NSMD-shaped opening 5a that exposes the surface and side surfaces of each connection terminal T1. A solder resist layer 14 having an exposed SMD-shaped opening 14a is obtained. In addition, since the filling member 4 and the solder resist layer 5 are integrally formed when the third and fourth filling methods described above are employed in the filling step, it is necessary to laminate the solder resist layer 5 in this step. Absent. *

(Plating step: FIG. 11) Next, the exposed surface of the connection terminal T1 is etched with sodium persulfate or the like to remove impurities such as an oxide film on the surface of the connection terminal T1, and around the main surface F of the connection terminal T1. A step L is formed on the substrate (see FIG. 3). Thereafter, the metal plating layer M is formed on the exposed surfaces of the connection terminals T1 and T11 by electroless reduction plating using a reducing agent. When the metal plating layer M is formed on the exposed surface of the connection terminal T1 by electroless displacement plating, the metal on the exposed surface of the connection terminal T1 is replaced to form the metal plating layer M. For this reason, a step L is formed around the main surface F of the connection terminal T1 without etching the exposed surface of the connection terminal T1 with sodium persulfate or the like. *

Further, when solder is coated on the exposed surface of the connection terminal T1, the following two methods can be selected according to the thickness of the solder layer to be coated. *

(First coating method) When a solder layer having a thickness of 5 to 30 μm is coated on the exposed surface of the connection terminal T1, the exposed surface of the connection terminal T1 is slightly etched (soft etching) to form an exposed surface of the connection terminal T1. The formed oxide film is removed. At this time, a step L is formed around the main surface F of the connection terminal T1. Next, paste (for example, Harima Kasei Co., Ltd .: Super Solder (product name)) in which an ionic compound containing a metal such as Sn (tin) powder, Ag (silver), Cu (copper), and a flux is mixed is connected to a connection terminal. A thin coating is applied to the entire SMD-shaped opening 5a so as to cover the entire exposed surface of T1. Thereafter, reflow is performed to form a solder layer made of Sn and Ag or an alloy of Sn, Ag and Cu on the exposed surface of the connection terminal T1. *

(Second coating method) When a solder layer having a thickness of 10 μm or less is coated on the exposed surface of the connection terminal T1, the exposed surface of the connection terminal T1 is slightly etched (soft etching) to form the exposed surface of the connection terminal T1. The formed oxide film is removed. At this time, a step L is formed around the main surface F of the connection terminal T1. Next, an electroless Sn (tin) plating is performed on the exposed surface of the connection terminal T1 to form a Sn plating layer, and a flux is applied so as to cover the entire surface of the Sn plating layer. Thereafter, reflow is performed to melt the Sn plating layer plated on the connection terminal T1, and a solder layer is formed on the main surface F of the connection terminal T1. At this time, the melted Sn aggregates on the main surface F of the connection terminal T1 due to surface tension. *

(Back-end process: FIG. 2) After solder paste is applied onto the metal plating layer M formed on the connection terminal T11 by solder printing, reflow is performed at a predetermined temperature and time, and solder balls are formed on the connection terminal T11. B is formed. *

As described above, in the wiring substrate 100 according to the first embodiment, the connection terminal T1 is formed directly on the conductor layer 32 without vias. For this reason, it is not necessary to provide a land for the connection terminal T1, and the degree of freedom in wiring layout is improved. Further, the width W of the metal wiring L2 at the position where the connection terminal T1 is formed is less than the length (diameter) W1 of the connection terminal T1 in the direction matching the width direction of the metal wiring L2. For this reason, it can suppress that connection terminal T1 becomes small too much and connection reliability with a semiconductor chip falls. *

Further, the width W of the metal wiring L2 at the position where the connection terminal T1 is formed is 0.5 times or more and less than 1.0 times the length W1 of the connection terminal T1 in the direction matching the width direction of the metal wiring L2. Yes. For this reason, it is possible to suppress the connection terminal T1 from becoming smaller and reducing the connection reliability with the semiconductor chip, and to compare the width of the connection terminal T1 with the width direction of the metal wiring L2 compared to the wiring width W. It can be suppressed that the length W1 becomes too long and the connection terminal T1 formed on the metal wiring L2 is inclined or falls down. *

Further, a thick width portion L2a having a thick wiring width W is provided at a position where the connection terminal T1 is formed. For this reason, even when the line width of the metal wiring L2 is narrow, or when the length W1 of the connection terminal T1 in the direction coinciding with the width direction of the metal wiring L2 is long, that is, the diameter of the connection terminal T1 is large. The connection terminal T1 can be formed directly on L2. *

Furthermore, the length W2 in the extending direction of the thick portion L2a of the metal wiring L2 is set to be not less than 0.5 times and not more than 2.0 times the length W1 in the direction coinciding with the extending direction of the metal wiring L2 of the connection terminal T1. . For this reason, it can suppress that the wide part L2a becomes long in an extending | stretching direction, and the freedom degree of wiring layout falls.

As other effects, since the space between the connection terminals T1 is filled with the filling member 4, underfill or NCP (Non) which is filled in the gap between the semiconductor chip and the wiring board when connected to the semiconductor chip. It is possible to prevent the generation of voids between the connection terminals T1 of -Conductive Past) and NCF (Non-Conductive Film). For this reason, at the time of reflow, it can prevent that a solder flows into this void and a connection terminal is short-circuited (short-circuited). Further, since the exposed area of the connection terminal T1 is reduced, the diameter of the solder coated on the connection terminal is not increased, and the connection terminal T1 can be narrowed. *

Furthermore, when forming the metal plating layer M on the surface of the connection terminal T1, it is possible to prevent plating sagging between the connection terminals T1 and undercut where the bottom of the connection terminal T1 is etched. Furthermore, since the step L is formed on the outer periphery of the first main surface F of the connection terminal T1, the diameter of the solder coated on the connection terminal T1 does not increase, and the connection terminals T1 can be further narrowed. . *

Further, since the contact surface of the connection terminal T1 with the filling member 4 is roughened and the filling member 4 is filled between the connection terminals T1, the adhesive strength between the connection terminal T1 and the filling member 4 is improved. . For this reason, the possibility that the connection terminal 1 may be peeled off during the manufacturing process is suppressed. Further, by making the material of the filling member 4 the same as that of the solder resist layer 5, the solder flowability of the filling member 4 becomes approximately the same as that of the solder resist layer 5, and the solder remains on the filling member 4 and the connection terminal T 1. It is possible to suppress a short circuit between them. *

Further, the thickness D2 of the filling member 4 filled between the connection terminals T1 is made thinner than the thickness (height) D1 of the connection terminals T1. That is, the connection terminal T <b> 1 is slightly protruded from the upper surface of the filling member 4. For this reason, even when the center of the connection terminal of the semiconductor chip and the center of the connection terminal T1 are deviated, the connection terminal of the semiconductor chip abuts on the end of the connection terminal T1, so that the connection terminal T1 and the connection terminal of the semiconductor chip Connection reliability is improved. *

(Modification of First Embodiment) In the first embodiment described with reference to FIGS. 1 to 11, the wiring substrate 100 in which the connection terminal T1 is formed directly on the metal wiring L2 of the conductor layer 32 has been described. However, the via conductor may be formed directly on the metal wiring of the conductor layer. In the modification of the first embodiment, a wiring board in which via conductors are directly formed on metal wiring of a conductor layer will be described. *

FIG. 12 is a partial cross-sectional view of a wiring board 100A according to a modification of the first embodiment. FIG. 13 is a plan view of wiring and via conductors of the wiring board 100A. Hereinafter, the configuration of a wiring board 100A according to a modification of the first embodiment will be described with reference to FIGS. Note that the same components as those described with reference to FIGS. 1 to 11 are denoted by the same reference numerals, and redundant description is omitted. *

As shown in FIGS. 12 and 13, the wiring board 100 </ b> A includes a build-up layer 3, a conductor layer 36 constituting a metal wiring L <b> 3 laminated on the resin insulation layer 31, and a resin insulation layer laminated on the conductor layer 36. 37 and a filled via 43 which is directly formed on the metal wiring L3 forming the conductor layer 36 and penetrates the resin insulating layer 37 to connect the conductor layers 36 and 32 to each other. The filled via 43 has a via hole 43a and a via conductor 43b filled in the via hole 43a by plating. That is, the conductor layers 36 and 32 are electrically connected by the via conductor 43b. *

Further, the wiring board 100A forms the conductor layer 136 constituting the metal wiring L13 laminated on the resin insulation layer 131, the resin insulation layer 137 laminated on the conductor layer 136, and the conductor layer 136 on the buildup layer 13. Further, a filled via 143 that is directly formed on the metal wiring L13 and that penetrates the resin insulating layer 137 and connects the conductor layers 136 and 132 is further provided. The filled via 143 includes a via hole 143a and a via conductor 143b filled in the via hole 143a by plating. That is, the conductor layers 136 and 132 are electrically connected by the via conductor 143b. *

FIG. 14 is a plan view of filled vias 43 and 143 and metal wirings L3 and L13.

FIG. 14A is a plan view of the metal wirings L3 and L13 that do not have the thick portions L3a and L13a in which the wiring width is increased at the positions where the filled vias 43 and 143 are formed.

FIG. 14B is a plan view of the metal wirings L3 and L13 having thick portions (second wide portions) L3a and L13a where the wiring width is increased at the positions where the filled vias 43 and 143 are formed.

As shown in FIG. 14A, the width W of the metal wirings L3 and L13 at the positions where the filled vias 43 and 143 are formed is the length of the filled vias 43 and 143 in the direction matching the width direction of the metal wirings L3 and L13. The thickness (diameter) is preferably less than W1. By setting the width W of the metal wirings L3 and L13 at the positions where the filled vias 43 and 143 are formed to be less than the length (diameter) W1 of the filled vias 43 and 143 in the direction matching the width direction of the metal wirings L3 and L13. Further, it is possible to prevent the filled vias 43 and 143 from becoming too narrow and the connection reliability between the conductor layer 36 and the conductor layer 32 and between the conductor layer 136 and the conductor layer 132 from being lowered. *

Further, the width W of the metal wirings L3 and L13 at the position where the filled vias 43 and 143 are formed is 0.5 times or more the length W1 of the filled vias 43 and 143 in the direction coinciding with the width direction of the metal wirings L3 and L13. It is preferably less than 1.0 times. By setting the width W of the metal wirings L3 and L13 at the positions where the filled vias 43 and 143 are formed to 0.5 times or more and less than 1.0 times the length W1 in the width direction of the wiring of the filled vias 43 and 143, 43 and 143 can be reduced and the connection reliability between the conductor layer 36 and the conductor layer 32 and between the conductor layer 136 and the conductor layer 132 can be suppressed, and the width of the filled vias 43 and 143 compared to the wiring width W can be suppressed. It can be suppressed that the length W1 in the direction becomes too long and the filled vias 43 and 143 formed on the metal wirings L3 and L13 are tilted or fall down. *

Further, when the metal wirings L3 and L13 are thin and the filled vias 43 and 143 are formed directly on the metal wirings L3 and L13, the filled vias 43 and 143 may be inclined or fall down. As shown in b), the thick portions L3a and L13a with the increased wiring width W can be provided at the positions where the filled vias 43 and 143 are formed. When the filled vias 43 and 143 are formed at the positions where the thick wiring portions L3a and L13a have a wide wiring width, the metal wirings L3 and L13 have a narrow line width, or the filled vias 43 and 143 are long in the width direction. Even when the length W1 is long, that is, when the diameter of the filled vias 43 and 143 is large, the filled vias 43 and 143 can be formed directly on the metal wirings L3 and L13. *

Further, the length W2 in the extending direction of the thick portions L3a and L13a of the metal wirings L3 and L13 is 0.5 times the length W1 of the filled vias 43 and 143 in the direction coinciding with the extending direction of the metal wirings L3 and L13. It is preferable to set it to 2.0 times or less. The length W2 of the thick portions L3a and L13a in the extending direction of the metal wirings L3 and L13 is 0.5 times or more and 2.0 times or less of the length W1 of the filled vias 43 and 143 in the extending direction of the metal wirings L3 and L13. By doing so, it can suppress that the wide part L3a and L13a become long in an extending | stretching direction, and the freedom degree of wiring layout falls. *

In addition, regarding the metal wirings L3 and L13 provided with the thick portions L3a and L13a, the width W at the position where the filled vias 43 and 143 of the metal wirings L3 and L13 are formed is equal to the width of the metal wirings L3 and L13 of the filled vias 43 and 143. The length (diameter) W1 is preferably less than the length (diameter) W1 in the direction matching the width direction of L13, and 0.5 times or more the length of the filled vias 43 and 143 in the direction matching the width direction of the metal wires L3 and L13 More preferably, it is less than 0.0 times. *

15 and 16 are manufacturing process diagrams of the wiring board 100A. Hereinafter, a method for manufacturing the wiring substrate 100A will be described with reference to FIGS. The processes other than the build-up process are the same as those in the method for manufacturing the wiring board 100 described with reference to FIGS. Here, only the build-up process in the manufacturing method of the wiring board 100A will be described, and redundant description of the other processes will be omitted. *

(Build-up process: FIG. 15) Film-like insulating resin materials mainly composed of epoxy resin to be the resin insulating layers 31 and 131 are arranged on the front surface and the back surface of the core substrate 2 so as to overlap each other. And this laminated body is pressurized and heated with a vacuum press-bonding hot press machine, and it crimps | bonds, heat-curing a film-form insulating resin material. Next, laser irradiation is performed using a conventionally known laser processing apparatus to form via holes 42a and 142a in the resin insulating layers 31 and 131, respectively (see FIG. 15A). *

Subsequently, after the surfaces of the resin insulating layers 31 and 131 are roughened, electroless plating is performed to form an electroless copper plating layer on the resin insulating layers 31 and 131 including the inner walls of the via holes 42a and 142a. Next, an insulating photosensitive resin is laminated on the electroless copper plating layer formed on the resin insulating layers 31 and 131, and exposure and development are performed to form resin masks MR3 and MR13 in desired shapes. Thereafter, copper is plated by electrolytic plating using the resin masks MR3 and MR13 as a mask to obtain a desired copper plating pattern (metal wirings L3 and L13) (see FIG. 15B). *

(Build-up process: FIG. 16) Next, without peeling off the resin masks MR3 and MR13, an insulating photosensitive resin is laminated, exposed and developed to form the resin masks MR4 and MR14 in a desired shape. To do. Thereafter, copper is plated by electrolytic plating using the resin masks MR4 and MR14 as a mask to obtain a desired copper plating pattern (filled vias 43 and 143) (see FIG. 16A). The resin masks MR3 and MR4 and MR13 and MR14 become insulating resin layers 37 and 137, respectively. *

Subsequently, a photoresist is laminated on the resin insulating layers 37 and 137, and exposure and development are performed to form resin masks MR5 and MR15 in a desired shape. Thereafter, copper is plated by electrolytic plating using the resin masks MR5 and MR15 as a mask to obtain a desired copper plating pattern (metal wirings L2 and L12) (see FIG. 16B). *

As described above, in the wiring board 100A according to the modification of the first embodiment, the via holes 43a and 143b for the filled vias 43 and 143 are formed by exposure and development instead of laser irradiation when the filled vias 43 and 143 are formed. Therefore, there is no need to form a via land serving as a stopper for laser irradiation. Therefore, filled vias 43 and 143 can be directly formed on metal wirings L3 and L13 forming conductor layers 36 and 136, respectively. *

Further, the width of the metal wirings L3 and L13 forming the conductor layers 36 and 136 at the position where the filled vias 43 and 143 are formed is 0.5 times or more and less than 1.0 times the length of the filled vias 43 and 143 in the width direction. It is said. For this reason, the pitch between the filled vias 43 and the filled vias 143 can be narrowed, and the degree of freedom in wiring layout is improved. Further, the connection reliability between the filled vias 43 and 143 and the metal wirings L3 and L13 forming the conductor layers 36 and 136 and the filled vias 43 and 143 and the metal wirings L2 and L12 forming the conductor layers 32 and 132 is reduced. Can be suppressed. *

Further, as shown in FIG. 14B, the metal wirings L3 and L13 forming the conductor layers 36 and 136 of the wiring board 100A are thicker at the positions where the filled vias 43 and 143 are formed. It can have parts L3a and L13a. By having the thick width portions L3a and L13a where the wiring width is increased at the position where the filled vias 43 and 143 are formed, the filled vias 43 and 143 having a large diameter can be directly formed on the metal wirings L3 and L13. Further, the connection reliability between the filled vias 43 and 143 and the metal wirings L3 and L13 forming the conductor layers 36 and 136 and the filled vias 43 and 143 and the metal wirings L2 and L12 forming the conductor layers 32 and 132 is improved. *

Furthermore, the length in the extending direction of the metal wirings L3 and L13 forming the conductor layers 36 and 136 of the thick portions L3a and L13a is 0.5 times or more and 2.0 times the length in the extending direction of the filled vias 43 and 143. It can be as follows. The length in the extending direction of the metal wirings L3 and L13 forming the conductor layers 36 and 136 of the thick portions L3a and L13a is 0.5 to 2.0 times the length in the extending direction of the filled vias 43 and 143. By doing so, it can suppress that the wide part L3a and L13a become too long in the extending | stretching direction, and the freedom degree of wiring layout falls. *

In the above description, the filled vias 43 and 143 are formed directly on the metal wirings L3 and L13 forming the conductor layers 36 and 136. However, the conductor layers 21 and 22 are also applied to other filled vias, for example, the filled vias 42 and 142. It may be configured to be formed directly on the metal wirings L1 and L11 forming.

Second Embodiment FIG. 17 is a plan view (surface side) of a wiring board 200 according to a second embodiment. As shown in FIG. 17, the connection terminal T <b> 1 serves as a signal connection terminal T <b> 1 (indicated by a broken line) only on the outer peripheral portion of the mounting region (component mounting region) of the semiconductor chip (component) mounted on the wiring substrate 200. It is preferable that a plurality of power supply and ground connection pads P2 (shown by solid lines) are arranged in the center of the mounting region. By using the connection terminal T1 as the signal connection terminal T1 whose wiring length is long and wiring is difficult, wiring can be easily routed and the degree of freedom of wiring layout can be improved. Also, by arranging a plurality of power and ground connection pads P2 in the center of the mounting area, the length of the power and ground wiring can be shortened. *

Third Embodiment FIG. 18 is a plan view (front side) of a wiring board 300 according to a third embodiment. FIG. 19 is a partial cross-sectional view of the wiring board 200 taken along line II in FIG. Hereinafter, the configuration of the wiring board 300 will be described with reference to FIGS. 18 and 19. However, the same configuration as the wiring board 100 according to the first embodiment described with reference to FIGS. The same reference numerals are assigned and duplicate descriptions are omitted. *

In the wiring substrate 100 according to the first embodiment described with reference to FIGS. 1 to 11, a film-like solder resist is pressed and laminated on the surface of the filling member 4, and the laminated film-like solder resist is laminated. Is exposed and developed to form a solder resist layer 5 having an NSMD-shaped opening 5a that exposes the surface and side surfaces of each connection terminal T1. However, the solder resist layer 5 may not be provided in FIGS. The effects of the wiring board 300 according to the third embodiment are the same as those of the wiring board 100 according to the first embodiment. *

Fourth Embodiment FIG. 20 is a plan view (surface side) of a wiring board 400 according to a fourth embodiment. FIG. 21 is an enlarged plan view of region A in FIG. Hereinafter, the configuration of the wiring board 400 will be described with reference to FIGS. 20 and 21, and the first to third embodiments described with reference to FIGS. 1 to 19 will be described. Components having the same configuration as 300 are denoted by the same reference numerals and redundant description is omitted. *

In the wiring substrate 400 according to the fourth embodiment, the opening 5a of the solder resist layer 5 has a so-called peripheral shape provided around the semiconductor chip mounting region. The effect of the wiring board 400 according to the fourth embodiment is the same as that of the wiring board 100 according to the first embodiment. *

(Other Embodiments) In the wiring boards 100, 100A, and 200 to 400 described with reference to FIGS. 1 to 21, the upper surfaces of the filling members 4 filled between the connection terminals T1 are flat. However, the upper surface of the filling member 4 is not necessarily flat (flat). For example, as shown in FIG. 22, the filling member 4 has a rounded upper surface, so-called fillet shape. Similar effects can be obtained. *

As described above, the present invention has been described in detail with specific examples.

The present invention is not limited to the above contents, and various modifications and changes can be made without departing from the scope of the present invention.

For example, in the above specific example, the embodiment has been described in which the wiring boards 100, 100A, and 200 to 400 are BGA boards that are connected to a mother board or the like via the solder balls B, but instead of the solder balls B, pins or lands are used. The provided wiring boards 100, 100A, 200 to 400 may be connected to a mother board or the like as a so-called PGA (Pin Grid Array) board or LGA (Land Grid Array) board.

Further, the connection terminal T1 has a columnar shape that is circular in a top view, but may have other shapes, for example, a quadrangular column shape that forms a square in a top view or a triangular column shape that forms a triangle in a top view. Also in the first and third embodiments, as shown in FIG. 17, the connection terminal T1 is a signal connection terminal T1, which is a semiconductor chip (component) mounted on the wiring boards 100, 100A, 300. The power supply and ground connection pads P2 may be arranged on the outer peripheral side of the mounting region (component mounting region) and on the center side of the mounting region. *

Further, in this embodiment, when the first filling method or the second filling method is adopted, the solder resist layer 5 is formed after the filling member 4 is formed, but the filling is performed after the solder resist layer 5 is formed. The member 4 may be filled between the connection terminals T1.

AM ... Alignment mark, B ... Solder ball, F ... Main surface, L ... Step, L1, L2, L3 ... Metal wiring, L11, L12, L13 ... Metal wiring, L2a, L3a, L13a ... Wide portion, M ... Metal Plated layer, MR1 to MR5, MR11 to MR15 ... resin mask, P1, P2 ... pad, T1, T11 ... connection terminal, 100, 100A, 200-400 ... wiring substrate, 2 ... core substrate, 3 ... build-up layer, 4 ... Filling member, 5 ... Solder resist layer, 5a, 5b ... Opening, 13 ... Build-up layer, 14 ... Solder resist layer, 14a ... Opening, 21, 22 ... Core conductor layer, 23 ... Through hole, 24 ... Through hole conductor 25 ... Resin filling material, 31 ... Resin insulating layer, 31, 131 ... Resin insulating layer, 32, 132 ... Conductor layer, 34, 134 ... Conductor layer, 36, 136 ... Conductor layer, 3 , 137 ... resin insulating layer, 41 ... cover plated layer, 42,43,142,143 ... filled via.

Claims (10)

A wiring board having a laminate in which one or more insulating layers and conductor layers are laminated,

A plurality of wirings formed on the laminate;

Columnar connection terminals directly formed on at least some of the plurality of wires,

With

The wiring board, wherein a width of the at least part of the wiring at a position where the connection terminal is formed is less than a length of the connection terminal in the width direction. The width at a position where the connection terminal of the at least part of the wiring is formed is 0.5 times or more and less than 1.0 times the length of the connection terminal in the width direction. Wiring board as described in. 3. The wiring board according to claim 1, wherein the at least part of the wiring has a first wide width portion where a wiring width is thick at a position where the connection terminal is formed. 4. The length in the extending direction of the at least part of the first wide width portion is not less than 0.5 times and not more than 2.0 times the length of the connecting terminal in the extending direction. The wiring board according to claim 3. 5. The wiring board according to claim 1, further comprising a solder resist layer that covers the plurality of wirings and exposes at least a part of the connection terminals. 6. The wiring board according to claim 5, wherein at least a part of the connection terminal protrudes from a surface of the solder resist layer. A plurality of the connection terminals are arranged as signal connection terminals only on the outer periphery of a rectangular component mounting region set on the laminate, and a power and ground connection pad is provided at the center of the component mounting region. The wiring board according to claim 1, wherein a plurality of are arranged. The multilayer body is formed by alternately laminating a plurality of the conductor layers and a plurality of the insulating layers, and is formed directly on the plurality of wirings forming the conductor layer, and penetrates the insulating layer to form the conductor. A via conductor connecting the layers is provided, and the width of the wiring forming the conductor layer at the position where the via conductor is formed is 0.5 times or more and less than 1.0 times the length of the via conductor in the width direction. The wiring board according to claim 1, wherein the wiring board is a wiring board. The wiring board according to claim 8, wherein the wiring forming the conductor layer has a second thick portion having a thick wiring width at a position where the via conductor is formed. The length in the extending direction of the wiring forming the conductor layer of the second thick portion is 0.5 to 2.0 times the length of the via conductor in the extending direction. The wiring board according to claim 9.

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