JP2007150111A - Wiring board - Google Patents

Wiring board Download PDF

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Publication number
JP2007150111A
JP2007150111A JP2005344627A JP2005344627A JP2007150111A JP 2007150111 A JP2007150111 A JP 2007150111A JP 2005344627 A JP2005344627 A JP 2005344627A JP 2005344627 A JP2005344627 A JP 2005344627A JP 2007150111 A JP2007150111 A JP 2007150111A
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conductor
filler
hole
wiring board
lid
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JP2007150111A5 (en
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Seiji Mori
聖二 森
Hiroyuki Deguchi
洋行 出口
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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Priority to JP2005344627A priority Critical patent/JP2007150111A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board excellent in an adhesion without causing a delamination of a conductive layer when a filler is filled in a through-hole and the conductive layer is provided on it. <P>SOLUTION: The wiring board comprises a core part 2 with a tubular through-hole conductor 30 and a filling material 31 for filling the inside of it formed is provided in a through-hole 12 for penetrating through in a plate thickness direction. The filling material 31 of the wiring board 1 comprises a resin material including an inoraganic filler, the ten points average roughness (Rz) regulated by the JIS-B-0601 at the end surface 31a of the filling material 31 fills Rz≤X/2 when the average particle diamter of the inorganic filler is X(μm), and the end surface 31a of the filling material 31 is covered by a cap conductor 21 connected to the through-hole conductor 30. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、配線基板に関する。   The present invention relates to a wiring board.

配線基板は、その一主面にLSIやICチップ等の電子部品を搭載する際に用いる多数の導体(電極)を備えており、他方の主面にはマザーボードなどと接続するための多数の導体(電極)及びそれに設置された接続端子(例えば、ハンダボール)を備えたものとされている。このようなタイプの配線基板においては、搭載するLSIやICチップあるいはチップコンデンサなどの電子部品の高集積化および高密度化を図るために、小型化や接続端子数(例えば、ボール数)の増大化等が進められている。   The wiring board has a large number of conductors (electrodes) used for mounting electronic components such as LSIs and IC chips on one main surface, and a large number of conductors for connection to a motherboard on the other main surface. (Electrodes) and connection terminals (for example, solder balls) installed thereon are provided. In such a type of wiring board, downsizing and increase in the number of connection terminals (for example, the number of balls) are required in order to achieve high integration and high density of electronic components such as LSIs, IC chips or chip capacitors to be mounted. Is being promoted.

従来技術として特許文献1には、高密度の配線機能を有する配線基板の内部構造として、絶縁性の基板に形成されたスルーホール内に充填材を充填し、この上に導体層を設け、この導体層に直接接続するビア導体を形成したものが開示されている。この技術によれば、スルーホール上にもビア導体を形成することができるため、配線の高集積化および高密度化を図ることができる。
特開平6−275959号公報
As a prior art, in Patent Document 1, as an internal structure of a wiring board having a high-density wiring function, a filler is filled in a through hole formed in an insulating substrate, and a conductor layer is provided thereon, A device in which a via conductor directly connected to a conductor layer is formed is disclosed. According to this technique, a via conductor can be formed also on a through hole, so that high integration and high density of wiring can be achieved.
JP-A-6-275959

しかしながら、特許文献1では、充填材に多官能エポキシ樹脂等の流動性有機系前駆体が挙げられているが、この場合、高温多湿等の過酷な条件下ではスルーホール充填材端面上に形成される導体層のデラミネーションが発生し、その導体層に直接接続するビア導体とスルーホール導体との電気的接続信頼性が得られないという問題があった。   However, in Patent Document 1, a fluid organic precursor such as a polyfunctional epoxy resin is cited as the filler. In this case, the filler is formed on the end surface of the through-hole filler under severe conditions such as high temperature and humidity. There is a problem in that delamination of the conductive layer occurs and reliability of electrical connection between the via conductor and the through-hole conductor directly connected to the conductive layer cannot be obtained.

デラミネーションの発生は、樹脂材と金属材との間に生じる熱膨張率の差が起因している(樹脂材のほうが金属材のそれよりも大きい)。例えば配線基板1が加熱された場合(図5(a)参照)に、金属材であるスルーホール導体30と、樹脂材料であるコア部2を構成する樹脂材25と、スルーホール12内に充填される充填材31とは、それぞれ板厚方向に膨張する。このとき、スルーホール導体30の熱膨張率に比べて、そのスルーホール導体の接する周囲樹脂材(樹脂材25及び充填材30)の熱膨張率の方が大きいため蓋状導体21は突き上げられる。また、逆に配線基板が冷却された場合(図5(b)参照)には、加熱された場合と逆の現象が起きる。その樹脂材料(樹脂材25及び充填材30)の収縮により蓋状導体21は引き下げられる。この温度サイクルにより、蓋状導体21に過度の応力集中が生じ、図5(c)に示すように、蓋状導体21と充填材の端面31aの間に空隙50が生じてしまう。即ち、蓋状導体21は、充填材の端面31aから剥離(デラミネーション)してしまう。   The occurrence of delamination is caused by the difference in coefficient of thermal expansion generated between the resin material and the metal material (the resin material is larger than that of the metal material). For example, when the wiring board 1 is heated (see FIG. 5A), the through hole conductor 30 that is a metal material, the resin material 25 that constitutes the core portion 2 that is a resin material, and the through hole 12 are filled. The filler 31 to be expanded expands in the plate thickness direction. At this time, since the thermal expansion coefficient of the surrounding resin material (resin material 25 and filler 30) with which the through-hole conductor is in contact is larger than the thermal expansion coefficient of the through-hole conductor 30, the lid-shaped conductor 21 is pushed up. On the other hand, when the wiring board is cooled (see FIG. 5B), a phenomenon opposite to that when the wiring board is heated occurs. The lid-like conductor 21 is pulled down by contraction of the resin material (resin material 25 and filler 30). Due to this temperature cycle, excessive stress concentration occurs in the lid-like conductor 21, and as shown in FIG. 5C, a gap 50 is created between the lid-like conductor 21 and the end face 31a of the filler. That is, the lid-like conductor 21 is peeled off (delaminated) from the end face 31a of the filler.

そこで、そのような条件下でも蓋状導体21と充填材の端面31aとの接続信頼性を低下させない配線基板が求められ、蓋状導体21と充填材の端面31aとの密着強度をより強めるために充填材の端面31aに粗化処理を行い、その端面31aを粗面化することで蓋状導体にアンカー効果を持たせたものが一般的に知られている。しかしながら、充填材の端面に粗化処理を行い、蓋状導体にアンカー効果をもたせたものでも、その蓋状導体が充填材の端面から剥離(デラミネーション)が発生してしまう場合があり、信頼性のある十分な密着強度が得られないという問題があった。   Therefore, a wiring board that does not lower the connection reliability between the lid-like conductor 21 and the end face 31a of the filler under such conditions is required, and the adhesion strength between the lid-like conductor 21 and the end face 31a of the filler is further increased. It is generally known that the end face 31a of the filler is roughened and the end face 31a is roughened to give the lid conductor an anchor effect. However, even if the end face of the filler is roughened and the lid conductor has an anchor effect, the lid conductor may be peeled off (delamination) from the end face of the filler. There was a problem that sufficient adhesive strength with sufficient properties could not be obtained.

本発明の課題は、上記実情に鑑みてなされたものであり、スルーホールに充填材を充填し、その上に導体層を設けた場合に、その導体層がデラミネーションを発生することなく、密着性に優れた配線基板を提供することにある。   An object of the present invention has been made in view of the above circumstances, and when a through hole is filled with a filler and a conductor layer is provided thereon, the conductor layer does not cause delamination and adheres closely. An object of the present invention is to provide a wiring board having excellent properties.

課題を解決するための手段及び効果Means and effects for solving the problems

上記課題を解決するために、本発明の配線基板は、
板厚方向に貫通するスルーホール内に筒状のスルーホール導体及びその内側を充填する充填材が形成されたコア部を備える配線基板であって、
充填材は無機フィラーを含む樹脂材料で構成され、該無機フィラーの平均粒径をX(μm)としたとき、当該充填材の端面におけるJIS−B−0601に規定する十点平均粗さ(Rz)がRz≦X/2を満たし、当該充填材の端面がスルーホール導体と接続された蓋状導体に覆われてなることを特徴とする。
In order to solve the above problems, the wiring board of the present invention is:
A wiring board including a core part in which a cylindrical through-hole conductor and a filler filling the inside thereof are formed in a through-hole penetrating in the plate thickness direction,
The filler is composed of a resin material containing an inorganic filler. When the average particle size of the inorganic filler is X (μm), the ten-point average roughness (Rz) defined in JIS-B-0601 on the end face of the filler. ) Satisfies Rz ≦ X / 2, and the end face of the filler is covered with a lid-like conductor connected to the through-hole conductor.

上記本発明によれば、充填材の端面のJIS−B−0601に規定の十点平均粗さRzを充填材に含まれる無機フィラーの平均粒径の半分以下とすることで、粗面化による充填材端面から一部露出する無機フィラーの充填材と接触して接着している領域を十分に確保することができるため、無機フィラーが充填材から脱落することを防止することができる。よって、無機フィラーが充填材から脱落しないので、蓋状導体を充填材の端面上により密着した状態で備えることができる。すなわち、上記温度サイクルによる過度の応力集中が生じてもデラミネーションを発生することなく、密着性が良好な蓋状導体を充填材端面上に備えることができ、ひいては電気的接続性に優れる高密度な配線基板を提供することが可能となる。   According to the present invention, the ten-point average roughness Rz defined in JIS-B-0601 of the end face of the filler is made half or less of the average particle diameter of the inorganic filler contained in the filler, thereby roughening the surface. Since it is possible to sufficiently secure a region in contact with and adhering to the filler of the inorganic filler that is partially exposed from the end face of the filler, it is possible to prevent the inorganic filler from falling off the filler. Therefore, since the inorganic filler does not fall off from the filler, the lid-like conductor can be provided in a more closely contacted state on the end face of the filler. That is, even if excessive stress concentration occurs due to the above temperature cycle, a lid-like conductor having good adhesion can be provided on the end face of the filler without causing delamination, and as a result, a high density with excellent electrical connectivity. It becomes possible to provide a simple wiring board.

また、本発明の配線基板は、
充填材の端面の十点平均粗さ(Rz)をX/3≦Rzとすることができる。これにより、充填材の端面の平均粗さRzを充填材に含まれる無機フィラーの平均粒径の3分の1以上とすることで、十分なアンカー効果が得られる表面粗さとすることができる。よって、蓋状導体を充填材の端面上に密着した状態で備えることができる。すなわち、上記温度サイクルによる過度の応力集中が生じてもデラミネーションを発生することなく、密着性が良好な蓋状導体を充填材端面上に備えることができ、ひいては電気的接続性に優れる高密度な配線基板を提供することが可能となる
The wiring board of the present invention is
The ten-point average roughness (Rz) of the end face of the filler can be set to X / 3 ≦ Rz. Thereby, it can be set as the surface roughness from which sufficient anchor effect is acquired by making the average roughness Rz of the end surface of a filler into 1/3 or more of the average particle diameter of the inorganic filler contained in a filler. Therefore, the lid-like conductor can be provided in a state of being in close contact with the end face of the filler. That is, even if excessive stress concentration occurs due to the above temperature cycle, a lid-like conductor having good adhesion can be provided on the end face of the filler without causing delamination, and as a result, a high density with excellent electrical connectivity. It becomes possible to provide a simple wiring board

なお、充填材に含まれるシリカフィラー等の無機フィラーの平均粒径は2μm〜5μmの範囲を満たしていることが望ましい。より好ましくは、無機フィラーの平均粒径を2μm〜4μmの範囲を満たしていることが望ましい。無機フィラーの平均粒径が大きすぎると充填材の端面が粗面化されたときに、その端面から無機フィラーの露出する領域が広くなり、充填材と接触して接着している領域を十分に確保することができないため無機フィラーは充填材から脱落してしまい、ひいては蓋状導体との十分な密着性が望めない。また、無機フィラーの平均粒径が小さすぎると、表面粗さも小さくなるため十分なアンカー効果を有する表面粗さとすることができず、蓋状導体との十分な密着性が望めない。   In addition, it is desirable that the average particle diameter of the inorganic filler such as silica filler contained in the filler satisfies the range of 2 μm to 5 μm. More preferably, it is desirable that the average particle size of the inorganic filler satisfies the range of 2 μm to 4 μm. When the average particle size of the inorganic filler is too large, when the end face of the filler is roughened, the area where the inorganic filler is exposed from the end face becomes wide, and the area that is in contact with the filler is sufficiently bonded. Since it cannot be ensured, the inorganic filler falls off the filler, and as a result, sufficient adhesion with the lid-like conductor cannot be expected. On the other hand, if the average particle size of the inorganic filler is too small, the surface roughness is also small, so that the surface roughness having a sufficient anchor effect cannot be obtained, and sufficient adhesion with the lid-like conductor cannot be expected.

また、本発明の配線基板は、
コア部の主面上に形成された樹脂絶縁層に埋設され蓋状導体と接続されたビア導体を備え、当該ビア導体が前記スルーホール上に位置することができる。また、ビア導体がスルーホール上の中央領域に位置することもできる。
The wiring board of the present invention is
A via conductor embedded in a resin insulating layer formed on the main surface of the core portion and connected to a lid-like conductor may be provided, and the via conductor may be located on the through hole. Also, the via conductor can be located in the central region on the through hole.

前述したように、樹脂材と金属材とは熱膨張率が異なるので、ビア導体(金属材)と樹脂絶縁層(樹脂材)との間にも熱膨張率の差が生じることから、温度サイクルによる膨張及び収縮の影響をうける。このビア導体が蓋状導体上に形成されると、ビア導体が蓋状導体上に形成されない場合と比して蓋状導体により大きな応力が生じ、蓋状導体は充填材の端面から剥離(デラミネーション)し易くなる。また、その応力は、ビア導体をスルーホール上の中央領域に形成したときに一番大きく生じ、蓋状導体は充填材の端面から剥離(デラミネーション)し易くなる。本発明の配線基板では、そのような状況下でも剥離(デラミネーション)が生じることなく安定して蓋状導体上にビア導体を設けることができ、さらには、一番大きく応力が生じるスルーホール上の中央領域にもビア導体を設けることができる。ここで、本発明におけるスルーホール上とは、コア部から板厚方向に樹脂絶縁層を形成(積層)していく方向を上向きとしている。   As described above, since the thermal expansion coefficient is different between the resin material and the metal material, a difference in thermal expansion coefficient also occurs between the via conductor (metal material) and the resin insulating layer (resin material). Affected by expansion and contraction. When this via conductor is formed on the lid-like conductor, a greater stress is generated by the lid-like conductor than when the via conductor is not formed on the lid-like conductor, and the lid-like conductor is peeled off from the end face of the filler (de- Easy to laminate). Further, the stress is greatest when the via conductor is formed in the central region on the through hole, and the lid-like conductor is easily peeled (delaminated) from the end face of the filler. In the wiring board of the present invention, a via conductor can be stably provided on the lid-like conductor without causing delamination even under such circumstances, and further, on the through hole where stress is most greatly generated. Via conductors can also be provided in the central region. Here, on the through hole in the present invention, the direction in which the resin insulating layer is formed (laminated) from the core portion in the plate thickness direction is upward.

また、本発明の配線基板は、
コア部の主面上に形成された2層以上の樹脂絶縁層にそれぞれビア導体が埋設され、該ビア導体が板厚方向に連なってスタックドビアを構成するとともに、当該スタックドビアが前記蓋状導体上に位置することができる。通常、スタックドビアは、複数のビア導体が板厚方向に連なって形成されており、ビア導体である金属材と樹脂絶縁層である樹脂材との接する距離が長い(面積が広い)ため、その一番下方にあるビア導体と接続される蓋状導体により大きな応力が生じる。しかし、そのような状況下においても蓋状導体が充填材の端面から剥離(デラミネーション)が生じることなく安定して蓋状導体上にスタックドビアを設けることができる。
The wiring board of the present invention is
Via conductors are respectively embedded in two or more resin insulation layers formed on the main surface of the core, and the via conductors are connected in the thickness direction to form a stacked via, and the stacked via is formed on the lid-shaped conductor. Can be located. Normally, a stacked via is formed by connecting a plurality of via conductors in the thickness direction, and the distance between the metal material that is the via conductor and the resin material that is the resin insulating layer is long (the area is large). A large stress is generated by the lid-like conductor connected to the lowermost via conductor. However, even in such a situation, the stacked conductor can be stably provided on the lid-shaped conductor without causing the delamination of the lid-shaped conductor from the end face of the filler.

以下、本発明の実施の形態を、図面を用いて説明する。
図1は本発明の一実施形態に係る配線基板1の断面構造を模式的に示すものである。該配線基板1は、耐熱性樹脂板(例えばビスマレイミド−トリアジン樹脂板)や、繊維強化樹脂板(例えばガラス繊維強化エポキシ樹脂)等で構成された板状コア(コア部)2の両表面MP1,MP2に、所定の配線パターンをなすコア導体層M1,M11がそれぞれ形成される。これらコア導体層M1,M11は板状コア2の表面の大部分を被覆する面導体パターンとして形成され、電源層又は接地層として用いられるものである。他方、板状コア2には、ドリル等により穿設されたスルーホール12が形成され、その内壁面にはコア導体層M1,M11を互いに導通させる内面メッキ層(スルーホール導体)30が形成されている。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 schematically shows a cross-sectional structure of a wiring board 1 according to an embodiment of the present invention. The wiring board 1 has both surfaces MP1 of a plate-like core (core part) 2 made of a heat-resistant resin plate (for example, bismaleimide-triazine resin plate), a fiber reinforced resin plate (for example, glass fiber reinforced epoxy resin), or the like. , MP2 are respectively formed with core conductor layers M1, M11 having a predetermined wiring pattern. These core conductor layers M1 and M11 are formed as surface conductor patterns that cover most of the surface of the plate-like core 2, and are used as a power supply layer or a ground layer. On the other hand, the plate-like core 2 is formed with a through-hole 12 drilled by a drill or the like, and an inner surface plating layer (through-hole conductor) 30 for connecting the core conductor layers M1 and M11 to each other is formed on the inner wall surface. ing.

また、スルーホール12には、平均粒径X(μm)が2〜5μmとなるシリカフィラー等の無機フィラーを含むエポキシ樹脂等の樹脂製穴埋め材(充填材)31がスルーホール導体30の内側に充填形成されており、その充填材31の端面31aは、JIS−B−0601に規定する十点平均粗さ(Rz)がX/3≦Rz≦X/2(本実施例においては、2.5μm以下)となるように粗面化されて形成されている。充填材31の端面31a上には、スルーホール導体30の端部と接続されたCuメッキからなる蓋状導体21が粗面化された端面31aと密着して形成されている。   Further, in the through hole 12, a resin hole filling material (filler) 31 such as an epoxy resin containing an inorganic filler such as a silica filler having an average particle diameter X (μm) of 2 to 5 μm is provided inside the through hole conductor 30. The end surface 31a of the filling material 31 has a ten-point average roughness (Rz) defined in JIS-B-0601 of X / 3 ≦ Rz ≦ X / 2 (in this embodiment, 2. 5 μm or less). On the end face 31a of the filler 31, a lid-like conductor 21 made of Cu plating connected to the end of the through-hole conductor 30 is formed in close contact with the roughened end face 31a.

また、コア導体層M1,M11の上層には、コア導体層M1,M11も含め配線積層部L1,L2が形成されている。具体的には、感光性または熱硬化性樹脂組成物6にて構成された第1樹脂絶縁層(ビルドアップ樹脂絶縁層)V1,V11がそれぞれ形成されている。さらに、その表面にはそれぞれ所定パターンをなす金属配線7を有する第1導体層M2,M12がCuメッキにより形成されている。なお、コア導体層M1,M11と第1導体層M2,M12とは、それぞれビア34により層間接続がなされている。ビア34は、第1樹脂絶縁層V1に形成されたビアホール(図3参照)にCuメッキが充填され、その形成されたビア導体によってコア導体層M1,M11と第1導体層M2,M12とが接続されている。また、ビア34は、図1に示すように、蓋状導体21と接続されスルホール12上に位置して形成されている。   In addition, on the upper layers of the core conductor layers M1 and M11, wiring laminated portions L1 and L2 including the core conductor layers M1 and M11 are formed. Specifically, first resin insulation layers (build-up resin insulation layers) V1 and V11 made of a photosensitive or thermosetting resin composition 6 are formed. Further, first conductor layers M2 and M12 having metal wirings 7 each having a predetermined pattern are formed on the surface by Cu plating. The core conductor layers M1 and M11 and the first conductor layers M2 and M12 are interconnected by vias 34, respectively. The via 34 is filled with Cu plating in a via hole (see FIG. 3) formed in the first resin insulation layer V1, and the core conductor layers M1, M11 and the first conductor layers M2, M12 are formed by the formed via conductor. It is connected. As shown in FIG. 1, the via 34 is connected to the lid-like conductor 21 and is formed on the through hole 12.

同様に、第1導体層M2,M12の上層には、感光性または熱硬化樹脂組成物6を用いた第2樹脂絶縁層(ビルドアップ樹脂絶縁層)V2,V12がそれぞれ形成されている。その表面には、金属端子パッド10,17を有する第2導体層M3,M13が形成されている。これら第1導体層M2,M12と第2導体層M3,M13とは、それぞれビア34により層間接続がなされている。このビア34は、第2樹脂絶縁層V2に形成されたビアホール(図3参照)にCuメッキが充填され、その形成されたビア導体によってコア導体層M2,M12と第2導体層M3,M13とが接続されている。また、ビア34は、図1に示すように、第1樹脂絶縁層に形成されたビア34(蓋状導体21と接続されスルホール12上に位置して形成されている)と接続され、且つ、そのビア34と板厚方向に連なるように位置して形成されている。これにより、蓋状導体21に接続されスルーホール12上に位置するスタックドビアが形成されている。   Similarly, second resin insulation layers (build-up resin insulation layers) V2 and V12 using the photosensitive or thermosetting resin composition 6 are formed on the first conductor layers M2 and M12, respectively. On the surface, second conductor layers M3 and M13 having metal terminal pads 10 and 17 are formed. The first conductor layers M2, M12 and the second conductor layers M3, M13 are connected to each other through vias 34. In the via 34, a Cu hole is filled in a via hole (see FIG. 3) formed in the second resin insulating layer V2, and the core conductor layers M2, M12 and the second conductor layers M3, M13 are formed by the formed via conductor. Is connected. Further, as shown in FIG. 1, the via 34 is connected to a via 34 (formed on the through hole 12 connected to the lid-like conductor 21) formed in the first resin insulating layer, and The via 34 is formed so as to be continuous with the plate thickness direction. Thereby, a stacked via connected to the lid-like conductor 21 and positioned on the through hole 12 is formed.

板状コア2の表面MP1においては、コア導体層M1、第1樹脂絶縁層V1、第1導体層M2及び第2樹脂絶縁層V2が積層され第1の配線積層部L1が形成されている。また、板状コア2の表面MP2においては、コア導体層M11、第1樹脂絶縁層V11、第1導体層M12及び第2樹脂絶縁層V12が積層され第2の配線積層部L2が形成されている。配線積層部L1,L2は、いずれも樹脂絶縁層と導体層とが交互に積層されたものであり、板状コア2から遠い側の主表面CPには、金属端子パッド10,17がそれぞれ形成されている。   On the surface MP1 of the plate-like core 2, the core conductor layer M1, the first resin insulation layer V1, the first conductor layer M2, and the second resin insulation layer V2 are laminated to form the first wiring laminated portion L1. On the surface MP2 of the plate-like core 2, the core conductor layer M11, the first resin insulation layer V11, the first conductor layer M12, and the second resin insulation layer V12 are laminated to form the second wiring laminated portion L2. Yes. Each of the wiring laminated portions L1 and L2 is formed by alternately laminating resin insulating layers and conductive layers, and metal terminal pads 10 and 17 are formed on the main surface CP on the side far from the plate-like core 2, respectively. Has been.

次に、その板状コア2から遠い側の主表面CP上には、金属端子パッド10,17が内部に露出するように開口部8a,18aを有するソルダーレジスト層SR1,SR2が形成されている。具体的には、ソルダーレジスト層SR1,SR2は、第2樹脂絶縁層V2,V12及び第3導体層M3,M13上に感光性または熱硬化性樹脂組成物8,18を用いて形成されている。また、開口部8a,18aは、ソルダーレジスト層SR1,SR2を感光性樹脂を用いる場合には、所定パターンにマスクされて紫外線で露光、現像することにより形成される。また、熱硬化性樹脂を用いる場合には、レーザまたはプラズマによって穿孔し形成される。以上のように、配線基板1は形成されている。   Next, solder resist layers SR1 and SR2 having openings 8a and 18a are formed on the main surface CP far from the plate-like core 2 so that the metal terminal pads 10 and 17 are exposed inside. . Specifically, the solder resist layers SR1 and SR2 are formed on the second resin insulation layers V2 and V12 and the third conductor layers M3 and M13 using the photosensitive or thermosetting resin compositions 8 and 18, respectively. . Further, when the solder resist layers SR1 and SR2 are made of a photosensitive resin, the openings 8a and 18a are formed by exposing and developing with ultraviolet rays while being masked in a predetermined pattern. When a thermosetting resin is used, it is formed by drilling with a laser or plasma. As described above, the wiring board 1 is formed.

なお、第1配線積層部L1側の金属端子パッド10は、集積回路チップなどをフリップチップ接続するためのパッドである半田パッドを構成し、半田バンプ11を備える。また、第2配線積層部L2側の金属端子パッド17は、配線基板自身をマザーボード等にピングリッドアレイ(PGA)あるいはボールグリッドアレイ(BGA)等により接続するための裏面パッドとして利用されるものである。また、配線基板1において信号伝送経路は、板状コア2の一主表面側(第1配線積層部L1側)に形成された金属端子パッド10から、他方の主表面側(第2配線積層部L2側)に形成された金属端子パッド17に至る形で形成される。   The metal terminal pad 10 on the first wiring laminated portion L1 side constitutes a solder pad that is a pad for flip-chip connection of an integrated circuit chip or the like, and includes a solder bump 11. The metal terminal pad 17 on the second wiring laminated portion L2 side is used as a back surface pad for connecting the wiring board itself to a mother board or the like by a pin grid array (PGA) or a ball grid array (BGA). is there. Further, in the wiring board 1, the signal transmission path extends from the metal terminal pad 10 formed on one main surface side (first wiring laminated portion L 1 side) of the plate-like core 2 to the other main surface side (second wiring laminated portion). L2 side) is formed so as to reach the metal terminal pad 17 formed on the L2 side.

次に、図2及び3を参照しながら本発明の配線基板1の製造方法について説明する。まず、耐熱性樹脂板(例えば、ビスマレイミド−トリアジン樹脂板)または繊維強化樹脂板(例えばガラス繊維強化エポキシ樹脂)などで形成される板状コア2に、ドリル等の方法でスルーホール12を穿孔する(工程1参照)。次に、そのスルーホールの内周面と板状コア2の両表面MP1,MP2上に無電解メッキを施し、その上に電解メッキを行い導体層を形成する。   Next, a method for manufacturing the wiring board 1 of the present invention will be described with reference to FIGS. First, a through-hole 12 is drilled in a plate-like core 2 formed of a heat-resistant resin plate (for example, bismaleimide-triazine resin plate) or a fiber reinforced resin plate (for example, glass fiber reinforced epoxy resin) by a method such as a drill. (See step 1). Next, electroless plating is performed on the inner peripheral surface of the through hole and both surfaces MP1 and MP2 of the plate-like core 2, and electrolytic plating is performed thereon to form a conductor layer.

次に、スルーホール導体30内に、平均粒径2〜5μmであるシリカフィラーなどの無機フィラーを含むエポキシ樹脂等の樹脂製穴埋め材(充填材)31を印刷充填し、これを加熱して半硬化させる。その後、板状コア2の両主表面MP1,MP2から膨出した余分な樹脂を研磨除去する(工程2参照)。そして、スルーホール導体30内に充填された充填材31の端面31aをメッキの密着性を向上させるために、過マンガン酸カリウム溶液等の粗化液で粗化処理する。このとき充填材の端面31aのJIS−B−0601に規定する十点平均粗さRzを充填材31に含まれるシリカフィラーの平均粒径の半分以下とすると、後に端面31aに密着性に優れたCuメッキを施すことができる。さらに、半硬化の樹脂材(充填材)を加熱硬化させて、スルーホール充填材31を形成する。(工程3参照)。   Next, a resin hole filling material (filler) 31 such as an epoxy resin containing an inorganic filler such as silica filler having an average particle diameter of 2 to 5 μm is printed and filled in the through-hole conductor 30, and this is heated and half-heated. Harden. Thereafter, excess resin swelled from both main surfaces MP1 and MP2 of the plate-like core 2 is removed by polishing (see step 2). Then, the end surface 31a of the filler 31 filled in the through-hole conductor 30 is roughened with a roughening solution such as a potassium permanganate solution in order to improve the adhesion of the plating. At this time, when the ten-point average roughness Rz defined in JIS-B-0601 of the end face 31a of the filler is set to be not more than half of the average particle diameter of the silica filler contained in the filler 31, the adhesiveness to the end face 31a is excellent. Cu plating can be applied. Further, the through-hole filler 31 is formed by heat-curing a semi-cured resin material (filler). (See step 3).

ここで、充填材の端面31aを粗化液を用いて粗化処理する場合に、あらかじめ樹脂材(充填材)を有機溶媒を含む液で膨潤させ、水洗いした後過マンガン酸カリウム溶液等の粗化液に浸漬して粗化処理を行う。この場合に、膨潤処理および粗化処理を行う温度,処理時間によって充填材の端面31aの表面粗さを調整することができる。   Here, when the end surface 31a of the filler is roughened using a roughening liquid, the resin material (filler) is swollen in advance with a liquid containing an organic solvent, washed with water, and then roughened with a potassium permanganate solution or the like. Roughening treatment is performed by dipping in a liquefying solution. In this case, the surface roughness of the end surface 31a of the filler can be adjusted by the temperature and processing time for performing the swelling treatment and the roughening treatment.

次に、板状コア2の両表面上、即ち、上記コア導体層M1,M11及び充填材の端面31aの上に、さらにCuメッキ層(導体層)を形成する。具体的には、無電解メッキを施し、その上に電解メッキをする。そして、上記コア導体層上に所定パターンのエッチングレジスト層を形成し、このレジスト層から露出する導体層をエッチング除去することにより、板状コア2の両表面MP1,MP2上に所定パターンのコア導体層M1,M11が形成され、また、充填材の端面31a及びスルーホール導体30の端部上には、平面視略円盤状の蓋状導体21が形成される(工程4参照)。   Next, a Cu plating layer (conductor layer) is further formed on both surfaces of the plate-like core 2, that is, on the core conductor layers M1 and M11 and the end face 31a of the filler. Specifically, electroless plating is performed and electrolytic plating is performed thereon. Then, an etching resist layer having a predetermined pattern is formed on the core conductor layer, and the conductor layer exposed from the resist layer is removed by etching, whereby a core conductor having a predetermined pattern is formed on both surfaces MP1 and MP2 of the plate core 2. Layers M1 and M11 are formed, and a lid-like conductor 21 having a substantially disk shape in plan view is formed on the end face 31a of the filler and the end of the through-hole conductor 30 (see step 4).

次に、コア導体層M1,M11および蓋状導体21上に、感光性または熱硬化性樹脂組成物6等からなる樹脂絶縁層V1,V11を形成する。その後、例えば樹脂絶縁層V1,V11の所定の位置(ここでは、蓋状導体上に位置する)をレーザまたはプラズマにより穿孔(熱硬化性樹脂を用いた場合)して、樹脂絶縁層V1,V11を貫通し、底面に蓋状導体21などのコア導体層M1,M11が露出するビアホール34hを形成する。または、所定パターンにマスクされて紫外線で露光,現像(感光性樹脂を用いた場合)することにより底面に蓋状導体21などのコア導体層M1,M11が露出するビアホール34hを形成する(工程5参照)。   Next, resin insulation layers V1 and V11 made of a photosensitive or thermosetting resin composition 6 or the like are formed on the core conductor layers M1 and M11 and the lid-like conductor 21. After that, for example, predetermined positions of the resin insulating layers V1 and V11 (here, located on the lid-like conductor) are perforated with a laser or plasma (when a thermosetting resin is used) to form the resin insulating layers V1 and V11. A via hole 34h is formed on the bottom surface through which the core conductor layers M1 and M11 such as the lid-like conductor 21 are exposed. Alternatively, a via hole 34h that exposes the core conductor layers M1 and M11 such as the lid-like conductor 21 is formed on the bottom surface by being masked in a predetermined pattern and exposed and developed with ultraviolet rays (when a photosensitive resin is used) (step 5). reference).

次に、上述した工程と同様にして、樹脂絶縁層V1,V11上にCuメッキ層(導体層)を形成すると共に、ビアホール34h内をCuメッキで充填して、フィルドビアであるビア34を形成する。具体的には、無電解メッキを施し、その上に電解メッキをする。その後、メッキ層上に所定パターンのエッチングレジスト層を形成し、このレジスト層から露出するメッキ層をエッチング除去することにより、ビア34を含む第1導体層M2,M12を形成する(工程6参照)。この工程により、コア導体層M1と導体層M2とが複数のビア34で接続される。これを繰り返すことにより、絶縁層V2,V12や第二導体層M3,M13、及びソルダーレジスト層SR1,SR11を積層していくことができ、配線積層部L1,L2を形成することができる(工程7参照)。   Next, in the same manner as described above, a Cu plating layer (conductor layer) is formed on the resin insulating layers V1 and V11, and the via hole 34h is filled with Cu plating to form a via 34 that is a filled via. . Specifically, electroless plating is performed and electrolytic plating is performed thereon. Thereafter, an etching resist layer having a predetermined pattern is formed on the plating layer, and the plating layer exposed from the resist layer is removed by etching to form the first conductor layers M2 and M12 including the via 34 (see step 6). . By this step, the core conductor layer M1 and the conductor layer M2 are connected by the plurality of vias 34. By repeating this, the insulating layers V2, V12, the second conductor layers M3, M13, and the solder resist layers SR1, SR11 can be stacked, and the wiring stacked portions L1, L2 can be formed (steps). 7).

また、図3(工程7)に示すように、第2樹脂絶縁層V2,V12にビア34を形成する場合に、第1樹脂絶縁層V1,V11に形成するビア34と接続する位置(板厚方向に連なる位置)にパターン形成することで、蓋状導体21上にスタックドビアを形成することができる。   Further, as shown in FIG. 3 (step 7), when the via 34 is formed in the second resin insulating layers V2 and V12, the position (plate thickness) connected to the via 34 formed in the first resin insulating layers V1 and V11. A stacked via can be formed on the lid-like conductor 21 by forming a pattern at a position continuous in the direction).

以下、本発明の効果を確認するために次の実験を行った。試用した試験品は以下の通りである。
まず、厚さ0.8mmの板状コア(松下電工製:松下R−1515T)に、直径300μmのスルーホールを穿孔し、前述した工程で平均粒径5μmに調整されたシリカフィラーを含むエポキシ樹脂をスルーホール導体内に充填する。これを20サンプル作製する。
Hereinafter, the following experiment was performed in order to confirm the effect of the present invention. The test samples used are as follows.
First, an epoxy resin containing a silica filler in which a through hole having a diameter of 300 μm is drilled in a plate-shaped core (Matsushita Electric Works: Matsushita R-1515T) having a thickness of 0.8 mm and adjusted to an average particle diameter of 5 μm in the above-described process. Is filled in the through-hole conductor. 20 samples are prepared.

次に、スルーホールに充填した充填材を以下の3サンプルずつ4条件で粗化処理を行い評価した。実施例1は、約70℃×約5分間の膨潤処理を行った後、過マンガン酸カリウムで約70℃×約6分間の粗化処理を行ったものである。実施例2は、約70℃×約10分間の膨潤処理を行った後、過マンガン酸カリウムで約70℃×約14分間の粗化処理を行ったものである。実施例3は、約70℃×約14分間の膨潤処理を行った後、過マンガン酸カリウムで約70℃×約14分間の粗化処理を行ったものである。比較例1は、約70℃×約15分間の膨潤処理を行った後、過マンガン酸カリウムで約70℃×約21分間の粗化処理を行ったものである。この粗化処理後にJIS−B−0601に規定する十点平均粗さ(Rz)を測定した。   Next, the filling material filled in the through holes was evaluated by roughening treatment under the following three samples in four conditions. In Example 1, a swelling treatment at about 70 ° C. for about 5 minutes was performed, followed by a roughening treatment at about 70 ° C. for about 6 minutes with potassium permanganate. In Example 2, a swelling treatment at about 70 ° C. for about 10 minutes was performed, followed by a roughening treatment at about 70 ° C. for about 14 minutes with potassium permanganate. In Example 3, a swelling treatment at about 70 ° C. for about 14 minutes was performed, followed by a roughening treatment at about 70 ° C. for about 14 minutes with potassium permanganate. In Comparative Example 1, after a swelling treatment at about 70 ° C. for about 15 minutes, a roughening treatment at about 70 ° C. for about 21 minutes was performed with potassium permanganate. After this roughening treatment, the ten-point average roughness (Rz) defined in JIS-B-0601 was measured.

次に、粗化処理を施した充填材の端面に無電解メッキ及び電解メッキにより厚さ25(誤差±0〜5μm)μmのCuメッキである蓋状導体を形成した。
続いて、この蓋状導体(メッキ部分)を幅10mmに切り出し、基板上に対して蓋状導体を垂直方向に引っ張り測定し、これをピール強度(密着強度)とした。この試験の結果である十点平均粗さRz(μm)、ピール強度(kgf/cm2)を表1に示す。また、表1に実施例1ないし3及び比較例1のピール強度(kgf/cm2)の平均値を示した。なお、ピール強度はCuメッキの厚さを25μmとした場合の換算値を示す。図4は、表1に対応する図であり、実施例1ないし3及び比較例1におけるピール強度(kgf/cm2)が示されている。
Next, a lid-like conductor made of Cu plating having a thickness of 25 (error ± 0 to 5 μm) μm was formed by electroless plating and electrolytic plating on the end surface of the roughened filler.
Subsequently, the lid-like conductor (plated portion) was cut out to a width of 10 mm, and the lid-like conductor was pulled in the vertical direction with respect to the substrate, and this was measured as peel strength (adhesion strength). Table 1 shows the ten-point average roughness Rz (μm) and peel strength (kgf / cm 2), which are the results of this test. Table 1 shows the average peel strength (kgf / cm 2) of Examples 1 to 3 and Comparative Example 1. Note that the peel strength indicates a conversion value when the thickness of the Cu plating is 25 μm. FIG. 4 is a diagram corresponding to Table 1, and shows the peel strength (kgf / cm 2) in Examples 1 to 3 and Comparative Example 1.

Figure 2007150111
Figure 2007150111

次に、実施例の結果として、十点平均粗さ(Rz)がシリカフィラーの平均粒径の約半分具体的には約2.5μm(実施例3)のとき、比較例1(十点平均粗さ(Rz)が2.8〜3.0μm)と比べてピール強度(密着強度)は良好であった。また、表1の結果からも分かるように、十点平均粗さ(Rz)がシリカフィラーの平均粒径の半分以下(実施例1〜3)の場合は、Rzが高いほどピール強度が高くなる傾向があった。一方、十点平均粗さ(Rz)がシリカフィラーの平均粒径の半分以上となると、明らかにピール強度が低くなる傾向があった。つまり、十点平均粗さ(Rz)がシリカフィラーの平均粒径の半分より大きいと、シリカフィラーの脱落により十分なピール強度を得ることができなかった。
また、2.0μm以上2.5μm以下(2X/5≦Rz≦X/2)のときピール強度(密着強度)は特に良好であった。十点平均粗さ(Rz)が1.6μmより下回ると、シリカフィラーの脱落は見られなかったが、粗度が十分に得られないため、十分なピール強度を得ることができなかった。
Next, as a result of the example, when the ten-point average roughness (Rz) is about half of the average particle diameter of the silica filler, specifically about 2.5 μm (Example 3), Comparative Example 1 (10-point average) The peel strength (adhesion strength) was better than the roughness (Rz) of 2.8 to 3.0 μm. Moreover, as can be seen from the results in Table 1, when the ten-point average roughness (Rz) is less than or equal to half of the average particle diameter of the silica filler (Examples 1 to 3), the peel strength increases as Rz increases. There was a trend. On the other hand, when the ten-point average roughness (Rz) is more than half of the average particle diameter of the silica filler, the peel strength clearly tends to be lowered. That is, when the ten-point average roughness (Rz) is larger than half of the average particle diameter of the silica filler, sufficient peel strength cannot be obtained due to the dropping of the silica filler.
The peel strength (adhesion strength) was particularly good when the thickness was 2.0 μm or more and 2.5 μm or less (2X / 5 ≦ Rz ≦ X / 2). When the ten-point average roughness (Rz) was less than 1.6 μm, the silica filler did not fall off, but the roughness could not be sufficiently obtained, so that sufficient peel strength could not be obtained.

なお、本発明において、上記実施例に限定されるものではなく、目的、用途に応じて本発明の範囲内で種々変更した実施例とすることもできる。   In addition, in this invention, it is not limited to the said Example, It can also be set as the Example variously changed within the range of this invention according to the objective and the use.

本発明に係る配線基板の断面構造の一例を示す図。The figure which shows an example of the cross-section of the wiring board which concerns on this invention. 本発明に係る配線基板の製造工程説明図Manufacturing process explanatory diagram of a wiring board according to the present invention 図2に続く配線基板の製造工程説明図Wiring board manufacturing process explanatory diagram following FIG. 表1に対応する図Figure corresponding to Table 1 配線基板の不具合を説明する図Diagram explaining defects in wiring board

符号の説明Explanation of symbols

1 配線基板(樹脂製配線基板)
2 板状コア(コア部)
12 スルーホール
21 蓋状導体
30 スルーホール導体
31 充填材
31a 端面
34 ビア導体
50 空隙部
1 Wiring board (resin wiring board)
2 Plate core (core part)
12 through-hole 21 lid-shaped conductor 30 through-hole conductor 31 filler 31a end face 34 via conductor 50 gap

Claims (5)

板厚方向に貫通するスルーホール内に筒状のスルーホール導体及びその内側を充填する充填材が形成されたコア部を備える配線基板であって、
前記充填材は無機フィラーを含む樹脂材料で構成され、該無機フィラーの平均粒径をX(μm)としたとき、当該充填材の端面におけるJIS−B−0601に規定する十点平均粗さ(Rz)がRz≦X/2を満たし、当該充填材の端面が前記スルーホール導体と接続された蓋状導体に覆われてなることを特徴とする配線基板。
A wiring board including a core part in which a cylindrical through-hole conductor and a filler filling the inside thereof are formed in a through-hole penetrating in the plate thickness direction,
The filler is composed of a resin material containing an inorganic filler. When the average particle diameter of the inorganic filler is X (μm), the ten-point average roughness defined in JIS-B-0601 on the end face of the filler ( Rz) satisfies Rz ≦ X / 2, and the end face of the filler is covered with a lid-like conductor connected to the through-hole conductor.
前記充填材の端面の十点平均粗さ(Rz)がX/3≦Rzである請求項1に記載の配線基板。   The wiring board according to claim 1, wherein a ten-point average roughness (Rz) of an end face of the filler is X / 3 ≦ Rz. 前記コア部の主面上に形成された樹脂絶縁層と、当該樹脂絶縁層に埋設され前記蓋状導体と接続されたビア導体とを備え、当該ビア導体が前記スルーホール上に位置する請求項1または2に記載の配線基板。   A resin insulating layer formed on a main surface of the core portion, and a via conductor embedded in the resin insulating layer and connected to the lid-shaped conductor, wherein the via conductor is located on the through hole. The wiring board according to 1 or 2. 前記ビア導体が前記スルーホール上の中央領域に位置する請求項3に記載の配線基板。   The wiring board according to claim 3, wherein the via conductor is located in a central region on the through hole. 前記コア部の主面上に2層以上の樹脂絶縁層が導体層を介して形成され前記ビア導体が板厚方向に連なってスタックドビアを構成するとともに、当該スタックドビアが前記蓋状導体上に位置する請求項3または4に記載の配線基板。   Two or more resin insulation layers are formed on the main surface of the core portion via a conductor layer, the via conductors are connected in the plate thickness direction to form a stacked via, and the stacked via is positioned on the lid-like conductor. The wiring board according to claim 3 or 4.
JP2005344627A 2005-11-29 2005-11-29 Wiring board Pending JP2007150111A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012078335A2 (en) * 2010-12-09 2012-06-14 Intel Corporation Hybrid-core through holes and vias
KR101412225B1 (en) 2012-08-10 2014-06-25 이비덴 가부시키가이샤 Wiring board and method for manufacturing wiring board
JP2014120736A (en) * 2012-12-19 2014-06-30 Shindengen Electric Mfg Co Ltd Multilayer substrate, and design method of multilayer substrate

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012078335A2 (en) * 2010-12-09 2012-06-14 Intel Corporation Hybrid-core through holes and vias
WO2012078335A3 (en) * 2010-12-09 2012-08-16 Intel Corporation Hybrid-core through holes and vias
US8552564B2 (en) 2010-12-09 2013-10-08 Intel Corporation Hybrid-core through holes and vias
CN103404245A (en) * 2010-12-09 2013-11-20 英特尔公司 Hybrid-core through holes and vias
US8928151B2 (en) 2010-12-09 2015-01-06 Intel Corporation Hybrid core through holes and vias
KR101525002B1 (en) * 2010-12-09 2015-06-09 인텔 코포레이션 Hybrid-core through holes and vias
TWI595622B (en) * 2010-12-09 2017-08-11 英特爾公司 Hybrid-core through holes and vias
US9820390B2 (en) 2010-12-09 2017-11-14 Intel Corporation Process for forming a semiconductor device substrate
KR101412225B1 (en) 2012-08-10 2014-06-25 이비덴 가부시키가이샤 Wiring board and method for manufacturing wiring board
JP2014120736A (en) * 2012-12-19 2014-06-30 Shindengen Electric Mfg Co Ltd Multilayer substrate, and design method of multilayer substrate

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