TWI228022B - Printed circuit board and manufacturing method thereof - Google Patents

Abstract

To prevent occurrence of electrical connection failure between conductor layers that is caused by a difference in thermal expansion between an insulating layer and the conductor layer in a via hole of a printed circuit board. In a printed circuit board of the present invention, an area of a joining surface 18 between a first conductor 12 and a second conductor 15 at a bottom portion of a via is increased, and further, the second conductor 15 has a fringe (flange) region 21 joining a surface 20 of a second insulating layer 14 at an outer peripheral portion around an opening of the second insulating layer 14 at the bottom portion of the via. Therefore, the printed circuit board is stable against a tensile stress generated due to a difference in thermal expansion between the insulating layer and the conductor layer, and hence, failure in electrical connection between the conductor in the via does not occur.

Description

1228022 V. Description of the invention (1) [Technical Field] The present invention relates generally to a printed circuit board and a method for manufacturing the same, and more particularly to a multilayer (muiUpiayer) printed circuit board having a via hole, and the via hole serves as a conductor. Electrical connection between layers, and conductor layers are inserted and separated with an insulating layer. Furthermore, the manufacturing method is further described. [Prior art] Sectional view of the interposer—one is ί also 11a 1 and) ’’ is provided as an insulator made of resin or the like and used as the bottom layer! on. The conductor layer 2 is covered by an insulator 4 formed of a resin or the like except for one of the openings 3 of a via. In the intermediary window, the opening 3 is formed by drilling a hole in the insulating layer 4 by a wet die or laser beam, and extends to the inside of the opening 3 of the layer 2 / intermediate window by the conductive layer 5 by electroplating or the like. The body layer 5 is connected to the conductor layer 2 and the conductor layer on the insulation layer 4 (the connection between the upper layer and the lower conductor layer of the insulator 4 is not shown in FIG. 5). The multilayer printed circuit board is manufactured by a conductor according to a technology such as Built-in P technology (bui Id-up technique), the interstitial hole is used as an electrical connector between conductor layers, and the conductor layers are inserted and separated by an insulating layer. Figure 1 shows a common ^ ^ ® Figure 1, patterning The conductor layer 2 of the printed circuit is usually called a printed circuit. The difference in μ coefficient causes the temperature of the thinker to change. The thermal expansion of the V-body layer and the insulation layer produces a tensile stress in the cavity. The tensile stress is shown in Figure 1. Zhi Shuo b. In particular, in Figure 丨, this force along the connection

4IBM0391TW.ptd Page 7 1228022 V. Description of the invention (2) The direction in which the ground conductor layer 2 and the intermediary window conductor layer 5 are separated. Therefore, the conductor layer 2 and the conductor layer 5 are separated on the connection surface 7 and cause the conductor layer 2 and Electrical insulation between the conductor layers 5 occurs. This phenomenon is especially noticeable when the diameter of the via hole becomes smaller. This is because the opening at the bottom of the via hole becomes smaller, so that the surface of the ground conductor 2 exposed to the opening is reduced, so the area of the connecting surface 7 between the conductor layer 2 and the conductor layer 5 is also reduced. Moreover, this phenomenon is particularly prominent in environments with large temperature changes, thereby reducing the reliability of printed circuit boards. Printed circuit board technology related to adding a conductor connection in a via hole to resist separation has been disclosed, such as JP-A-200 1-24329. However, this disclosed technique does not teach a technique for avoiding electrical insulation caused by the separation of the conductor layer 2 and the conductor layer 5 in FIG. 1. JP-A-H0 5-6 78 82 discloses a technique for avoiding the electrical insulation of the conductor layer 2 and the conductor layer 5. This technology uses a laser beam to increase the diameter of the bottom of the intermediate window or the depth of the intermediate window to make the conductive layer 2 and the conductor The connection area of layer 5 increases. Therefore, the disclosed technology cannot solve the problem that the diameter and depth of the interposer cannot be increased due to the design. In other words, for the needs of today and tomorrow's printed circuit boards, this disclosed technology is not effective in detailing minute vias (eg diameter: tens of microns or less). [Content] One aspect of the present invention is to prevent the lack of electrical contact (insulation) between conductors due to the difference in thermal expansion between the insulation layer and the conductor layer in the via hole of the printed circuit board.

4IBM0391TW.ptd Page 8 1228022 V. Description of the invention (3) On the other hand, the present invention improves the reliability of the printed circuit board against temperature changes. The invention provides a printed circuit board with a via hole, which includes a first conductor layer formed on a first insulating layer; a second insulating layer is formed on the first insulating layer and the first conductor layer; a hole Formed in the second insulating layer on the first conductor layer and extending to the first conductor layer; and a second conductor layer covering at least one of the inner peripheral surface and the surface of the hole, and one of the first insulating layer The surface is opened around one of the holes and contacts the first conductor layer, wherein the first conductor layer and the second conductor layer are connected at a joining surface, the connecting surface is located at the bottom of one of the holes and is between the first conductor And below a conductive surface between the second insulators. A diameter of one of the connecting surfaces is larger than an opening diameter of a second insulator at the bottom of the hole. In the printed circuit board of the present invention, the connection area between the first conductor and the second conductor is located at the bottom of the interposer, and the second conductor has a fringe region and is insulated from the second The surface of the layer is connected to a peripheral portion of the opening of the insulation layer from the bottom to the bottom. Therefore, the printed circuit board is stable in tensile stress caused by different thermal expansion between the insulating layer and the conductor layer, and therefore, the lack of electrical contact between the conductor layers in the intermediary window does not occur.

Page 1228022 5. Description of the invention (4) According to the present invention, a method for manufacturing a printed circuit board is provided, which includes the following steps: (a) preparing a first insulating layer; (b) providing a first conductor layer on the first On the insulating layer; (c) providing a second insulating layer on the first insulating layer and the first conductor layer; (d) providing a hole in the second insulating layer on the first conductor layer, and the hole extends to the first conductor (E) providing an opening portion facing the hole in the first conductor layer, the diameter of the opening portion is larger than the opening diameter of a hole in a bottom portion; and (f) forming a second conductor layer to fill the opening portion and cover at least An inner peripheral surface of a hole and a surface of the second insulation layer are opened around one of the holes α ° According to the manufacturing method of the printed circuit board of the present invention, at the bottom of the intermediate window and between the connection areas of the first conductor and the second conductor Moreover, the second conductor has an edge region which is connected to a peripheral portion of the surface of the second insulating layer at the bottom of one of the intermediary windows surrounding an opening of the second insulating layer. Therefore, the printed circuit board is stable in tensile stress caused by different thermal expansion between the insulating layer and the conductor layer, so the lack of electrical contact between the conductor layers does not occur. 【method of execution】

4IBM0391TW.ptd Page 10 1228022 V. Description of the invention (5) --- The following is a detailed description of the present invention. The features of the present invention relate to the via hole of the printed circuit board. Since other parts of the printed circuit board can be manufactured by conventional techniques, the description order is omitted. It is known that the via hole of the present invention is compatible with all printed circuits including a multiplayer build-up board. 2 is a cross-sectional view of a via hole of a printed circuit board according to a preferred embodiment of the present invention. A conductive layer 丨 2 as a ground is formed on an insulating layer 丨 丨. An insulating layer 14 is formed on the insulating layer including the conductor layer 12, and the insulating layer is formed on the conductor layer 12 having a hole 13. A conductor layer 15 covers an inner peripheral surface 16 of the hole, and One surface 17 of the insulating layer n surrounds the opening of the hole 13 on the top of the insulating layer 14 and is connected to the conductive layer 丨 2 at the connecting surface 丨 8. The connecting surface 18 is located below the plane 19, and the plane 19 includes the conductive layer 12 and insulation The contact surface of layer 14 is located at the bottom of one of the holes 丨 3. The diameter L of the connection surface j 8 is set to be larger than the opening diameter L1 of the insulating layer 丨 4 at the bottom of the hole 丨 3 in a peripheral area. (Outer peripheral portion) surrounds the opening of the insulating layer 14 at the bottom of the hole 13, and the conductive layer 15 has a fringe (flange) region 21 connected to one surface 20 of the insulating layer n. The conductive layer A part 22 of 15 is located below a flat surface 19 having a shape like a nail or a screw head. This conductive part 22 makes the area of the connecting surface 18 of the conductive layer 12 larger than the area of the general connecting surface 7 in FIG. 1. , Because the conductor portion 22 has a shape like a screw head (with an edge region Domain 2 1), mesotheli cave warrior formation warrior

1228022

Their effect counteracts the tension in the direction of arrow 23 caused by the different thermal expansion coefficients between the insulating layer and the conductor layer. The dotted line 24 in FIG. 2 is the maximum size that the conductor portion 22 can increase. In particular, the diameter of the conductor portion 22 (for example, the diameter of the connecting surface 8) can be increased up to the width L2 of the conductor layer 12. Furthermore, the thickness η of the conductor portion 22 can be increased to a thickness Η1 of the conductor layer 12. As the size of the conductor portion 22 increases, the area 18 of the connection surface also increases, and at the same time, the edge area 21 of the surface contacting the insulating layer 14 also increases. Therefore, the structure of the mesoporous hole is stronger to resist the tension generated from the direction 23 of the arrow. In this example, according to the area ratio between the conductor layer 2 and the connection surface 8 of the body portion 22, the structure of the via hole tends to be stronger to resist tension. 3 is a sectional view of a printed circuit board according to another preferred embodiment of the present invention. FIG. 3 shows a structure in which a hole 13 in FIG. 2 is filled with a conductive layer 15 and other structures are the same as those in FIG. 2. As shown in FIG. 2, the mesoporous structure of FIG. 3 is stronger due to the existence of the conductor portion 22 below the dotted line 19 to resist the tension generated from the direction 23 of the arrow. FIG. 4 is a flowchart of a method for manufacturing a printed circuit board according to the present invention. ® In step (a), a first insulating layer 11 is prepared. The first insulating layer 11 can be applied to the substrate or an insulating layer on the substrate. For example, the insulating layer is used in step (b), and a first conductor layer 12 is provided on the first insulating layer 11

1228022 5. In the description of the invention (7), the conductor layer 12 is patterned (etched) on the conductor layer of the first conductor layer 11 using lithography to obtain the first conductor layer 12. Alternatively, the patterned conductor layer 12 is obtained using a technique called a pattern plate technique. In step (c), a second conductor layer 14 is provided on an insulating layer 11 including a brother of the first conductor layer 12. The second insulating layer 14 can be obtained by, for example, coating a resin under pressure and curing it. In step (d), a hole 13 extending to the first conductive layer 12 is formed on the second insulating layer 14 on the first conductive layer 12. The holes 1 3 are obtained by lithography (remainder) or laser beam (removed). In step (e), an opening part 30 with a diameter L is formed on the first conductor layer 12 and faces the hole 13, where the diameter l is larger than the diameter L1 of an opening radius of the hole 13 at the bottom. The opening portion 30 is formed by wet-engraving the first conductor layer 12 with a solution such as an acid. The size (width L and thickness Η) of the opening portion 30 can be controlled by the concentration, time, or the like of the etching solution. What is important here is that the first conductor layer 12 of the worm is not only in the vertical direction, that is, the so-called non-isotropic residual moment, but also the horizontal money token, that is, the so-called 14 isotropic moment. In this step (e), one surface 20 of the second insulating layer 14 is exposed at a peripheral portion located at the bottom of the hole 13. After a conductive layer is formed by electroplating (p 1 ati ng) in a subsequent step, a rough step is performed in step (e) 以 to form fine and coarse chains on a surface of the second insulating layer 14 in the hole 13. on. This is to improve the adhesion between the plated metal and the second insulating layer. In step (f), a second conductor layer is filled into the opening portion 30 and covered.

4IBM0391TW.ptd Page 13 1228022 V. Description of the invention (8) '' Around the hole Body layer 15 Body layer 15 Conductor layer Insulation layer Second insulation conductor. Yu step through the interlayer. One of the openings 13 is, for example, electroplated by the lithography 15 and the electrical edge layer 14 above and below the second insulation 14. The outer layer 15 has a step (f), and the via structure can at least one of the holes 13 The inner periphery surface 6 and a surface 17 of the second insulating layer n on the top periphery 13. The second lead was formed. A second conductive (etching) technique is formed on the second insulating layer 4 to form a predetermined pattern. The second edge layer 14 contacts another conductor layer. Therefore, a second contact can be established by the second conductor layer 15. In the surrounding portion 'surrounding the opening at the bottom of the hole 13, the structure in which the second edge region 21 is connected to the 20 hole on the surface of the second insulating layer 14 can be obtained as shown in FIG. Incidentally, in FIG. 3, the second conductor layer 15 fills the hole 3 to the dotted line 32 to obtain the surface of the via hole of a part of the product obtained by the manufacturing method of the present invention. Figure 5 is based on a miniature of a real intermediary window section. The component symbols in FIG. 5 correspond to those in FIGS. 2 and 3. In Fig. 5, the diameter U3 of the opening U at the top L3_μm (㈣, and the diameter U of the opening layer 14 at the bottom of the center = about 38 microns. One width (diameter) L2 of the conductor layer ^ about 95 The thickness of the conductive layer 15 is about 5 microns, and the diameter L is about 57 microns. The conductive layers 12 and 15 are copper plating layers, and the insulating layer 1 4 series resin layer. The step of manufacturing the via hole in FIG. 5 uses the stencil technology, as shown below: U) By etching a ground conductor or stencil technology to form a circuit board containing the conductor layer 12.

1228022 5. Description of the invention (9) (b) The insulating layer 14 is under pressure, covered with an insulating layer and cured to obtain. (c) A hole is formed by a laser beam. In this case, an opening portion including an edge region has not been formed. (d) In order to increase the adhesion of the electroplated copper to the following steps, the surface of an insulating layer resin is roughened by overacid acid (061: 111 & 1 ^ 311 丨 (: & (: ([1). roughened. In this case, the edge region has not yet been formed. (E) Using a mixed solution containing an acid such as sulfuric acid, the bottom of the conductor layer 12 is engraved to form an opening portion. (F) Electroless copper plating is used on the entire surface of the insulation layer, Under this condition, electroless copper plating is also used in the opening portion of the conductor layer 12. 41 (g) A patterned photoresist is fixed on the board for easy exposure and development. (H) Electroless copper is formed in the previous step (f ) As a seed layer to perform copper bonding, thus forming a pattern. The pattern is formed according to the template technology and the semi-additive technique. In this case, copper plating is used in the previous step (e) The opening portion is filled with copper. In this method, the edge region (conductor portion 22) is formed at the bottom of the via hole. The present invention shown in FIG. 5 is a printed circuit board including an interposer window, which is robust. The results of the temperature cycle test are as follows For comparison, the panel containing the general intermediary window shown in Figure 1 is also tested at the same time. (A) Test conditions The following tests 1 and 2 are performed under the temperature cycle (cycle: 100,000 cycles). 1 · Test Condition 1 :

4IBM0391TW.ptd Page 15 1228022 V. Description of the invention (10) Cycle 2 cycles / hour and 1000 times at -55 to 125 degrees 2 Test condition 2: (b) Samples 10 cycles / hour and -55 to 2,000 undercycles at 125 ° 1 · Plate A contains the general intermediary window as shown in Figure 1 Test 1 is 39 boards (including 1 3040 intermediary window) Test 2 is 5 6 boards (1 7 3 3 6 0 intermediary window) 2 · plate β contains the intermediary window of the present invention as shown in FIG. 2 Test 1 is 20 boards (including 70 00 0 intermediary window) Test 2 is 41 boards (692 1 6 intermediary window)

(c) Test result 1 · General board A: Number of t 5 9 boards' includes 39 boards as temperature cycle, board as temperature cycle test 2, 11 boards have medium window lightning guidance, 11 tests 1 and 56 (12% chance of failure). Electrical failure (insulation) 2. The board B of the present invention: a total of 61 boards' contains 20 boards as temperature cycle boards as temperature cycle test 2. In particular, i 392 1 6 and 41 fail to conduct electricity (insulation) (Failure probability is 0%). There is no printed circuit board obtained according to the manufacturing method of the present invention in the dielectric window. Between the first conductor and the second conductor of the dielectric window = the conductor area increases, and further, the two conductors have an edge region, and the dielectric window The bottom portion surrounds the peripheral portion of the opening of the second insulating layer and is connected to the surface of the second insulating layer.

4IBM〇39lTW.ptd Page 16 1228022 V. Description of the invention (11) Therefore, the tensile stress caused by the printed circuit board due to different thermal expansion between the insulation layer and the conductor layer is stable, so the electrical contact between the conductor layers in the intermediary window is lacking will not happen. The printed circuit board of the present invention has high stability and reliability with respect to thermal tension. The present invention improves current and future printed circuit board requirements, especially fine via holes.

4IBM0391TW.ptd Page 17 1228022 Figure fal early explanation Figure 1 is a sectional view of a general via hole; Figure 2 is a sectional view of a via hole portion of a printed circuit board according to a preferred embodiment of the present invention; Figure 3 FIG. 4 is a cross-sectional view of a via hole portion of a printed circuit board according to another preferred embodiment of the present invention; FIG. 4 is a flowchart of manufacturing a printed circuit board according to the present invention; FIG. 5 is a part obtained by the manufacturing method of the present invention An enlarged cross-sectional view of the interstitial hole of the product. Symbols of the illustrated components 1, 4, 11, 1 4 Insulator 2, 5 M2 '15 3 Opening 6, 23 Arrow 7, 1 8 Connection surface 13 Hole 16 Inner surface 17, 2 0 Surface 19 Flat surface 21 Edge area 22 Conductor Part 30 open part 32 dotted line conductor layer

4IBM0391TW.ptd Page 18

Claims (1)

1228022 6. Scope of patent application 1. A printed circuit board with a via hole includes: a first conductor is formed on a first insulating layer; a second insulating layer is formed on the first An insulating layer and the first conductor; a hole (ho 1 e) formed in the second insulating layer on the first conductor and extending to the first conductor; and a second conductor covering at least one of the holes An inner surface (innersurf ace) and a surface of the second insulating layer opening around the hole and contacting the first conductor, wherein the first conductor and the second conductor system join in a connecting surface surf ace), and the connection surface is located at the bottom of one of the holes and below a contact surface of the first conductor and the second insulation layer, and one of the connection surfaces is larger in diameter than the hole An opening diameter of one of the second insulating layers at the bottom. 2. A printed circuit board having a via hole includes: a first conductor is formed on a first insulating layer; a second insulating layer is formed on the first insulating layer and the first conductor; a hole is formed on Inside the second insulating layer on the first conductor and extending to the first conductor; and a second conductor covering at least one inner surface of the hole, and one surface of the second insulating layer surrounding an opening of the hole And contacting the first conductor, wherein the second conductor has a fringe region surrounding a peripheral portion of an opening of the second insulating layer at a bottom of the hole 4IBM0391TW.ptd Page 19 1228022 6. The outer peripheral portion of the patent application is connected to one surface of the second insulation layer. 3. The printed circuit board according to item 1 of the scope of patent application, wherein a diameter of the connection surface between the first and second conductors is smaller than a width of the first conductor. 4. A printed circuit board with a via hole includes: a first conductor is formed on a first insulating layer; a second insulating layer is formed on the first insulating layer and the first conductor; a hole is formed on Inside the second insulation layer on the first conductor and extending to the first conductor; and a second conductor filling the hole and covering at least one surface of the second insulation layer surrounding an opening of the hole and contacting the first conductor A conductor, wherein the first conductor and the second conductor are connected at a connection surface, the connection surface is located at the bottom of one of the holes and is under the contact surface of the first conductor and the second insulation layer, and the connection A diameter of one of the faces is larger than an opening diameter of a second insulator at the bottom of the hole. 5. A method of forming a printed circuit board, comprising the following steps: (a) preparing a first insulating layer; (b) forming a first conductor layer on the first insulating layer; (c) forming a second An insulating layer on the first insulating layer and the first conductor layer 4IBM0391TW.ptd Page 20 1228022 6. Scope of the patent application (d) A hole is formed in the second insulating layer on the first conductor layer, and the hole extends to the first conductor layer; (e) Formed facing the An opening portion of the hole is on the first conductor layer, a diameter of the opening portion is greater than an opening diameter of the hole at a bottom portion; and (f) forming a second conductor layer to fill the opening portion and cover at least the hole An inner surface and a surface of the second insulating layer, the surface opening around one of the holes. 6. The method according to item 5 of the scope of patent application, wherein the second conductor layer, if®, enters the opening portion and has an edge region and a surface of the second insulation layer at the bottom of the hole, the second insulation. A peripheral portion of one of the openings of the layer is connected. 7. The method according to item 5 of the scope of patent application, wherein the step (e) of forming the opening portion includes a step of exposing a surface of the second insulating layer to the second insulating layer at the bottom of the hole One opening and one peripheral portion. 8. The method as described in item 5 of the scope of patent application, wherein the step (e) of forming the opening portion% comprises a step of wet first insect cutting (wet e t c h i n g) the first conductor layer. 4IBM0391TW.ptd Page 21