KR101558579B1 - Printed circuit board and method for fabricating the same - Google Patents

Abstract

The present invention relates to a printed circuit board and a manufacturing method thereof.

A method of manufacturing a printed circuit board according to an embodiment of the present invention includes: preparing an insulating member having a metal thin film layer; Forming a first plating layer on the metal thin film layer; Selectively removing the first plating layer and the metal thin film layer to form a first circuit pattern; And forming a second plating layer on the upper surface and side surfaces of the first plating layer and the side surfaces of the metal thin film layer forming the first circuit pattern.

Printed circuit board

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a printed circuit board (PCB)

The present invention relates to a printed circuit board and a manufacturing method thereof.

BACKGROUND ART [0002] Recently, as a circuit pattern of a printed circuit board has become finer, thinner, and smaller, various techniques for forming a circuit pattern on a printed circuit board have been studied.

In particular, a technique for obtaining a fine pattern with a high yield is required.

Conventionally, a circuit pattern is mainly formed depending on etching, but a method of forming a circuit pattern by etching has a limitation in obtaining a fine circuit pattern because distortion occurs in the circuit pattern.

A method of forming a circuit pattern by adding not only etching but also a plating process is used. However, this method has a problem in that the number of processes is large, there is a limit to forming a good fine pattern, and a manufacturing cost of a printed circuit board is increased.

An embodiment provides a printed circuit board of a new structure and a method of manufacturing the same.

The embodiments provide a printed circuit board which forms a fine circuit pattern simply and at low cost and a method of manufacturing the same.

The embodiment provides a printed circuit board capable of forming a fine circuit pattern with a high yield and a method of manufacturing the same.

A method of manufacturing a printed circuit board according to an embodiment of the present invention includes: preparing an insulating member having a metal thin film layer; Forming a first plating layer on the metal thin film layer; Selectively removing the first plating layer and the metal thin film layer to form a first circuit pattern; And forming a second plating layer on the upper surface and side surfaces of the first plating layer and the side surfaces of the metal thin film layer forming the first circuit pattern.

A printed circuit board according to an embodiment includes an insulating member; A second circuit pattern on the insulating member, the second circuit pattern including a metal thin film layer; A first plating layer formed on the metal thin film layer; And a second plating layer formed on an upper surface and a side surface of the first plating layer and a side surface of the metal thin layer.

The embodiments can provide a printed circuit board of a new structure and a method of manufacturing the same.

The embodiments can provide a printed circuit board which forms a circuit pattern simply and at a low cost, and a method of manufacturing the same.

The embodiment can provide a printed circuit board capable of forming a circuit pattern with a good yield and a high yield, and a manufacturing method thereof.

In describing an embodiment according to the present invention, it is to be understood that each layer (film), pattern or structure may be formed "on" or "under" a substrate, each layer Quot; on "and" under "include both what is meant to be" directly "or" indirectly " In addition, the criteria for above or below each layer will be described with reference to the drawings.

The thickness and size of each layer in the drawings are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. Also, the size of each component does not entirely reflect the actual size.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a printed circuit board according to embodiments and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

1st Example

1 to 6 are views for explaining a printed circuit board according to the first embodiment and a method of manufacturing the same.

Referring to FIG. 1, an insulating member 110 having metal foil layers 121 formed on both surfaces thereof is prepared. The insulating member 110 may include a resin material, for example, an epoxy resin or a phenol resin. Alternatively, the insulating member 110 may be an ABF resin or a polyimide film. The ABF resin or polyimide film is excellent in impact resistance and electrical insulation, so that a printed circuit board with improved reliability can be produced.

The metal thin film layer 121 is formed of at least one of metal, for example, copper (Cu), tin (Sn), and nickel (Ni).

A via hole 111 may be formed in the insulating member 110 to penetrate both surfaces of the insulating member 110. The via hole 111 may be formed when it is necessary to electrically connect the circuit patterns to be formed on both sides of the insulating member 110.

Referring to FIG. 2, a first plating layer 120 is formed by plating the metal thin film layer 121 and the via hole 111. Specifically, the first plating layer 120 may be formed by performing electroless plating to form a seed layer, followed by electroplating. The material of the first plating layer 120 may be at least one of metal, for example, copper (Cu), tin (Sn), and nickel (Ni).

The thickness of the first plating layer 120 and the thickness of the metal foil layer 121 may be 10 μm or less.

Referring to FIG. 3, a photoresist pattern 130 is formed on the first plating layer 120 including the via hole 111 and a portion adjacent to the via hole 111. The exposed surface 131 of the first plating layer 120 not covered by the photoresist pattern 130 is also formed. The photoresist pattern 130 may be formed of, for example, a dry film.

The photoresist pattern 130 may be formed using photolithography. Specifically, first, photoresist coating is performed on both sides of the insulating member 110 where the first plating layer 120 is formed, and then a photomask (not shown) is formed on the photoresist coating. Next, the photoresist pattern 130 can be formed by performing exposure after performing photoexposure using ultraviolet rays or the like and then developing. The detailed description will be omitted because it can be easily understood by those skilled in the art.

Referring to FIGS. 3 and 4, the first plating layer 120 and the metal thin film layer 121 are selectively etched using the photoresist pattern 130 as a mask to form a first circuit pattern 140. That is, the exposed surface 131 of the first plating layer 120 not covered by the photoresist pattern 130 is removed by etching to form the first circuit pattern 140. Also, the exposed surface 115 of the insulating member 110 is exposed by the etching.

4, the first circuit pattern 140 and the second circuit pattern 140 are formed on the first and second circuit patterns 140 and 140, respectively. In the process of etching the first and second metal layers 120 and 121, As shown in the figure, it may be formed by being distorted by an inclined surface or the like. This is because the etchant is etched from the uppermost surface of the exposed surface 131 of the metal layer 120, and the closer to the uppermost surface, the more the etchant contacts the etchant.

If the side surface 141 of the first circuit pattern 140 is formed by being distorted by an inclined surface or the like, it is difficult to obtain a good fine pattern and it may be difficult to realize a minute circuit.

In addition, as the depth of etching is thicker, that is, as the first plating layer 120 and the metal thin film layer 121 are thicker, the first circuit pattern 140 becomes more distorted and the yield of obtaining a good pattern is lowered do.

However, since the first plating layer 120 and the metal thin film layer 121 are formed together to a thickness of 10 m or less, the present invention minimizes the thickness at which the etching is performed to minimize the degree of distortion of the first circuit pattern 140 Can be reduced.

Also, by reducing the degree of distortion of the first circuit pattern 140 as described above, there is an effect that the second circuit pattern 160 to be formed later can be formed into a good circuit pattern without distortion.

Referring to FIG. 5, the photoresist pattern 130 on the first circuit pattern 140 is removed. The photoresist pattern 130 may be removed using an ashing process.

Referring to FIG. 6, a second plating layer 150 is formed on the first circuit pattern 140 through a plating process to form a second circuit pattern 160, A second plating layer 150 is formed on the first plating layer 120.

The second plating layer 150 may be formed to surround the first circuit pattern 140. That is, the second plating layer 150 may be formed on the top and side surfaces of the first plating layer 120 forming the first circuit pattern 140 and on the side surfaces of the metal foil layer 121.

At this time, a part of the second plating layer 150 may be in direct contact with the insulating member 110. At least a part of the second plating layer 150 may be disposed on the same horizontal plane as the metal thin film layer 121.

The second plating layer 150 may be formed by plating using a gold-plated lead wire. The material of the second plating layer 150 is formed of at least one of a metal material such as copper (Cu), tin (Sn), and nickel (Ni) . Alternatively, the second plating layer 150 may be formed through electroplating.

The reason why the second plating layer 150 is formed is that the first circuit pattern 140 is formed to a thickness of 10 μm or less as described above because the thickness of the first circuit pattern 140 may not be sufficient to stably secure the electric conductivity to be. Thus, the second plating layer 150 may be formed to form the second circuit pattern 160 complementing the thickness of the first circuit pattern 140. That is, the second circuit pattern 160 has a thickness sufficient to stably obtain the electrical conductivity by stacking the second plating layer 150 on the first circuit pattern 140.

As described above, the first plating layer 120 formed in the via hole 111 is also formed to a thickness of 10 μm or less. The thickness of the first plating layer 120 is used to stably secure electrical conductivity for electrical conduction on both surfaces of the printed circuit board It may be insufficient. Therefore, the second plating layer 150 is formed on the first plating layer 120 formed in the via hole 111, and the thickness of the inner wall of the via hole 111 is compensated for.

In addition, in the process of forming the second plating layer 150, not only the distorted shape of the first circuit pattern 140, but also flaws and cracks that may occur in the process of manufacturing the printed circuit board are corrected, The second circuit pattern 160 can be stably formed.

In addition, since the manufacturing process for forming the second circuit patterns 160 and the via holes 111 is simple and the number of steps is small, the printed circuit board can be manufactured at a low cost.

Second Example

7 to 14 are views for explaining a printed circuit board according to the second embodiment and a method of manufacturing the same.

7 to 11 are the same as those in the first embodiment, and therefore detailed description thereof will be omitted.

Referring to FIG. 7, an insulating member 210 having a metal thin film layer 221 formed on both surfaces thereof is prepared. The insulating member 210 may be formed with a via hole 211 passing through both surfaces of the insulating member 210. The via holes 211 may be formed when it is necessary to electrically connect the circuit patterns to be formed on both surfaces of the insulating member 210.

Referring to FIG. 8, a first plating layer 220 is formed by plating the metal thin film layer 221 and the via holes 211.

The thickness of the first plating layer 220 and the metal thin film layer 221 may be less than 10 μm.

Referring to FIG. 9, a photoresist pattern 230 is formed on the first plating layer 220 including the via hole 211 and a portion adjacent to the via hole 211. The exposed surface 231 of the first plating layer 220 not covered by the photoresist pattern 230 is also formed.

Referring to FIGS. 9 and 10, the first plating layer 220 and the metal thin film layer 221 are selectively etched using the photoresist pattern 230 as a mask to form a first circuit pattern 240. Also, the exposed surface 215 of the insulating member 210 is exposed by the etching.

4 (a) and 4 (b), when the first circuit pattern 240 is formed, the first plating layer 220 and the metal foil layer 221 are etched, As shown in the figure, it may be formed by being distorted by an inclined surface or the like. This is because an etchant is etched from the uppermost surface of the exposed surface 231 of the metal layer 220, and the closer to the uppermost surface, the more the etchant contacts the etchant.

In the case where the side surface 241 of the first circuit pattern 240 is distorted by an inclined plane or the like, it is difficult to obtain a good fine pattern, and thus it may be difficult to realize a minute circuit.

In addition, as the depth of etching is thicker, that is, as the first plating layer 220 and the metal foil layer 221 are thicker, the distortion of the first circuit pattern 240 becomes severe and the yield of obtaining a good pattern is decreased do.

However, since the first plating layer 220 and the metal thin film layer 221 are formed to have a thickness of 10 m or less, the thickness of the etching is minimized so that the degree of distortion of the first circuit pattern 240 Can be reduced.

In addition, by reducing the degree of distortion of the first circuit pattern 240 as described above, there is an effect that the second circuit pattern 260 to be formed later can be formed into a good circuit pattern without distortion.

Referring to FIG. 11, the photoresist pattern 230 on the first circuit pattern 240 is removed.

Referring to FIG. 12, an insulating mask 270 is formed on the side surfaces of the first circuit pattern 240 and the exposed surface 215 of the insulating member 210. At this time, the insulation mask 270 is formed to expose the upper surface of the first circuit pattern 240 and the via hole 211. The insulating mask may be formed of, for example, a dry film.

13, a second plating layer 250 is formed on the first circuit pattern 240 and the first plating layer 220 in the via hole 211 without being covered by the insulating mask 270 . A second plating layer 250 is formed on the first circuit pattern 240 to form a second circuit pattern 260. The first circuit pattern 240 is formed on the first plating layer 220 formed in the via hole 211, 2 plating layer 250 is formed to increase the inner wall of the via hole 211.

The second plating layer 250 may be formed by plating using a gold-plated lead wire. The material of the second plating layer 250 may be any one of a metal material such as copper (Cu), tin (Sn), and nickel (Ni) . Alternatively, the second plating layer 250 may be formed through electroplating.

14, the insulating mask 270 formed on the exposed surface 215 of the insulating member 210 is removed and the second circuit pattern 260 and the via hole The printed circuit board according to the second embodiment in which the printed circuit board 211 is formed is manufactured.

The insulating mask 270 may be removed using an ashing process.

The second plating layer 250 may be formed only on the upper surface of the first circuit pattern 240 and may be formed to be wider than the upper surface of the first circuit pattern 240 because the second plating layer 250 is formed by plating. That is, the second width of the second plating layer 250 may be larger than the first width of the upper surface of the first circuit pattern 240.

In addition, since the second plating layer 250 is formed by plating the first circuit pattern 240 with a seed layer, it is not necessary to form a separate seed layer.

The reason why the second plating layer 250 is formed is that the first circuit pattern 240 is formed to a thickness of 10 탆 or less as described above. The thickness of the first circuit pattern 240 may be insufficient for stably securing the electric conductivity It is because. Thus, the second plating layer 250 may be formed to form the second circuit pattern 260 which is complementary to the thickness of the first circuit pattern 240. That is, the second circuit pattern 260 has a thickness sufficient to stably obtain the electrical conductivity by stacking the second plating layer 250 on the first circuit pattern 240.

As described above, the first plating layer 220 formed in the via hole 211 is also formed to have a thickness of 10 μm or less. The thickness of the first plating layer 220 is set to a value that ensures stable electrical conductivity for electrical conduction on both surfaces of the printed circuit board It may be lacking. Accordingly, the second plating layer 250 is formed on the first plating layer 220 formed in the via hole 211 to increase the inner wall of the via hole 211, thereby overcoming such a problem.

In addition, in the process of forming the second plating layer 250, scratches, cracks, and the like that may occur during the manufacturing process of the printed circuit board are corrected, and an advantageous effect of stably forming a good second circuit pattern 260 have.

Also, since the manufacturing process for forming the second circuit patterns 260 and the via holes 211 is simple and the number of processes is small, the printed circuit board can be manufactured with a small cost.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

1 to 14 are views for explaining a printed circuit board according to an embodiment and a manufacturing method thereof.

Claims (9)

Preparing an insulating member having a metal thin film layer formed thereon; Forming a via hole through the metal thin film layer and the insulating member; Forming a first plating layer on the metal thin film layer and the inner wall of the via hole; Selectively removing the first plating layer and the metal foil layer to form a first circuit pattern and a via; And forming a second plating layer on the upper surface and side surfaces of the first plating layer and the side surfaces of the metal thin film layer forming the first circuit pattern and the via. Preparing an insulating member having a metal thin film layer formed thereon; Forming a via hole through the metal thin film layer and the insulating member; Forming a first plating layer on the metal thin film layer and the inner wall of the via hole; Selectively removing the first plating layer and the metal foil layer to form a first circuit pattern and a via; And a second circuit pattern formed on the upper surface of the first circuit pattern, the upper surface of the via, and the inner surface of the via, while covering the side surface of the first circuit pattern on the exposed surface of the insulating member exposed in the formation of the first circuit pattern and the via. Forming an insulating mask that exposes the insulating layer; And And forming a second plating layer on an upper surface of the first circuit pattern exposed by the insulating mask, an upper surface of the via, and an inner wall of the via. 3. The method of claim 2, The second plating layer formed on the upper surface of the first circuit pattern, Wherein the first circuit pattern is in contact with the upper surface of the first circuit pattern without contacting the side surface of the first circuit pattern, Wherein the first circuit pattern has a second width larger than a first width of the upper surface of the first circuit pattern. Insulating member; A via formed in the via hole passing through the insulating member; And A second circuit pattern on the insulating member, The vias may include, A first portion formed on an inner wall of the via hole passing through the insulating member, A second portion formed on the insulating member and connected to the first portion, the second portion corresponding to the second circuit pattern, The second circuit pattern including the second portion of the via A metal thin film layer formed on the insulating member; A first plating layer formed on the metal thin film layer; And And a second plating layer formed on an upper surface and a side surface of the first plating layer and a side surface of the metal thin film layer. 5. The method of claim 4, And a portion of the second plating layer is in contact with the insulating member. Insulating member; A via formed in the via hole passing through the insulating member; A second circuit pattern on the insulating member, The vias may include, A first portion formed on an inner wall of the via hole passing through the insulating member, A second portion formed on the insulating member and connected to the first portion, the second portion corresponding to the second circuit pattern, The second circuit pattern including the second portion of the via A metal thin film layer formed on the insulating member; A first plating layer formed on the metal thin film layer; And And a second plating layer formed on an upper surface and a side surface of the first plating layer and a side surface of the metal thin film layer, Wherein the second plating layer has a second width larger than a first width of the upper surface of the first plating layer. The method according to claim 6, And the second plating layer of the second circuit pattern contacts only the upper surface of the first circuit pattern layer without contacting the side surfaces of the metal thin film layer and the first plating layer. delete The method according to claim 4 or 6, Wherein the thickness of the metal thin film layer and the thickness of the first plating layer are both 10 占 퐉 or less.

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