JP5025443B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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JP5025443B2
JP5025443B2 JP2007319033A JP2007319033A JP5025443B2 JP 5025443 B2 JP5025443 B2 JP 5025443B2 JP 2007319033 A JP2007319033 A JP 2007319033A JP 2007319033 A JP2007319033 A JP 2007319033A JP 5025443 B2 JP5025443 B2 JP 5025443B2
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protruding electrode
substrate
semiconductor device
sealing resin
recess
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JP2009141287A (en
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義明 清水
敏行 福田
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

本発明は、半導体装置を多段に積層したＰＯＰ（Ｐａｃｋａｇｅ Ｏｎ Ｐａｃｋａｇｅ）と呼ばれる半導体装置に関する。   The present invention relates to a semiconductor device called POP (Package On Package) in which semiconductor devices are stacked in multiple stages.

従来の積層型半導体装置は、基板の主面上に搭載された半導体素子を封止樹脂で封止し、その樹脂封止領域の外周に、積層する半導体装置と接続するための突起電極を形成して、上側に他の半導体装置が積層される半導体装置を製造していた。しかし、基板の主面上に樹脂封止領域と樹脂封止されていない領域があるため、基板に反りが発生し、半導体装置を積層する上で問題となっていた。   In a conventional stacked semiconductor device, a semiconductor element mounted on the main surface of a substrate is sealed with a sealing resin, and a protruding electrode is formed on the outer periphery of the resin sealing region to connect to the stacked semiconductor device. Thus, a semiconductor device in which another semiconductor device is stacked on the upper side is manufactured. However, since there are a resin-sealed region and a region that is not resin-sealed on the main surface of the substrate, the substrate is warped, which causes a problem in stacking semiconductor devices.

そこで、主面上に半導体素子と突起電極が配置された基板の主面側の全面を封止樹脂で封止し、封止樹脂の表面から突起電極の平坦化された上部を露出させる技術が提案されている。   Therefore, there is a technique in which the entire surface on the main surface side of the substrate on which the semiconductor element and the protruding electrode are arranged on the main surface is sealed with a sealing resin, and the flattened upper portion of the protruding electrode is exposed from the surface of the sealing resin. Proposed.

具体的には、図１７に示すように、基板１０１の主面上に形成されている配線１０２の素子搭載領域から遠い側の端部上に突起電極１０３を形成し、次に、基板１０１の主面の素子搭載領域に半導体素子１０４を搭載して、配線１０２の素子搭載領域側の端部に金属細線１０５を介して半導体素子１０４の表面に形成されている図示しない電極を電気的に接続する。次に、基板１０１を金型のキャビティに載置して、基板１０１の主面側を、突起電極１０３が完全に埋まるように封止樹脂１０６で封止した後、封止樹脂１０６の上部を切削して、封止樹脂１０６の表面から突起電極１０３の平坦化された上部を露出させ、その後、基板１０１の主面とは反対側の面に形成されている外部端子（図示せず）上にボール電極１０７を設ける技術が提案されている（例えば、特許文献１参照。）。   Specifically, as shown in FIG. 17, the protruding electrode 103 is formed on the end of the wiring 102 formed on the main surface of the substrate 101 on the side far from the element mounting region, and then the substrate 101 The semiconductor element 104 is mounted in the element mounting region on the main surface, and an electrode (not shown) formed on the surface of the semiconductor element 104 is electrically connected to the end of the wiring 102 on the element mounting region side via the fine metal wire 105. To do. Next, the substrate 101 is placed in the cavity of the mold, and the main surface side of the substrate 101 is sealed with the sealing resin 106 so that the protruding electrodes 103 are completely buried, and then the upper portion of the sealing resin 106 is formed. By cutting, the flattened upper portion of the protruding electrode 103 is exposed from the surface of the sealing resin 106, and then on an external terminal (not shown) formed on the surface opposite to the main surface of the substrate 101. A technique has been proposed in which a ball electrode 107 is provided (see, for example, Patent Document 1).

また、他の従来例として、図１８に示すように、基板２０１の主面上に形成されている配線２０２の素子搭載領域から遠い側の端部上に突起電極２０３を形成し、次に、基板２０１の主面の素子搭載領域に半導体素子２０４を搭載して、配線２０２の素子搭載領域側の端部に金属細線２０５を介して半導体素子２０４の表面に形成されている図示しない電極を電気的に接続した後、基板２０１を金型のキャビティに載置する。この金型の上側キャビティには、突起電極２０３の上部が埋め込まれる弾性テープ２０８が予め貼り付けてあり、基板２０１の主面側を封止樹脂２０６で封止した後、弾性テープ２０８を剥がして、封止樹脂２０６の表面から突起電極２０３の上部を突出させ、その後、基板２０１の主面とは反対側の面に形成されている外部端子（図示せず）上にボール電極２０７を設ける技術が提案されている（例えば、特許文献２参照。）。   As another conventional example, as shown in FIG. 18, a protruding electrode 203 is formed on the end of the wiring 202 formed on the main surface of the substrate 201 on the side far from the element mounting region, The semiconductor element 204 is mounted on the element mounting region on the main surface of the substrate 201, and an electrode (not shown) formed on the surface of the semiconductor element 204 is electrically connected to the end of the wiring 202 on the element mounting region side via the thin metal wire 205. After the connection, the substrate 201 is placed in the mold cavity. An elastic tape 208 in which the upper portion of the protruding electrode 203 is embedded is attached in advance to the upper cavity of the mold. After sealing the main surface side of the substrate 201 with the sealing resin 206, the elastic tape 208 is peeled off. A technique of projecting the upper portion of the protruding electrode 203 from the surface of the sealing resin 206 and then providing the ball electrode 207 on an external terminal (not shown) formed on the surface opposite to the main surface of the substrate 201. Has been proposed (see, for example, Patent Document 2).

しかしながら、従来の半導体装置の製造方法では、封止樹脂の表面から突起電極の平坦化された上部を露出させるために、封止樹脂の上部を切削する加工工程が必要であり、製造タスクの面で問題があった。   However, in the conventional method for manufacturing a semiconductor device, in order to expose the flattened upper portion of the protruding electrode from the surface of the sealing resin, a processing step for cutting the upper portion of the sealing resin is necessary. There was a problem.

また、弾性テープを用いて封止樹脂の表面から突起電極の上部を突出させる従来の半導体装置の製造方法では、封止樹脂の上部を切削しない分、製造タスクの面で有利であるが、積層する半導体装置がＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）型の場合、封止樹脂の表面から突出する突起電極の上部にＢＧＡ型半導体装置のボール電極を搭載しなければならず、位置ずれが起こりやすいという問題があった。
特開２００２−３５９３２３号公報 特開２００４−３２７８５５号公報 In addition, the conventional method for manufacturing a semiconductor device in which the upper part of the protruding electrode protrudes from the surface of the sealing resin using an elastic tape is advantageous in terms of manufacturing tasks because the upper part of the sealing resin is not cut. When the semiconductor device to be operated is of the BGA (Ball Grid Array) type, the ball electrode of the BGA type semiconductor device must be mounted on the protruding electrode protruding from the surface of the sealing resin, and there is a problem that the positional deviation is likely to occur. there were.
JP 2002-359323 A JP 2004-327855 A

本発明は、上記問題点に鑑み、封止樹脂の上部を切削する加工を行うことなく、封止樹脂の表面から突起電極の平坦化された上部を露出させることが可能で、積層するＢＧＡ型半導体装置のボール電極を突起電極の上部に搭載する際の位置精度の向上を図ることができる半導体装置の製造方法を提供することを目的とする。   In view of the above problems, the present invention can expose the flattened upper portion of the protruding electrode from the surface of the sealing resin without cutting the upper portion of the sealing resin, and laminates the BGA type. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can improve the positional accuracy when the ball electrode of the semiconductor device is mounted on the upper portion of the protruding electrode.

また、本発明は、封止樹脂の表面から露出する突起電極の上部に凹部を設けるか、あるいは、封止樹脂の表面に凹部を設けて、その凹部から突起電極の上部を露出させることにより、積層するＢＧＡ型半導体装置のボール電極を突起電極の上部に搭載する際の位置精度をより向上させることができる半導体装置の製造方法および半導体装置を提供することを目的とする。   Further, the present invention provides a recess on the top of the protruding electrode exposed from the surface of the sealing resin, or by providing a recess on the surface of the sealing resin and exposing the top of the protruding electrode from the recess, It is an object of the present invention to provide a method of manufacturing a semiconductor device and a semiconductor device capable of further improving the positional accuracy when a ball electrode of a laminated BGA type semiconductor device is mounted on an upper portion of a protruding electrode.

本発明の請求項１記載の半導体装置の製造方法は、基板の主面の素子搭載領域の外部に突起電極を形成する工程と、前記素子搭載領域に半導体素子を搭載して、前記基板と前記半導体素子を電気的に接続する工程と、主面上に前記突起電極と前記半導体素子が配置され、前記半導体素子に電気的に接続された前記基板を、金型のキャビティに載置し、前記金型のキャビティの内面を前記突起電極の上部に押し付けて前記突起電極をクランプする工程と、前記基板が載置された前記金型のキャビティ内に樹脂を注入し、前記基板の主面側を封止する封止樹脂を形成する工程と、前記封止樹脂の表面に凹部を形成し、その凹部の底面から前記突起電極の上部を露出させる工程と、を具備し、前記封止樹脂の表面から前記突起電極の上部が露出する半導体装置を製造する半導体装置の製造方法であって、前記金型のキャビティの内面により、前記封止樹脂の表面から露出する前記突起電極の上部を、前記封止樹脂の表面に対して平坦化し、前記封止樹脂の凹部から露出する前記突起電極の上部の少なくとも一部にさらに凹部を形成することを特徴とする。 According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a protruding electrode outside an element mounting region on a main surface of a substrate; mounting a semiconductor element on the element mounting region; A step of electrically connecting a semiconductor element, the protruding electrode and the semiconductor element are disposed on a main surface, and the substrate electrically connected to the semiconductor element is placed in a cavity of a mold, and Pressing the inner surface of the cavity of the mold against the upper part of the protruding electrode, and clamping the protruding electrode; injecting resin into the cavity of the mold on which the substrate is placed; Forming a sealing resin for sealing; and forming a recess on the surface of the sealing resin, and exposing an upper portion of the protruding electrode from the bottom surface of the recess, and the surface of the sealing resin The top of the protruding electrode is exposed from A method of manufacturing a semiconductor device for manufacturing a conductor arrangement, the inner surface of the mold cavity, an upper portion of the protruding electrodes exposed from the surface of the sealing resin, flattened against the surface of the sealing resin Further, a recess is further formed in at least a part of the upper portion of the protruding electrode exposed from the recess of the sealing resin .

また、本発明の請求項２記載の半導体装置の製造方法は、請求項１記載の半導体装置の製造方法であって、前記封止樹脂の表面から露出する前記突起電極の上部の少なくとも一部に凹部を形成する工程をさらに具備することを特徴とする。   The semiconductor device manufacturing method according to claim 2 of the present invention is the semiconductor device manufacturing method according to claim 1, wherein at least part of the upper portion of the protruding electrode exposed from the surface of the sealing resin. The method further includes the step of forming a recess.

また、本発明の請求項３記載の半導体装置の製造方法は、基板の主面の素子搭載領域の外部に突起電極を形成する工程と、前記素子搭載領域に半導体素子を搭載して、前記基板と前記半導体素子を電気的に接続する工程と、主面上に前記突起電極と前記半導体素子が配置され、前記半導体素子に電気的に接続された前記基板を、金型のキャビティに載置し、前記金型のキャビティの内面を前記突起電極の上部に押し付けて前記突起電極をクランプする工程と、前記基板が載置された前記金型のキャビティ内に樹脂を注入し、前記基板の主面側を封止する封止樹脂を形成する工程と、を具備し、前記封止樹脂の表面から前記突起電極の上部が露出する半導体装置を製造する半導体装置の製造方法であって、前記金型のキャビティの内面には凸部が設けられており、前記凸部により、前記封止樹脂の表面から露出する前記突起電極の上部の少なくとも一部に凹部を形成し、かつ、前記凸部により前記突起電極の凹部の内壁の少なくとも一部に先細りのテーパー形状、円弧形状あるいは段差形状を持たせることを特徴とする。 According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: forming a protruding electrode outside an element mounting area on a main surface of a substrate; mounting a semiconductor element on the element mounting area; A step of electrically connecting the semiconductor element, and the projecting electrode and the semiconductor element are disposed on a main surface, and the substrate electrically connected to the semiconductor element is placed in a cavity of a mold. A step of pressing the inner surface of the cavity of the mold against the upper part of the protruding electrode and clamping the protruding electrode; and injecting resin into the cavity of the mold on which the substrate is placed, and the main surface of the substrate Forming a sealing resin for sealing the side, and a method of manufacturing a semiconductor device for manufacturing a semiconductor device in which an upper portion of the protruding electrode is exposed from the surface of the sealing resin, the mold Convex on the inner surface of the cavity Provided by the convex portion, wherein at least a portion of the top of the protruding electrodes exposed from the surface of the sealing resin in a recess, and at least one inner wall of the recess of the projection electrodes by the protrusions tapering tapered in section, characterized by Rukoto to have a circular arc shape or stepped shape.

また、本発明の請求項４記載の半導体装置の製造方法は、基板の主面の素子搭載領域の外部に突起電極を形成する工程と、前記素子搭載領域に半導体素子を搭載して、前記基板と前記半導体素子を電気的に接続する工程と、主面上に前記突起電極と前記半導体素子が配置され、前記半導体素子に電気的に接続された前記基板を、金型のキャビティに載置し、前記金型のキャビティの内面を前記突起電極の上部に押し付けて前記突起電極をクランプする工程と、前記基板が載置された前記金型のキャビティ内に樹脂を注入し、前記基板の主面側を封止する封止樹脂を形成する工程と、を具備し、前記封止樹脂の表面から前記突起電極の上部が露出する半導体装置を製造する半導体装置の製造方法であって、前記金型のキャビティの内面には凸部が設けられており、前記凸部により前記封止樹脂の表面に凹部を形成し、その凹部の底面から前記突起電極の上部を露出させ、かつ、前記凸部により前記封止樹脂の凹部の内壁の少なくとも一部に先細りのテーパー形状、円弧形状あるいは段差形状を持たせることを特徴とする。 According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: forming a protruding electrode outside an element mounting region on a main surface of a substrate; mounting a semiconductor element on the element mounting region; A step of electrically connecting the semiconductor element, and the projecting electrode and the semiconductor element are disposed on a main surface, and the substrate electrically connected to the semiconductor element is placed in a cavity of a mold. A step of pressing the inner surface of the cavity of the mold against the upper part of the protruding electrode and clamping the protruding electrode; and injecting resin into the cavity of the mold on which the substrate is placed, and the main surface of the substrate Forming a sealing resin for sealing the side, and a method of manufacturing a semiconductor device for manufacturing a semiconductor device in which an upper portion of the protruding electrode is exposed from the surface of the sealing resin, the mold Convex on the inner surface of the cavity Provided, the recess is formed on the surface of the sealing resin by the convex portion, to expose the upper portion of the projecting electrode from the bottom surface of the recess, and, by the projecting portion of the inner wall of the recess of the sealing resin tapering tapered at least in part, characterized by Rukoto to have a circular arc shape or stepped shape.

また、本発明の請求項５記載の半導体装置の製造方法は、基板の主面の素子搭載領域の外部に突起電極を形成する工程と、前記素子搭載領域に半導体素子を搭載して、前記基板と前記半導体素子を電気的に接続する工程と、主面上に前記突起電極と前記半導体素子が配置され、前記半導体素子に電気的に接続された前記基板を、金型のキャビティに載置し、前記金型のキャビティの内面を前記突起電極の上部に押し付けて前記突起電極をクランプする工程と、前記基板が載置された前記金型のキャビティ内に樹脂を注入し、前記基板の主面側を封止する封止樹脂を形成する工程と、を具備し、前記封止樹脂の表面から前記突起電極の上部が露出する半導体装置を製造する半導体装置の製造方法であって、前記金型のキャビティの内面には凸部が設けられており、前記凸部により前記封止樹脂の表面に凹部を形成し、その凹部の底面から前記突起電極の上部を露出させ、かつ、前記凸部により、さらに前記突起電極の上部の少なくとも一部に凹部を形成することを特徴とする。 According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: forming a protruding electrode outside an element mounting area on a main surface of a substrate; mounting a semiconductor element on the element mounting area; A step of electrically connecting the semiconductor element, and the projecting electrode and the semiconductor element are disposed on a main surface, and the substrate electrically connected to the semiconductor element is placed in a cavity of a mold. A step of pressing the inner surface of the cavity of the mold against the upper part of the protruding electrode and clamping the protruding electrode; and injecting resin into the cavity of the mold on which the substrate is placed, and the main surface of the substrate Forming a sealing resin for sealing the side, and a method of manufacturing a semiconductor device for manufacturing a semiconductor device in which an upper portion of the protruding electrode is exposed from the surface of the sealing resin, the mold Convex on the inner surface of the cavity Provided, a recess in the surface of the sealing resin by the convex portion, the from the bottom surface of the recess to expose the upper portion of the protruding electrode, and, by the projecting portion, at least another of the top of the protrusion electrodes A recess is formed in a part.

また、本発明の請求項６記載の半導体装置の製造方法は、請求項５記載の半導体装置の製造方法であって、前記凸部により前記突起電極の凹部の内壁の少なくとも一部に先細りのテーパー形状、円弧形状あるいは段差形状を持たせることを特徴とする。 The semiconductor device manufacturing method according to claim 6 of the present invention is the semiconductor device manufacturing method according to claim 5 , wherein at least a part of the inner wall of the concave portion of the protruding electrode is tapered by the convex portion. It is characterized by having a shape, an arc shape or a step shape.

また、本発明の請求項７記載の半導体装置の製造方法は、請求項１ないし６のいずれかに記載の半導体装置の製造方法であって、前記封止樹脂を形成する際の温度を、前記突起電極の融点よりも低い温度にすることを特徴とする。 A method for manufacturing a semiconductor device according to claim 7 of the present invention is the method for manufacturing a semiconductor device according to any one of claims 1 to 6 , wherein the temperature at which the sealing resin is formed is set to The temperature is lower than the melting point of the protruding electrode.

また、本発明の請求項８記載の半導体装置の製造方法は、請求項１ないし６のいずれかに記載の半導体装置の製造方法であって、前記突起電極を、前記封止樹脂を形成する際の温度よりも高い融点を持つ材料で形成することを特徴とする。 A method for manufacturing a semiconductor device according to claim 8 of the present invention is the method for manufacturing a semiconductor device according to any one of claims 1 to 6 , wherein the protruding electrode is formed on the sealing resin. It is characterized in that it is formed of a material having a melting point higher than the above temperature.

また、本発明の請求項９記載の半導体装置は、基板と、前記基板の主面上に搭載され前記基板に電気的に接続された半導体素子と、前記基板の主面上に形成された突起電極と、前記基板の主面側を封止する封止樹脂と、を備えた半導体装置であって、前記突起電極は、その上部が前記封止樹脂の表面から露出しており、かつその露出した上部の少なくとも一部に凹部を有し、前記突起電極の凹部の内壁の少なくとも一部に先細りのテーパー形状、円弧形状あるいは段差形状を有することを特徴とする。 A semiconductor device according to claim 9 of the present invention includes a substrate, a semiconductor element mounted on the main surface of the substrate and electrically connected to the substrate, and a protrusion formed on the main surface of the substrate. An electrode and a sealing resin that seals the main surface side of the substrate, wherein the protruding electrode has an upper portion exposed from the surface of the sealing resin, and the exposure was possess a recess in at least a part of the upper, tapering tapered on at least part of the inner wall of the recess of the protrusion electrodes, characterized in that it have a circular arc shape or stepped shape.

また、本発明の請求項１０記載の半導体装置は、基板と、前記基板の主面上に搭載され前記基板に電気的に接続された半導体素子と、前記基板の主面上に形成された突起電極と、前記基板の主面側を封止する封止樹脂と、を備えた半導体装置であって、前記突起電極は、その上部が、前記封止樹脂の表面に形成されている凹部の底面から露出しており、前記封止樹脂の凹部の内壁の少なくとも一部に先細りのテーパー形状、円弧形状あるいは段差形状を有することを特徴とする。 According to a tenth aspect of the present invention, there is provided a semiconductor device comprising: a substrate; a semiconductor element mounted on the main surface of the substrate and electrically connected to the substrate; and a protrusion formed on the main surface of the substrate. A semiconductor device comprising: an electrode; and a sealing resin that seals a main surface side of the substrate, wherein the protruding electrode has a bottom surface of a recess formed on a surface of the sealing resin. is exposed from, tapered tapered on at least part of the inner wall of the recess of the sealing resin, and wherein Rukoto to have a circular arc shape or stepped shape.

また、本発明の請求項１１記載の半導体装置は、基板と、前記基板の主面上に搭載され前記基板に電気的に接続された半導体素子と、前記基板の主面上に形成された突起電極と、前記基板の主面側を封止する封止樹脂と、を備えた半導体装置であって、前記突起電極は、その上部が、前記封止樹脂の表面に形成されている凹部の底面から露出しており、前記突起電極は、前記封止樹脂の凹部の底面から露出する上部の少なくとも一部に凹部を有することを特徴とする。 A semiconductor device according to an eleventh aspect of the present invention includes a substrate, a semiconductor element mounted on the main surface of the substrate and electrically connected to the substrate, and a protrusion formed on the main surface of the substrate. A semiconductor device comprising: an electrode; and a sealing resin that seals a main surface side of the substrate, wherein the protruding electrode has a bottom surface of a recess formed on a surface of the sealing resin. The protruding electrode has a recess in at least a part of the upper portion exposed from the bottom surface of the recess of the sealing resin.

また、本発明の請求項１２記載の半導体装置は、請求項１１記載の半導体装置であって、前記突起電極の凹部の内壁の少なくとも一部に先細りのテーパー形状、円弧形状あるいは段差形状を有することを特徴とする。 A semiconductor device according to a twelfth aspect of the present invention is the semiconductor device according to the eleventh aspect , wherein at least a part of the inner wall of the concave portion of the protruding electrode has a tapered shape, an arc shape, or a step shape. It is characterized by.

本発明の好ましい形態によれば、封止樹脂の上部を切削する加工を行うことなく、封止樹脂の表面から突起電極の平坦化された上部を露出させることが可能で、積層するＢＧＡ型半導体装置のボール電極を突起電極の上部に搭載する際の位置精度の向上を図ることができる。   According to a preferred embodiment of the present invention, it is possible to expose the flattened upper portion of the protruding electrode from the surface of the sealing resin without cutting the upper portion of the sealing resin, and to laminate the BGA type semiconductor It is possible to improve the positional accuracy when the ball electrode of the apparatus is mounted on the protruding electrode.

また、封止樹脂の表面から露出する突起電極の上部に凹部を設けるか、あるいは、封止樹脂の表面に凹部を設けて、その凹部から突起電極の上部を露出させることにより、積層するＢＧＡ型半導体装置のボール電極を凹部へ落とし込み、位置規制できるので、ＢＧＡ型半導体装置のボール電極を突起電極の上部に搭載する際の位置精度をより向上させることができる。また、凹部の大きさ（深さや広さ）を変更することで、積層する半導体装置の取り付け高さを変化させることができる。   In addition, a BGA type is formed by providing a concave portion on the protruding electrode exposed from the surface of the sealing resin, or by providing a concave portion on the surface of the sealing resin and exposing the upper portion of the protruding electrode from the concave portion. Since the position of the ball electrode of the BGA type semiconductor device can be regulated by dropping the ball electrode of the semiconductor device into the recess, the positional accuracy when mounting the ball electrode of the BGA type semiconductor device on the protruding electrode can be further improved. In addition, by changing the size (depth or width) of the recess, the mounting height of the stacked semiconductor devices can be changed.

（実施の形態１）
以下、本発明の半導体装置の製造方法および半導体装置の実施の形態１について図面を交えて説明する。 (Embodiment 1)
Hereinafter, a semiconductor device manufacturing method and a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.

本実施の形態１における半導体装置の製造方法について、図１ないし図４に示す工程断面図を用いて説明する。なお、ここでは、複数の半導体装置を同時に樹脂成形するＭＡＰ方式について説明する。   A method for manufacturing a semiconductor device according to the first embodiment will be described with reference to process cross-sectional views shown in FIGS. Here, a MAP method in which a plurality of semiconductor devices are molded simultaneously with resin will be described.

まず、図１に示すように、基板１の主面の素子搭載領域３の周囲に形成されている配線２の素子搭載領域３から遠い側の端部上に突起電極４を形成する。なお、突起電極４は、半田ボールでもよいし、ＡｕやＮｉ、Ｃｕからなるめっきバンプでもよいし、樹脂コアに金属めっきを施したバンプでもよいし、Ａｕスタッドバンプに導電ペーストを上乗せしたような複合バンプでもよく、リフローにより形成する。   First, as shown in FIG. 1, the protruding electrode 4 is formed on the end of the wiring 2 formed on the main surface of the substrate 1 on the side far from the element mounting area 3. The protruding electrode 4 may be a solder ball, a plated bump made of Au, Ni, or Cu, a bump obtained by metal plating on a resin core, or a conductive paste on an Au stud bump. It may be a composite bump and is formed by reflow.

次に、図２に示すように、基板１の主面の素子搭載領域３に半導体素子５を搭載し、配線２の素子搭載領域３側の端部に金属細線６を介して半導体素子５の表面に形成されている図示しない電極を電気的に接続する。金属細線６のループ高さは、後述する突起電極４の封止樹脂の表面から露出する面の高さよりも低く設定する。   Next, as shown in FIG. 2, the semiconductor element 5 is mounted on the element mounting region 3 on the main surface of the substrate 1, and the end of the wiring 2 on the element mounting region 3 side is connected to the end of the semiconductor element 5 via the thin metal wire 6. An electrode (not shown) formed on the surface is electrically connected. The loop height of the fine metal wire 6 is set to be lower than the height of the surface exposed from the surface of the sealing resin of the protruding electrode 4 described later.

なお、本実施の形態１では、基板と半導体素子を金属細線を介して電気的に接続する構成の半導体装置について説明するが、基板の主面に対向する面にバンプが配置された半導体素子を、素子搭載領域に端子が形成された基板に搭載し、バンプを介して基板と半導体素子とを電気的に接続したいわゆるフリップチップ接続構造の半導体装置にも適用可能である。この場合、後述する突起電極４の封止樹脂から露出する面の高さは、半導体素子の上面の高さよりも高くするのが好ましい。   In the first embodiment, a semiconductor device having a structure in which a substrate and a semiconductor element are electrically connected via a thin metal wire will be described. However, a semiconductor element in which bumps are arranged on a surface facing the main surface of the substrate is described. It can also be applied to a semiconductor device having a so-called flip-chip connection structure in which the substrate is mounted on a substrate having terminals formed in the element mounting region, and the substrate and the semiconductor element are electrically connected via bumps. In this case, it is preferable that the height of the surface exposed from the sealing resin of the protruding electrode 4 described later is higher than the height of the upper surface of the semiconductor element.

次に、図３に示すように、基板１を金型７のキャビティ８に載置して、金型７により基板１をクランプする。また、キャビティ８の上面は突起電極４よりも低い高さとなっており、基板１をクランプすると同時に、上側キャビティの内面により突起電極４の上部もクランプする。本実施の形態１では、金型７の突起電極４の上部に接触する部分は平坦であり、上側キャビティの内面を突起電極４の上部に押し付けることで、突起電極４の上部は、後述する封止樹脂の表面に対して平坦化される。   Next, as shown in FIG. 3, the substrate 1 is placed in the cavity 8 of the mold 7, and the substrate 1 is clamped by the mold 7. Further, the upper surface of the cavity 8 is lower than the protruding electrode 4, and at the same time as the substrate 1 is clamped, the upper portion of the protruding electrode 4 is also clamped by the inner surface of the upper cavity. In the first embodiment, the portion of the mold 7 that contacts the upper portion of the protruding electrode 4 is flat, and the upper surface of the protruding electrode 4 is sealed as described later by pressing the inner surface of the upper cavity against the upper portion of the protruding electrode 4. It is flattened against the surface of the stop resin.

このように基板１と突起電極４をクランプした状態でキャビティ８内に樹脂を注入し、その注入した樹脂を熱硬化させ、封止樹脂を形成する。樹脂が熱硬化した時点で金型７を開放し、主面側の全面が封止樹脂により封止された基板１を取り出す。その結果、突起電極４の金型７に押し付けられていた部分が封止樹脂の表面から露出する。この封止樹脂から露出する突起電極４の上部が、当該半導体装置の上側に積層する他の半導体装置の下部電極に電気的に接続する上部電極となる。   In this manner, the resin is injected into the cavity 8 with the substrate 1 and the protruding electrode 4 clamped, and the injected resin is thermally cured to form a sealing resin. When the resin is thermally cured, the mold 7 is opened, and the substrate 1 whose entire main surface is sealed with the sealing resin is taken out. As a result, the portion of the protruding electrode 4 pressed against the mold 7 is exposed from the surface of the sealing resin. The upper part of the protruding electrode 4 exposed from the sealing resin becomes an upper electrode that is electrically connected to the lower electrode of another semiconductor device stacked on the upper side of the semiconductor device.

なお、封止樹脂を形成する際の温度を、突起電極４の融点よりも低い温度にするか、あるいは、突起電極４を、封止樹脂を形成する際の温度よりも高い融点を持つ材料により形成するのが好ましい。   The temperature at which the sealing resin is formed is set to a temperature lower than the melting point of the protruding electrode 4, or the protruding electrode 4 is made of a material having a melting point higher than the temperature at which the sealing resin is formed. Preferably formed.

次に、金型から取り出した基板１の主面とは反対側の面に形成されている外部端子（図示せず）上にボール電極（半田ボールやＡｕバンプ等）１０を設けた後、個片化して、図４に示す、封止樹脂９の表面から突起電極４の平坦化された上部が露出するＢＧＡ型半導体装置１１を得る。 Then, after the main surface of the substrate 1 taken out from the mold in which a ball electrode (solder ball or Au bump or the like) 10 on the external terminals formed on the opposite side (not shown), pieces The BGA type semiconductor device 11 is obtained in which the flattened upper portion of the protruding electrode 4 is exposed from the surface of the sealing resin 9 shown in FIG.

なお、突起電極の封止樹脂の表面から露出している面にプラズマを照射して、その面に不着している酸化膜および樹脂ワックス等の有機成分を除去すれば、半導体装置を積層する際の半田接合が良好になる。   When the semiconductor device is stacked, the surface exposed from the surface of the sealing resin of the protruding electrode is irradiated with plasma to remove organic components such as oxide film and resin wax that are not attached to the surface. The solder joint becomes better.

またここでは、ＢＧＡ型半導体装置を製造する場合について説明したが、無論、ＬＧＡ（Ｌａｎｄ Ｇｒｉｄ Ａｒｒａｙ）型半導体装置の製造にも適用することができる。また、複数の半導体装置を同時に樹脂成形するＭＡＰ方式について説明したが、単数の半導体装置を個別に封止する個片成型方式にも適用することができる。   Although the case of manufacturing a BGA type semiconductor device has been described here, it is needless to say that the present invention can also be applied to the manufacture of an LGA (Land Grid Array) type semiconductor device. Further, although the MAP method in which a plurality of semiconductor devices are simultaneously resin-molded has been described, the present invention can also be applied to a single-piece molding method in which a single semiconductor device is individually sealed.

以上のように製造した半導体装置１１の上側にＢＧＡ型半導体装置１２を搭載する工程を説明するための工程断面図を図５に示す。図５に示すように、突起電極４の半導体装置１１の表面から露出する部分（上部電極）は平坦化されているので、その上部電極へ、積層するＢＧＡ型半導体装置１２のボール電極（下部電極）１３を搭載する際の位置精度が向上する。また、積層する半導体装置がＢＧＡ型の場合、半田ペーストを追加することなく直接実装することが可能になる。   FIG. 5 is a process cross-sectional view for explaining a process of mounting the BGA type semiconductor device 12 on the upper side of the semiconductor device 11 manufactured as described above. As shown in FIG. 5, since the portion (upper electrode) exposed from the surface of the semiconductor device 11 of the protruding electrode 4 is flattened, the ball electrode (lower electrode) of the BGA type semiconductor device 12 to be stacked on the upper electrode. ) Position accuracy when mounting 13 is improved. Further, when the semiconductor device to be stacked is a BGA type, it can be directly mounted without adding a solder paste.

以上のように、本実施の形態１によれば、半導体装置の上側を切削する加工を行うことなく、封止樹脂の表面から突起電極の平坦化された上部を露出させることができる。   As described above, according to the first embodiment, it is possible to expose the flattened upper portion of the protruding electrode from the surface of the sealing resin without performing a process of cutting the upper side of the semiconductor device.

なお、表面から突起電極の平坦化された上部が露出する封止樹脂を形成した後、パンチ加工、プレス加工、ザグリ加工もしくはレーザ加工のいずれかの加工法で封止樹脂の表面に凹部を形成して、その凹部の底面から突起電極の上部を露出させてもよい。   In addition, after forming the sealing resin that exposes the flattened upper part of the protruding electrode from the surface, a recess is formed on the surface of the sealing resin by any one of punching, pressing, counterboring, or laser processing. Then, the upper portion of the protruding electrode may be exposed from the bottom surface of the concave portion.

図６に封止樹脂の平坦な表面から突起電極の上部が露出する半導体装置を使用した積層型半導体装置の断面図を示し、図７に封止樹脂の表面に形成された凹部の底面から突起電極の上部が露出する半導体装置を使用した積層型半導体装置の断面図を示す。   FIG. 6 shows a cross-sectional view of a stacked semiconductor device using a semiconductor device in which the upper portion of the protruding electrode is exposed from the flat surface of the sealing resin, and FIG. 7 shows a protrusion from the bottom surface of the recess formed on the surface of the sealing resin. FIG. 2 is a cross-sectional view of a stacked semiconductor device using a semiconductor device in which an upper portion of an electrode is exposed.

図６に示す積層型半導体装置の積層状態に比べて、図７に示す積層型半導体装置では、積層するＢＧＡ型半導体装置のボール電極を凹部に取り込むことができるため、凹部の大きさ（深さや広さ）を変更することで、半導体装置の積層高さを変えることが可能となる。 Compared to stacked state of the stacked type semiconductor device shown in FIG. 6, in the stacked semiconductor device is shown in Fig. 7, since the ball electrode of the BGA type semiconductor device to be stacked can be incorporated into the recess, the size of the recess (depth It is possible to change the stack height of the semiconductor device by changing the sheath width.

なお、封止樹脂の表面に凹部を形成し、その凹部の底面から突起電極の上部を露出させる場合に限らず、封止樹脂の表面から露出する突起電極の上部の少なくとも一部にのみ凹部を形成してもよいし、封止樹脂の表面に凹部を形成し、その凹部の底面から突起電極の上部を露出させ、且つその露出する突起電極の上部の少なくとも一部にさらに凹部を形成してもよい。   The concave portion is formed on the surface of the sealing resin and the upper portion of the protruding electrode is exposed from the bottom surface of the concave portion, but the concave portion is formed only on at least a part of the upper portion of the protruding electrode exposed from the surface of the sealing resin. Or forming a recess on the surface of the sealing resin, exposing the upper portion of the protruding electrode from the bottom surface of the recess, and further forming a recess on at least a part of the exposed upper portion of the protruding electrode. Also good.

（実施の形態２）
以下、本発明の半導体装置の製造方法および半導体装置の実施の形態２について、前述した実施の形態１と異なる点を、図８ないし図１０を用いて説明する。なお、前述した実施の形態１で説明した部材と同一の部材には同一符号を付している。 (Embodiment 2)
Hereinafter, a method for manufacturing a semiconductor device and a second embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 8 to 10 for differences from the first embodiment. The same members as those described in the first embodiment are denoted by the same reference numerals.

図８は、本実施の形態２における半導体装置の製造工程の一部を示す工程断面図であり、主面上に突起電極４と半導体素子５が配置され、半導体素子５に金属細線６を介して電気的に接続された基板１を、金型７のキャビティ８に載置した状態を示している。   FIG. 8 is a process cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the second embodiment. The protruding electrode 4 and the semiconductor element 5 are arranged on the main surface, and the semiconductor element 5 is interposed with the metal thin wire 6. 3 shows a state where the electrically connected substrate 1 is placed in the cavity 8 of the mold 7.

図８に示すように、金型７の上側キャビティの内面には凸部１４が設けられており、基板１を金型７によりクランプする際に、突起電極４の上部に凸部１４を押し当てて、突起電極４をクランプする。本実施の形態２では、凸部１４の投影面積は、突起電極４の封止樹脂の表面から露出する部分の投影面積と同じ大きさである。   As shown in FIG. 8, a convex portion 14 is provided on the inner surface of the upper cavity of the mold 7. When the substrate 1 is clamped by the mold 7, the convex portion 14 is pressed against the upper portion of the protruding electrode 4. Then, the protruding electrode 4 is clamped. In the second embodiment, the projected area of the convex portion 14 is the same size as the projected area of the portion of the protruding electrode 4 exposed from the surface of the sealing resin.

このように基板１と突起電極４をクランプした状態でキャビティ８内に樹脂を注入し、その注入した樹脂を熱硬化させ、封止樹脂を形成することにより、図９に示すように、突起電極４の封止樹脂９から露出する上部に凹部１５が形成される。本実施の形態２では、凸部１４は円柱形状であり、突起電極４の凹部１５の底面は平坦化される。   As shown in FIG. 9, the resin is injected into the cavity 8 with the substrate 1 and the protruding electrode 4 clamped, and the injected resin is thermally cured to form a sealing resin. A concave portion 15 is formed in the upper portion exposed from the sealing resin 9 of 4. In the second embodiment, the convex portion 14 has a cylindrical shape, and the bottom surface of the concave portion 15 of the protruding electrode 4 is flattened.

図１０に、図９に示す半導体装置１１の上側にＢＧＡ型半導体装置１２を搭載する工程を説明するための工程断面図を示す。図１０に示すように、突起電極４の半導体装置１１の表面から露出する部分（上部電極）に凹部１５が設けられているので、ＢＧＡ型半導体装置１２を積層する際に、ＢＧＡ型半導体装置１２のボール電極（下部電極）１３をその凹部１５に落とし込み、位置規制でき、積層する半導体装置を搭載する際の位置精度をより向上させることができる。さらに、凹部１５の大きさ（深さや広さ）を変更することで、積層する半導体装置の取り付け高さを変化させることができる。   FIG. 10 is a process cross-sectional view for explaining a process of mounting the BGA type semiconductor device 12 on the upper side of the semiconductor device 11 shown in FIG. As shown in FIG. 10, since the concave portion 15 is provided in a portion (upper electrode) of the protruding electrode 4 exposed from the surface of the semiconductor device 11, the BGA type semiconductor device 12 is stacked when the BGA type semiconductor device 12 is stacked. The ball electrode (lower electrode) 13 can be dropped into the concave portion 15 to regulate the position, and the positional accuracy when mounting the semiconductor devices to be stacked can be further improved. Furthermore, by changing the size (depth or width) of the recess 15, the mounting height of the semiconductor device to be stacked can be changed.

なお、本実施の形態２では、凸部１４の投影面積が、突起電極４の封止樹脂９の表面から露出する部分の投影面積と同じ大きさである場合について説明したが、突起電極４の封止樹脂９の表面から露出する部分よりも投影面積が小さい凸部を設けてもよい。この場合、突起電極４の封止樹脂９の表面から露出する部分の一部に凹部が形成され、その凹部の周囲は封止樹脂９の表面に対して平坦化される。   In the second embodiment, the case where the projected area of the convex portion 14 is the same size as the projected area of the portion exposed from the surface of the sealing resin 9 of the protruding electrode 4 has been described. A convex portion having a projected area smaller than the portion exposed from the surface of the sealing resin 9 may be provided. In this case, a recess is formed in a part of the portion of the protruding electrode 4 exposed from the surface of the sealing resin 9, and the periphery of the recess is flattened with respect to the surface of the sealing resin 9.

また、金型に円柱形状の凸部を設けた場合について説明したが、凸部は円すい形状や半球形状、先細りの階段形状等であってもよく、凹部の内壁の少なくとも一部に先細りのテーパ形状、円弧形状あるいは段差形状を持たせることで、金型を開放する際の型離れ性を向上させることができる。   Further, the case where the cylindrical convex portion is provided in the mold has been described, but the convex portion may be a conical shape, a hemispherical shape, a tapered step shape, or the like, and a tapered taper is formed on at least a part of the inner wall of the concave portion. By providing the shape, the arc shape, or the step shape, the mold releasability when the mold is opened can be improved.

（実施の形態３）
以下、本発明の半導体装置の製造方法および半導体装置の実施の形態３について、前述した実施の形態１、２と異なる点を、図１１ないし図１３を用いて説明する。なお、前述した実施の形態１、２で説明した部材と同一の部材には同一符号を付している。 (Embodiment 3)
Hereinafter, a method for manufacturing a semiconductor device and a third embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 11 to 13 for differences from the first and second embodiments. The same members as those described in the first and second embodiments are denoted by the same reference numerals.

図１１は、本実施の形態３における半導体装置の製造工程の一部を示す工程断面図であり、主面上に突起電極４と半導体素子５が配置され、半導体素子５に金属細線６を介して電気的に接続された基板１を、金型７のキャビティ８に載置した状態を示している。   FIG. 11 is a process cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the third embodiment. The protruding electrode 4 and the semiconductor element 5 are arranged on the main surface, and the semiconductor element 5 is interposed with the fine metal wire 6. 3 shows a state where the electrically connected substrate 1 is placed in the cavity 8 of the mold 7.

本実施の形態３は、金型７の上側キャビティの内面に設けた凸部１６の投影面積が、突起電極の封止樹脂の表面から露出する部分の投影面積よりも大きい点が、前述した実施の形態２と異なる。   The third embodiment is that the projected area of the convex portion 16 provided on the inner surface of the upper cavity of the mold 7 is larger than the projected area of the portion exposed from the surface of the sealing resin of the protruding electrode. This is different from the second form.

図１１に示すように、基板１を金型７によりクランプする際に、突起電極４の上部に凸部１６を押し当てて、突起電極４をクランプし、その状態でキャビティ８内に樹脂を注入し、その注入した樹脂を熱硬化させ、封止樹脂を形成することにより、図１２に示すように、封止樹脂９の表面に凹部１７が形成され、その凹部１７の底面から突起電極４の上部が露出する。本実施の形態３では、凸部１６は円柱形状であり、突起電極４の上部は平坦化される。   As shown in FIG. 11, when the substrate 1 is clamped by the mold 7, the protruding portion 4 is pressed against the upper portion of the protruding electrode 4 to clamp the protruding electrode 4, and in this state, resin is injected into the cavity 8. Then, the injected resin is thermally cured to form a sealing resin, whereby a recess 17 is formed on the surface of the sealing resin 9 as shown in FIG. The upper part is exposed. In the third embodiment, the convex portion 16 has a cylindrical shape, and the upper portion of the protruding electrode 4 is flattened.

図１３に、図１２に示す半導体装置１１の上側にＢＧＡ型半導体装置１２を搭載する工程を説明するための工程断面図を示す。図１３に示すように、封止樹脂９の表面に凹部１７が設けられ、その凹部１７の底面から突起電極４の上部（上部電極）が露出しているので、ＢＧＡ型半導体装置１２を積層する際に、ＢＧＡ型半導体装置１２のボール電極（下部電極）１３をその凹部１７に落とし込み、位置規制でき、積層する半導体装置を搭載する際の位置精度をより向上させることができる。さらに、封止樹脂９に凹部１７を設けたので、隣接するボール電極との半田ショートを防止することができる。また、凹部１７の大きさ（深さや広さ）を変更することで、積層する半導体装置の取り付け高さを変化させることができる。   FIG. 13 is a process cross-sectional view for explaining a process of mounting the BGA type semiconductor device 12 on the upper side of the semiconductor device 11 shown in FIG. As shown in FIG. 13, the concave portion 17 is provided on the surface of the sealing resin 9, and the upper portion (upper electrode) of the protruding electrode 4 is exposed from the bottom surface of the concave portion 17, so that the BGA type semiconductor device 12 is laminated. At this time, the ball electrode (lower electrode) 13 of the BGA type semiconductor device 12 can be dropped into the concave portion 17 and the position can be regulated, and the positional accuracy when mounting the semiconductor devices to be stacked can be further improved. Furthermore, since the recess 17 is provided in the sealing resin 9, it is possible to prevent a solder short-circuit with the adjacent ball electrode. Further, by changing the size (depth or width) of the recess 17, the mounting height of the semiconductor device to be stacked can be changed.

なお、本実施の形態３では、金型に円柱形状の凸部を設けた場合について説明したが、凸部は円すい形状や半球形状、先細りの階段形状等であってもよく、凹部の内壁の少なくとも一部に先細りのテーパ形状、円弧形状あるいは段差形状を持たせることで、金型を開放する際の型離れ性を向上させることができる。   In addition, in this Embodiment 3, although the case where the column-shaped convex part was provided in the metal mold | die was demonstrated, a convex part may be conical shape, hemispherical shape, a tapered staircase shape, etc., and the inner wall of a recessed part By providing at least a part with a tapered shape, an arc shape or a step shape, it is possible to improve the mold releasability when the mold is opened.

（実施の形態４）
以下、本発明の半導体装置の製造方法および半導体装置の実施の形態４について、前述した実施の形態１ないし３と異なる点を、図１４ないし図１６を用いて説明する。なお、前述した実施の形態１ないし３で説明した部材と同一の部材には同一符号を付している。 (Embodiment 4)
Hereinafter, a method for manufacturing a semiconductor device and a fourth embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 14 to 16 for differences from the first to third embodiments. The same members as those described in the first to third embodiments are denoted by the same reference numerals.

図１４は、本実施の形態４における半導体装置の製造工程の一部を示す工程断面図であり、主面上に突起電極４と半導体素子５が配置され、半導体素子５に金属細線６を介して電気的に接続された基板１を、金型７のキャビティ８に載置した状態を示している。   FIG. 14 is a process cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the fourth embodiment, in which the protruding electrode 4 and the semiconductor element 5 are arranged on the main surface, and the metal element 6 is interposed in the semiconductor element 5. 3 shows a state where the electrically connected substrate 1 is placed in the cavity 8 of the mold 7.

本実施の形態４は、金型７の上側キャビティの内面に設けた凸部１８が２段となっており、１段目により封止樹脂の表面に凹部を形成し、２段目により封止樹脂の凹部から露出する突起電極の上部にさらに凹部を形成する点が前述した実施の形態３と異なる。   In the fourth embodiment, the convex portion 18 provided on the inner surface of the upper cavity of the mold 7 has two steps, the concave portion is formed on the surface of the sealing resin by the first step, and the sealing is performed by the second step. The difference from Embodiment 3 described above is that a recess is further formed on the protruding electrode exposed from the recess of the resin.

図１４に示すように、基板１を金型７によりクランプする際に、突起電極４の上部に凸部１８を押し当てて、突起電極４をクランプし、その状態でキャビティ８内に樹脂を注入し、その注入した樹脂を熱硬化させ、封止樹脂を形成することにより、図１５に示すように、封止樹脂９の表面に凹部１９が形成され、その凹部１９の底面から突起電極４の上部が露出し、かつその露出している突起電極４の上部に凹部２０が形成される。本実施の形態４では、凸部１８は２段の円柱形状であり、突起電極４の上部は平坦化される。   As shown in FIG. 14, when the substrate 1 is clamped by the mold 7, the protruding portion 18 is pressed against the upper portion of the protruding electrode 4 to clamp the protruding electrode 4, and in this state, resin is injected into the cavity 8. Then, the injected resin is thermally cured to form a sealing resin, whereby a recess 19 is formed on the surface of the sealing resin 9 as shown in FIG. The upper portion is exposed, and a recess 20 is formed on the exposed protruding electrode 4. In the fourth embodiment, the convex portion 18 has a two-stage cylindrical shape, and the upper portion of the protruding electrode 4 is flattened.

図１６に、図１５に示す半導体装置１１の上側にＢＧＡ型半導体装置１２を搭載する工程を説明するための工程断面図を示す。図１６に示すように、封止樹脂９の表面に凹部１９が設けられ、その凹部１９の底面から突起電極４の上部（上部電極）が露出し、かつその露出している突起電極４の上部に凹部２０が設けられているので、ＢＧＡ型半導体装置１２を積層する際に、ＢＧＡ型半導体装置１２のボール電極（下部電極）１３を突起電極４の凹部２０に落とし込み、位置規制でき、積層する半導体装置を搭載する際の位置精度をより向上させることができる。さらに、封止樹脂９に凹部１９を設けたので、隣接するボール電極との半田ショートを防止することができる。また、凹部１９、２０の大きさ（深さや広さ）を変更することで、積層する半導体装置の取り付け高さを変化させることができる。   FIG. 16 is a process cross-sectional view for explaining a process of mounting the BGA type semiconductor device 12 on the upper side of the semiconductor device 11 shown in FIG. As shown in FIG. 16, a concave portion 19 is provided on the surface of the sealing resin 9, and the upper portion (upper electrode) of the protruding electrode 4 is exposed from the bottom surface of the concave portion 19, and the exposed upper portion of the protruding electrode 4. Since the recess 20 is provided in the BGA type semiconductor device 12, when the BGA type semiconductor device 12 is stacked, the ball electrode (lower electrode) 13 of the BGA type semiconductor device 12 is dropped into the recess 20 of the protruding electrode 4 so that the position can be regulated and stacked. The positional accuracy when mounting the semiconductor device can be further improved. Further, since the recess 19 is provided in the sealing resin 9, it is possible to prevent a solder short with the adjacent ball electrode. Further, by changing the size (depth or width) of the recesses 19 and 20, the mounting height of the stacked semiconductor devices can be changed.

なお、本実施の形態４では、凸部１８が２段の円柱形状である場合について説明したが、封止樹脂９と突起電極４の少なくとも一方の凹部の内壁の少なくとも一部を先細りのテーパ形状、円弧形状あるいは段差形状にする凸部を用いることで、金型を開放する際の型離れ性を向上させることができる。   In the fourth embodiment, the case where the convex portion 18 has a two-stage cylindrical shape has been described. However, at least a part of the inner wall of at least one concave portion of the sealing resin 9 and the protruding electrode 4 is tapered. By using the convex portion having an arc shape or a step shape, the mold releasability when the mold is opened can be improved.

本発明にかかる半導体装置の製造方法および半導体装置によれば、封止樹脂の上部を切削する加工を行うことなく、封止樹脂の表面から突起電極の平坦化された上部を露出させることが可能で、積層するＢＧＡ型半導体装置のボール電極を突起電極の上部に搭載する際の位置精度の向上を図ることができ、半導体装置を多段に積層したＰＯＰに有用である。   According to the method for manufacturing a semiconductor device and the semiconductor device according to the present invention, it is possible to expose the flattened upper portion of the protruding electrode from the surface of the sealing resin without cutting the upper portion of the sealing resin. Thus, it is possible to improve the positional accuracy when the ball electrode of the BGA type semiconductor device to be stacked is mounted on the upper part of the protruding electrode, which is useful for POPs in which semiconductor devices are stacked in multiple stages.

本発明の実施の形態１における半導体装置の製造工程を説明するための工程断面図（その１）Process sectional drawing for demonstrating the manufacturing process of the semiconductor device in Embodiment 1 of this invention (the 1) 本発明の実施の形態１における半導体装置の製造工程を説明するための工程断面図（その２）Process sectional drawing for demonstrating the manufacturing process of the semiconductor device in Embodiment 1 of this invention (the 2) 本発明の実施の形態１における半導体装置の製造工程を説明するための工程断面図（その３）Process sectional drawing for demonstrating the manufacturing process of the semiconductor device in Embodiment 1 of this invention (the 3) 本発明の実施の形態１における半導体装置の製造工程を説明するための工程断面図（その４）Process sectional drawing for demonstrating the manufacturing process of the semiconductor device in Embodiment 1 of this invention (the 4) 本発明の実施の形態１における積層型半導体装置の製造工程を説明するための工程断面図Process sectional drawing for demonstrating the manufacturing process of the laminated semiconductor device in Embodiment 1 of this invention 本発明の実施の形態１における積層型半導体装置の断面図Sectional drawing of the laminated semiconductor device in Embodiment 1 of this invention 本発明の実施の形態１における積層型半導体装置の他例の断面図Sectional drawing of the other example of the laminated semiconductor device in Embodiment 1 of this invention 本発明の実施の形態２における半導体装置の製造工程を説明するための工程断面図（その１）Process sectional drawing for demonstrating the manufacturing process of the semiconductor device in Embodiment 2 of this invention (the 1) 本発明の実施の形態２における半導体装置の製造工程を説明するための工程断面図（その２）Process sectional drawing for demonstrating the manufacturing process of the semiconductor device in Embodiment 2 of this invention (the 2) 本発明の実施の形態２における積層型半導体装置の製造工程を説明するための工程断面図Process sectional drawing for demonstrating the manufacturing process of the laminated semiconductor device in Embodiment 2 of this invention 本発明の実施の形態３における半導体装置の製造工程を説明するための工程断面図（その１）Process sectional drawing for demonstrating the manufacturing process of the semiconductor device in Embodiment 3 of this invention (the 1) 本発明の実施の形態３における半導体装置の製造工程を説明するための工程断面図（その２）Process sectional drawing for demonstrating the manufacturing process of the semiconductor device in Embodiment 3 of this invention (the 2) 本発明の実施の形態３における積層型半導体装置の製造工程を説明するための工程断面図Process sectional drawing for demonstrating the manufacturing process of the laminated semiconductor device in Embodiment 3 of this invention 本発明の実施の形態４における半導体装置の製造工程を説明するための工程断面図（その１）Process sectional drawing for demonstrating the manufacturing process of the semiconductor device in Embodiment 4 of this invention (the 1) 本発明の実施の形態４における半導体装置の製造工程を説明するための工程断面図（その２）Process sectional drawing for demonstrating the manufacturing process of the semiconductor device in Embodiment 4 of this invention (the 2) 本発明の実施の形態４における積層型半導体装置の製造工程を説明するための工程断面図Process sectional drawing for demonstrating the manufacturing process of the laminated semiconductor device in Embodiment 4 of this invention 従来の半導体装置の製造方法を説明するための工程断面図Process sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device 従来の半導体装置の製造方法の他例を説明するための工程断面図Process sectional drawing for demonstrating the other example of the manufacturing method of the conventional semiconductor device

符号の説明Explanation of symbols

１ 基板
２ 配線
３ 素子搭載領域
４ 突起電極
５ 半導体素子
６ 金属細線
７ 金型
８ キャビティ
９ 封止樹脂
１０ ボール電極
１１ 半導体装置
１２ 積層する半導体装置
１３ ボール電極
１４、１６、１８ 凸部
１５、１７、１９、２０ 凹部
１０１、２０１ 基板
１０２、２０２ 配線
１０３、２０３ 突起電極
１０４、２０４ 半導体素子
１０５、２０５ 金属細線
１０６、２０６ 封止樹脂
１０７、２０７ ボール電極
２０８ 弾性テープ DESCRIPTION OF SYMBOLS 1 Substrate 2 Wiring 3 Element mounting area 4 Protruding electrode 5 Semiconductor element 6 Metal thin wire 7 Mold 8 Cavity 9 Sealing resin 10 Ball electrode 11 Semiconductor device 12 Semiconductor device to be stacked 13 Ball electrodes 14, 16, 18 Protruding portions 15, 17 , 19, 20 Recess 101, 201 Substrate 102, 202 Wiring 103, 203 Protruding electrode 104, 204 Semiconductor element 105, 205 Metal wire 106, 206 Sealing resin 107, 207 Ball electrode 208 Elastic tape

Claims (12)

基板の主面の素子搭載領域の外部に突起電極を形成する工程と、
前記素子搭載領域に半導体素子を搭載して、前記基板と前記半導体素子を電気的に接続する工程と、
主面上に前記突起電極と前記半導体素子が配置され、前記半導体素子に電気的に接続された前記基板を、金型のキャビティに載置し、前記金型のキャビティの内面を前記突起電極の上部に押し付けて前記突起電極をクランプする工程と、
前記基板が載置された前記金型のキャビティ内に樹脂を注入し、前記基板の主面側を封止する封止樹脂を形成する工程と、
前記封止樹脂の表面に凹部を形成し、その凹部の底面から前記突起電極の上部を露出させる工程と、
を具備し、前記封止樹脂の表面から前記突起電極の上部が露出する半導体装置を製造する半導体装置の製造方法であって、
前記金型のキャビティの内面により、前記封止樹脂の表面から露出する前記突起電極の上部を、前記封止樹脂の表面に対して平坦化し、
前記封止樹脂の凹部から露出する前記突起電極の上部の少なくとも一部にさらに凹部を形成する
ことを特徴とする半導体装置の製造方法。 Forming a protruding electrode outside the element mounting region on the main surface of the substrate;
Mounting a semiconductor element in the element mounting region and electrically connecting the substrate and the semiconductor element;
The protruding electrode and the semiconductor element are disposed on a main surface, and the substrate electrically connected to the semiconductor element is placed on a cavity of a mold, and the inner surface of the cavity of the mold is placed on the protruding electrode. Clamping the protruding electrode against the top,
Injecting resin into a cavity of the mold on which the substrate is placed, and forming a sealing resin for sealing the main surface side of the substrate;
Forming a recess on the surface of the sealing resin and exposing the upper portion of the protruding electrode from the bottom surface of the recess;
A semiconductor device manufacturing method for manufacturing a semiconductor device in which an upper portion of the protruding electrode is exposed from the surface of the sealing resin,
The upper surface of the protruding electrode exposed from the surface of the sealing resin is planarized with respect to the surface of the sealing resin by the inner surface of the cavity of the mold ,
A method of manufacturing a semiconductor device , further comprising forming a recess in at least a part of the upper portion of the protruding electrode exposed from the recess of the sealing resin . 前記封止樹脂の表面から露出する前記突起電極の上部の少なくとも一部に凹部を形成する工程をさらに具備することを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a recess in at least a part of the upper portion of the protruding electrode exposed from the surface of the sealing resin. 基板の主面の素子搭載領域の外部に突起電極を形成する工程と、
前記素子搭載領域に半導体素子を搭載して、前記基板と前記半導体素子を電気的に接続する工程と、
主面上に前記突起電極と前記半導体素子が配置され、前記半導体素子に電気的に接続された前記基板を、金型のキャビティに載置し、前記金型のキャビティの内面を前記突起電極の上部に押し付けて前記突起電極をクランプする工程と、
前記基板が載置された前記金型のキャビティ内に樹脂を注入し、前記基板の主面側を封止する封止樹脂を形成する工程と、
を具備し、前記封止樹脂の表面から前記突起電極の上部が露出する半導体装置を製造する半導体装置の製造方法であって、
前記金型のキャビティの内面には凸部が設けられており、前記凸部により、前記封止樹脂の表面から露出する前記突起電極の上部の少なくとも一部に凹部を形成し、かつ、前記凸部により前記突起電極の凹部の内壁の少なくとも一部に先細りのテーパー形状、円弧形状あるいは段差形状を持たせる
ことを特徴とする半導体装置の製造方法。 Forming a protruding electrode outside the element mounting region on the main surface of the substrate;
Mounting a semiconductor element in the element mounting region and electrically connecting the substrate and the semiconductor element;
The protruding electrode and the semiconductor element are disposed on a main surface, and the substrate electrically connected to the semiconductor element is placed on a cavity of a mold, and the inner surface of the cavity of the mold is placed on the protruding electrode. Clamping the protruding electrode against the top,
Injecting resin into a cavity of the mold on which the substrate is placed, and forming a sealing resin for sealing the main surface side of the substrate;
A semiconductor device manufacturing method for manufacturing a semiconductor device in which an upper portion of the protruding electrode is exposed from the surface of the sealing resin,
A convex portion is provided on the inner surface of the cavity of the mold, and the convex portion forms a concave portion in at least a part of the upper portion of the protruding electrode exposed from the surface of the sealing resin. the tapering of the tapered shape at least a part of the inner wall of the recess of the protruding electrode, method of manufacturing a semi-conductor device you wherein Rukoto to have a circular arc shape or stepped shape by parts. 基板の主面の素子搭載領域の外部に突起電極を形成する工程と、
前記素子搭載領域に半導体素子を搭載して、前記基板と前記半導体素子を電気的に接続する工程と、
主面上に前記突起電極と前記半導体素子が配置され、前記半導体素子に電気的に接続された前記基板を、金型のキャビティに載置し、前記金型のキャビティの内面を前記突起電極の上部に押し付けて前記突起電極をクランプする工程と、
前記基板が載置された前記金型のキャビティ内に樹脂を注入し、前記基板の主面側を封止する封止樹脂を形成する工程と、
を具備し、前記封止樹脂の表面から前記突起電極の上部が露出する半導体装置を製造する半導体装置の製造方法であって、
前記金型のキャビティの内面には凸部が設けられており、前記凸部により前記封止樹脂の表面に凹部を形成し、その凹部の底面から前記突起電極の上部を露出させ、かつ、前記凸部により前記封止樹脂の凹部の内壁の少なくとも一部に先細りのテーパー形状、円弧形状あるいは段差形状を持たせることを特徴とする半導体装置の製造方法。 Forming a protruding electrode outside the element mounting region on the main surface of the substrate;
Mounting a semiconductor element in the element mounting region and electrically connecting the substrate and the semiconductor element;
The protruding electrode and the semiconductor element are disposed on a main surface, and the substrate electrically connected to the semiconductor element is placed on a cavity of a mold, and the inner surface of the cavity of the mold is placed on the protruding electrode. Clamping the protruding electrode against the top,
Injecting resin into a cavity of the mold on which the substrate is placed, and forming a sealing resin for sealing the main surface side of the substrate;
A semiconductor device manufacturing method for manufacturing a semiconductor device in which an upper portion of the protruding electrode is exposed from the surface of the sealing resin,
A convex portion is provided on the inner surface of the cavity of the mold, the concave portion is formed on the surface of the sealing resin by the convex portion, the upper portion of the protruding electrode is exposed from the bottom surface of the concave portion, and tapered shape tapered at least in a part of the inner wall of the recess of the sealing resin by the convex portion, a manufacturing method of a semi-conductor device you wherein Rukoto to have a circular arc shape or stepped shape. 基板の主面の素子搭載領域の外部に突起電極を形成する工程と、
前記素子搭載領域に半導体素子を搭載して、前記基板と前記半導体素子を電気的に接続する工程と、
主面上に前記突起電極と前記半導体素子が配置され、前記半導体素子に電気的に接続された前記基板を、金型のキャビティに載置し、前記金型のキャビティの内面を前記突起電極の上部に押し付けて前記突起電極をクランプする工程と、
前記基板が載置された前記金型のキャビティ内に樹脂を注入し、前記基板の主面側を封止する封止樹脂を形成する工程と、
を具備し、前記封止樹脂の表面から前記突起電極の上部が露出する半導体装置を製造する半導体装置の製造方法であって、
前記金型のキャビティの内面には凸部が設けられており、前記凸部により前記封止樹脂の表面に凹部を形成し、その凹部の底面から前記突起電極の上部を露出させ、かつ、前記凸部により、さらに前記突起電極の上部の少なくとも一部に凹部を形成することを特徴とする半導体装置の製造方法。 Forming a protruding electrode outside the element mounting region on the main surface of the substrate;
Mounting a semiconductor element in the element mounting region and electrically connecting the substrate and the semiconductor element;
The protruding electrode and the semiconductor element are disposed on a main surface, and the substrate electrically connected to the semiconductor element is placed on a cavity of a mold, and the inner surface of the cavity of the mold is placed on the protruding electrode. Clamping the protruding electrode against the top,
Injecting resin into a cavity of the mold on which the substrate is placed, and forming a sealing resin for sealing the main surface side of the substrate;
A semiconductor device manufacturing method for manufacturing a semiconductor device in which an upper portion of the protruding electrode is exposed from the surface of the sealing resin,
The inner surface of the mold cavity has a convex portion is provided, a recess in the surface of the front Kifutome resin Ri by the convex portion, to expose the upper portion of the projecting electrode from the bottom surface of the recess, In addition , a method of manufacturing a semiconductor device , wherein a concave portion is further formed in at least a part of the upper portion of the protruding electrode by the convex portion . 前記凸部により前記突起電極の凹部の内壁の少なくとも一部に先細りのテーパー形状、円弧形状あるいは段差形状を持たせることを特徴とする請求項５記載の半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 5, wherein at least a part of the inner wall of the concave portion of the protruding electrode is provided with a tapered shape, an arc shape, or a step shape by the convex portion. 前記封止樹脂を形成する際の温度を、前記突起電極の融点よりも低い温度にすることを特徴とする請求項１ないし６のいずれかに記載の半導体装置の製造方法。 Wherein the temperature for forming the sealing resin, a method of manufacturing a semiconductor device according to any one of claims 1 to 6, the to Rukoto wherein a temperature lower than the melting point of the projection electrode. 前記突起電極を、前記封止樹脂を形成する際の温度よりも高い融点を持つ材料で形成することを特徴とする請求項１ないし６のいずれかに記載の半導体装置の製造方法。 Method for producing the bump electrodes, the semiconductor device according to any one of claims 1, characterized that you formed of a material having a melting point higher than the temperature for forming the sealing resin 6. 基板と、前記基板の主面上に搭載され前記基板に電気的に接続された半導体素子と、前記基板の主面上に形成された突起電極と、前記基板の主面側を封止する封止樹脂と、を備えた半導体装置であって、
前記突起電極は、その上部が前記封止樹脂の表面から露出しており、かつその露出した上部の少なくとも一部に凹部を有し、
前記突起電極の凹部の内壁の少なくとも一部に先細りのテーパー形状、円弧形状あるいは段差形状を有する
ことを特徴とする半導体装置。 A substrate, a semiconductor element mounted on the main surface of the substrate and electrically connected to the substrate, a protruding electrode formed on the main surface of the substrate, and a seal for sealing the main surface side of the substrate; A semiconductor device comprising a stop resin,
The protruding electrode has an upper portion exposed from the surface of the sealing resin, and has a recess in at least a part of the exposed upper portion,
At least a portion tapering tapered, semi-conductor equipment characterized in that have a circular arc shape or stepped shape of the inner wall of the recess of the protruding electrode. 基板と、前記基板の主面上に搭載され前記基板に電気的に接続された半導体素子と、前記基板の主面上に形成された突起電極と、前記基板の主面側を封止する封止樹脂と、を備えた半導体装置であって、
前記突起電極は、その上部が、前記封止樹脂の表面に形成されている凹部の底面から露出しており、
前記封止樹脂の凹部の内壁の少なくとも一部に先細りのテーパー形状、円弧形状あるいは段差形状を有する
ことを特徴とする半導体装置。 A substrate, a semiconductor element mounted on the main surface of the substrate and electrically connected to the substrate, a protruding electrode formed on the main surface of the substrate, and a seal for sealing the main surface side of the substrate; A semiconductor device comprising a stop resin,
The protruding electrode has an upper portion exposed from the bottom surface of the recess formed on the surface of the sealing resin,
At least a portion tapering tapered, semi-conductor equipment characterized Rukoto to have a circular arc shape or stepped shape of the inner wall of the recess of the sealing resin. 基板と、前記基板の主面上に搭載され前記基板に電気的に接続された半導体素子と、前記基板の主面上に形成された突起電極と、前記基板の主面側を封止する封止樹脂と、を備えた半導体装置であって、
前記突起電極は、その上部が、前記封止樹脂の表面に形成されている凹部の底面から露出しており、
前記突起電極は、前記封止樹脂の凹部の底面から露出する上部の少なくとも一部に凹部を有する
ことを特徴とする半導体装置。 A substrate, a semiconductor element mounted on the main surface of the substrate and electrically connected to the substrate, a protruding electrode formed on the main surface of the substrate, and a seal for sealing the main surface side of the substrate; A semiconductor device comprising a stop resin,
The protruding electrode has an upper portion exposed from the bottom surface of the recess formed on the surface of the sealing resin,
The protrusion electrodes, the semi-conductor equipment you characterized Rukoto which having a recess in at least part of an upper exposed from the bottom surface of the recess of the sealing resin. 前記突起電極の凹部の内壁の少なくとも一部に先細りのテーパー形状、円弧形状あるいは段差形状を有することを特徴とする請求項１１記載の半導体装置。 The semiconductor equipment according to claim 11, at least a portion tapering tapered, characterized Rukoto to have a circular arc shape or stepped shape of the inner wall of the recess of the protruding electrode.
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