JP2005005358A - Connection structure between laminated substrates of semiconductor module - Google Patents

Connection structure between laminated substrates of semiconductor module Download PDF

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Publication number
JP2005005358A
JP2005005358A JP2003164809A JP2003164809A JP2005005358A JP 2005005358 A JP2005005358 A JP 2005005358A JP 2003164809 A JP2003164809 A JP 2003164809A JP 2003164809 A JP2003164809 A JP 2003164809A JP 2005005358 A JP2005005358 A JP 2005005358A
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Japan
Prior art keywords
solder
melting point
solder layer
connection structure
solder bump
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JP2003164809A
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Japanese (ja)
Inventor
Masaaki Ozaki
正昭 尾崎
Koki Kitaoka
幸喜 北岡
Akira Yoshida
陽 吉田
Naoki Sakota
直樹 迫田
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Sharp Corp
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Sharp Corp
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Priority to JP2003164809A priority Critical patent/JP2005005358A/en
Publication of JP2005005358A publication Critical patent/JP2005005358A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an upper solder bump from falling at the time of performing reflow soldering. <P>SOLUTION: In the peripheral sections of the front and rear surfaces of two intermediate substrates 24 mounted with semiconductor chips 21 on both front and rear surfaces, interlayer connecting electrode pads 22a and 22b are formed. On the electrode pads 22a, solder bumps 25 covering the peripheries of resin-based balls 29 with solder layers 30 are formed and, on the electrode pads 22b, solder bumps 26 covering the peripheries of metallic balls 27 with solder layers 28 having higher melting points that the solder layers 30 have are formed. Then the solder bumps 25 and 26 of the intermediate substrates 24 are placed upon another with the solder bump 25 having the low-melting point solder layer 30 on the bottom side and melt-connected to each other under a temperature condition where the lower solder layer 30 melts and the upper solder layer 28 does not melt. Since the solder layer 28 of the upper solder bump 26 is melted, the falling of the solder bump 26 from the interlayer connecting electrode pad 22b can be prevented. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
この発明は、複数の半導体回路素子が高密度に表面実装された複数の中間基板を積層して成る半導体モジュールの積層基板間接続構造に関する。
【０００２】
【従来の技術】
近年における電子機器の小型化や薄型化の要求に応えるために、半導体集積回路の高密度実装方法として、複数の半導体チップやチップ部品を中間基板に実装して成るモジュール基板を複数段積層することが行われている。一般に、このような積層体モジュールの形成方法として、互いに対向している２つのモジュール基板を半田ボールによって電気的に接続する方法が知られている。
【０００３】
以下、従来におけるこの種の半導体モジュールの積層基板間接続構造について図３に従って説明する。図３において、１は半導体チップ、２は中間基板、３は層間接続用の電極パッド、４は半田バンプである。
【０００４】
上記半導体チップ１は中間基板２の片面にフリップチップ実装され、半導体チップ１側の電極（図示せず）と中間基板２側の電極（図示せず）とが電気的に接続されている。さらに、中間基板２における周辺部の表裏両面に層間接続用の電極パッド３，３が設けられ、中間基板２に形成されたスルーホール（図示せず）を介して接続されて、モジュール基板５が形成されている。そして、各モジュール基板５，５は、モジュール基板５の厚さ方向に積層され、各モジュール基板５，５の層間接続用の電極パッド３，３を互いに対向させると共に、両電極パッド３，３の間に半田バンプ４を介在させることによって両モジュール基板５，５間を電気的に接続している。
【０００５】
同様にして、３個以上のモジュール基板５を積層して成る複数段の半導体モジュールを形成することも可能である。
【０００６】
上記従来の半導体モジュールの積層基板間接続構造においては、単機能デバイスを構成する場合が多く、信号数および端子数が少ないために、隣接する電極パッド３，３間のピッチ寸法を大きく設定して、各半田バンプ４として比較的多量の半田を用いることができる。したがって、層間接続端子としての電極パッド３間の高さを十分に高くすることができ、製造時における被接続電極パッド３，３間のオープン不良や隣接電極パッド３，３間のショート不良を生じることは少ない。
【０００７】
ところが、近年の小型化・高機能化に伴って中間基板２に実装される回路素子の数および個々の回路素子の電極数が増加し、中間基板２の周辺に設けられた層間接続用の電極パッド３の数も増えるの対して、電極パッド３数の増加に伴う中間基板２の面積増大を抑制するために、電極パッド３の面積および隣接電極パッド３，３間ピッチが小さくなる傾向にある。そのために、積層された２枚の中間基板２，２間において、互いに対向する電極パッド３，３を接続する半田バンプの高さが低くなり、半導体チップ１の厚み以上の十分な実装高さを積層中間基板２，２間に確保することができなくなる。さらに、上記中間基板の表裏両面に回路素子を実装したモジュール基板を積層して層間接続を行う場合には、実装高さを確保することがより一層困難になる。
【０００８】
このような問題を解決するために、金属コアを内装する半田バンプを垂直方向に２段重ねした部品の接続構造が提案されている（例えば、特許文献１参照）。この部品の接続構造は、図４に示すような構造を有している。すなわち、図４において、１１はマルチチップモジュール、１２は接続構造、１３はマザーボード、１４はパッケージ基板、１５は電子部品、１６ａはパッケージ基板１４上に配置された電極パッド、１６ｂはマザーボード１３上に配置された電極パッド、１７は半田層、１８ａおよび１８ｂは金属ボールである。
【０００９】
上記接続構造１２は、上記パッケージ基板１４上の電極パッド１６ａとマザーボード１３上の電極パッド１６ｂとの間に垂直方向に重ね合わせて配置された２個の金属ボール１８ａ，１８ｂを、低融点の半田層１７で覆って構成されている。こうして、上側に位置するパッケージ基板１４上の電極パッド１６ａと下側に位置するマザーボード１３上の電極パッド１６ｂとの間を、機械的・電気的に接続している。
【００１０】
【特許文献１】
特開平８‐１７９７２号公報
【００１１】
【発明が解決しようとする課題】
しかしながら、上記従来の特許文献１に開示された部品の接続構造には、以下のような問題がある。すなわち、図４に示す接続構造１２は、電極パッド１６ａに形成された金属ボール１８ａを内装する上段の半田バンプと、電極パッド１６ｂに形成された金属ボール１８ｂを内装する下段の半田バンプとを、互いに対向させてリフロー処理を行って両半田バンプの半田層１７，１７を再溶融させることによって形成される。
【００１２】
ところが、上記半田層１７を再溶融させた場合に、複数の接続構造１２において、総ての金属ボール１８ａ，１８ｂが垂直方向に一直線上に並ぶとは限らない。そして、垂直方向に一直線上に並ばない金属ボール１８ａ，１８ｂが存在する場合には、パッケージ基板１４に荷重を掛けると、溶融した半田層１７の中において上記垂直方向に一直線上に並んでいない金属ボール１８ａ，１８ｂ相互の位置関係が大きく崩れ、上段に位置すべき金属ボール１８ａが電極パッド１６ａから脱落する場合が生ずる。
【００１３】
その場合には、被接続電極パッド１６ａ，１６ｂ間のオープン不良や隣接電極パッド間のショート不良を引き起こす要因となる。
【００１４】
そこで、この発明の目的は、垂直方向に重ね合わせた半田バンプをリフローして積層基板間を接続するに際して、リフロー時に上段の半田バンプが脱落することを防止できる半導体モジュールの積層基板間接続構造を提供することにある。
【００１５】
【課題を解決するための手段】
上記目的を達成するため、この発明は、半導体回路素子が表面実装されると共に表面に半田バンプが形成された２以上の基板を，互いの半田バンプを略垂直方向に重ね合わせて融着することによって，積層してなる半導体モジュールの積層基板間接続構造であって、上記半田バンプは核とこの核よりも低融点の半田層とで構成されており、上記融着の際に上側に位置する半田バンプを構成する半田層の融点が下側に位置する半田バンプを構成する半田層の融点よりも高くなっている。
【００１６】
上記構成によれば、上記２以上の基板における互いの半田バンプを略垂直方向に重ね合わせて融着して、上記２以上の基板が積層されてなる半導体モジュールを形成する際に、上記融着の温度を、下側に位置する半田層の融点以上で且つ上側に位置する半田層の融点未満とすることによって、上記融着の際に、上側に位置する半田バンプを構成する半田層が溶融して上側の半田バンプが脱落することが防止される。
【００１７】
こうして、被接続電極パッド間のオープン不良や隣接電極パッド間のショート不良の発生が防止される。さらに、上記層間接続後において上側の半田バンプの核と下側の半田バンプの核とを垂直方向に一直線上に重ねることができ、十分な実装高さ（積層された上記基板の間隔）が確保される。
【００１８】
また、１実施例の半導体モジュールの積層基板間接続構造では、上記融着の際に上側に位置する半田バンプを構成する半田層の融点は２２０℃以上である。
【００１９】
この実施例によれば、上側に位置する半田バンプを構成する半田層の融点を２２０℃以上と高めに設定しているので、下側に位置する半田バンプを構成する半田層の融点の選択範囲が広められる。さらに、下側に位置する半田バンプを構成する半田層の融点を低めに設定すれば両半田層の融点差が大きくなり、上記２以上の基板における互いの半田バンプを重ね合わせて融着する際におけるリフロー炉内の温度分布の影響が排除される。こうして、上側に位置する半田層を溶融させることなく、下側に位置する半田層のみが確実に溶融される。
【００２０】
また、１実施例の半導体モジュールの積層基板間接続構造では、上記融着の際に下側に位置する半田バンプを構成する半田層の融点は１８５℃以下である。
【００２１】
この実施例によれば、下側に位置する半田バンプを構成する半田層の融点を１８５℃以下と低めに設定しているので、上側に位置する半田バンプを構成する半田層の融点の選択範囲が広められる。さらに、上側に位置する半田バンプを構成する半田層の融点を高めに設定すれば両半田層の融点差が大きくなり、上記リフロー炉内の温度分布の影響が排除されて下側に位置する半田層のみが確実に溶融される。
【００２２】
また、１実施例の半導体モジュールの積層基板間接続構造では、上記融着の際に上側に位置する半田バンプを構成する半田層の融点は２２１℃であり、上記核は銅およびニッケルの何れか一方でなる金属ボールであり、上記融着の際に下側に位置する半田バンプを構成する半田層の融点は１８３℃であり、上記核はジビニルベンゼン架橋共重合体でなる樹脂系ボールである。
【００２３】
この実施例によれば、上側・下側に位置する両半田バンプ共、核の融点は半田層の融点よりも高い。したがって、上記基板の表面に両半田バンプを形成する際に半田層を溶融しても核に対しては熱的影響が無く、上記融着の際に実装高さを確保すると言う上記核の機能が消滅することはない。
【００２４】
【発明の実施の形態】
以下、この発明を図示の実施の形態により詳細に説明する。図１は、本実施の形態の半導体モジュールの積層基板間接続構造を示す断面拡大図である。図１において、２１は半導体チップ、２２ａ，２２ｂは層間接続用電極パッド、２３はソルダーレジスト、２４は中間基板、２５，２６は半田バンプである。
【００２５】
上記中間基板２４の表裏両面には、複数の半導体チップ２１がフリップチップ実装されている。その際に、半導体チップ２１の電極（図示せず）と中間基板２４の電極（図示せず）とが電気的に接続されると共に、半導体チップ２１と中間基板２４との隙間にはアンダーフィル材（図示せず）が注入されて半導体チップ２１が中間基板２４に強固に固着されている。また、中間基板２４の表裏両面における周辺部には層間接続用電極パッド２２ａ，２２ｂが形成されて、配線パターン（図示せず）によって同一中間基板２４に実装されている半導体チップ２１と電気的に接続されている。
【００２６】
さらに、上記中間基板２４の上面に設けられた層間接続用電極パッド２２ａ上には半田バンプ２５が形成されており、中間基板２４の下面に設けられた層間接続用電極パッド２２ｂ上には半田バンプ２６が形成されている。
【００２７】
上述のように構成された２つの中間基板２４，２４は、下側の中間基板２４における層間接続用電極パッド２２ａと上側の中間基板２４における層間接続用電極パッド２２ｂとが、互いに対向するように位置合わせして積層されている。そして、層間接続は、層間接続用電極パッド２２ｂ上に形成された半田バンプ２６と層間接続用電極パッド２２ａ上に形成された半田バンプ２５とを垂直方向に重ね合わせて接続することによって行われている。
【００２８】
上記半田バンプ２６は、核として金属ボール２７を有しており、その周りを半田層２８で被覆して構成されている。尚、金属ボール２７として、半田層２８よりも融点が高くて半田に対して濡れ性が良好な銅またはニッケルを用いている。これに対して、半田バンプ２５は、核として樹脂系ボール２９を有しており、その周りを半田層３０で被覆して構成されている。尚、樹脂系ボール２９として、半田層３０の融点であっても高耐熱性を有する材料（例えば、ジビニルベンゼン架橋共重合体）を用いている。尚、半田層２８，３０の材料としては、半田層２８の融点が半田層３０の融点よりも高くなるような材料が用いられている。その場合、リフロー炉内の温度分布の影響を考慮して、半田層２８と半田層３０との融点の差が大きい材料を選択することが好ましい。
【００２９】
以下、上記構成を有する半導体モジュールの積層基板間接続構造の形成方法について説明する。図２は、上記半導体モジュールの積層基板間接続構造の形成方法における一例を示す工程図である。先ず、複数の半導体チップ２１がフリップチップ実装された中間基板２４を用意する。そして、図２（ａ）に示すように、基板積層時に下側になる面を上側に向けて、層間接続用電極パッド２２ｂにフラックスを塗布して半田ボール２６’を搭載する。この半田ボール２６’は、核に銅またはニッケルから成る金属ボール２７を有し、その周りを融点が２２１℃の半田層２８で被覆して構成されている。
【００３０】
次に、この状態において、融点が２２１℃である半田層２８が溶融する条件でリフロー処理を行う。そうすると、金属ボール２７の周りを球状に被覆していた半田層２８が溶融して下側に向って流れ出し、金属ボール２７と層間接続用電極パッド２２ｂとの間を埋める。こうして、層間接続用電極パッド２２ｂ上に電気的・機械的に接続された半田バンプ２６（図１参照）が形成されるのである。その際に、半田濡れ性の悪いソルダーレジスト２３が層間接続用電極パッド２２ｂの周辺に設けられているので、流れ出した半田は層間接続用電極パッド２２ｂによってせき止められる。したがって、溶融した半田が隣接した層間接続用電極パッドまで広がってショートすることが防止される。
【００３１】
次に、図２（ｂ）に示すように、上記層間接続用電極パッド２２ａが上面になるように中間基板２４が裏返される。そして、層間接続用電極パッド２２ａにフラックスを塗布して半田ボール２５’を搭載する。この半田ボール２５’は、核に樹脂系ボール２９を有し、その周りを融点が１８３℃の半田層３０で被覆して構成されている。この状態で、半田層３０が溶融して半田バンプ２６の半田層２８が溶融しない温度、つまり１８３℃以上で且つ２２１℃未満の温度条件で、リフロー処理を行うことによって、層間接続用電極パッド２２ａ上に電気的・機械的に接続された半田バンプ２５（図１参照）が形成される。
【００３２】
この場合にも、上記半田バンプ２６の場合と同様に、ソルダーレジスト２３の効果によって、溶融した半田が隣接した層間接続用電極パッドまで広がってショートすることが防止される。また、この場合のリフロー条件は、半田バンプ２６の半田層２８における融点以下に設定されている。したがって、半田バンプ２６の半田層２８が再溶融して、半田バンプ２６が層間接続用電極パッド２２ｂから脱落することを防止できる。
【００３３】
次に、図２（ｃ）に示すように、図２（ｂ）に示すごとく表裏に半田バンプ２５，２６が形成された状態の２枚の中間基板２４を半田バンプ２６側を下にして基板の厚さ方向に積層し、下側に位置する中間基板２４の層間接続用電極パッド２２ａと上側に位置する中間基板２４の層間接続用電極パッド２２ｂとが重なり合うように位置合せを行い、半田バンプ２６と半田バンプ２５とが重なって垂直方向に一直線上に並ぶようにする。この場合における位置合せは、例えば、各中間基板２４に設けた貫通穴に位置決めピンを挿通することによって行うようにすればよい。尚、重なっている半田バンプ２６と半田バンプ２５との間に、フラックスを塗布しても構わない。
【００３４】
次に、上記半田バンプ２５の半田層３０が再溶融する一方、半田バンプ２６の半田層２８が再溶融しない温度、つまり１８３℃以上で且つ２２１℃未満の温度条件で、リフロー処理を行うことによって、半田層３０が再溶融される。その際における上記リフロー条件は、半田バンプ２６の半田層２８の融点未満に設定されている。したがって、半田バンプ２６の半田層２８が再溶融して、半田バンプ２６が層間接続用電極パッド２２ｂから脱落することを防止できる。
【００３５】
そうした後、上記再溶融した半田バンプ２５の半田層３０が、表面張力と半田バンプ２６の半田層２８への濡れ性とによって、図１に示すように半田層２８の表面に沿って上昇して行き、半田バンプ２６と半田バンプ２５とが機械的・電気的に接続されるのである。
【００３６】
以上のごとく、本実施の形態においては、表裏両面に複数の半導体チップ２１がフリップチップ実装された中間基板２４の表裏両面の周辺部に、層間接続用電極パッド２２ａ，２２ｂを形成する。そして、層間接続用電極パッド２２ａ上には樹脂系ボール２９の周囲を半田層３０で被覆した半田バンプ２５を形成し、層間接続用電極パッド２２ｂ上には金属ボール２７の周囲を融点が半田層３０よりも高い半田層２８で被覆した半田バンプ２６を形成する。
【００３７】
そして、一方の中間基板２４の半田バンプ２５と他方の中間基板２４の半田バンプ２６とを重ねて位置合せを行い、リフロー処理によって半田バンプ２５と半田バンプ２６とを溶融接続して、一方の中間基板２４の層間接続用電極パッド２２ａと他方の中間基板２４の層間接続用電極パッド２２ｂとを機械的・電気的に接続する。
【００３８】
その際に、融点が低い半田層３０を有する半田バンプ２５を下側とし、リフロー温度条件を下側の半田層３０が溶融する一方上側の半田層２８が溶融しない温度としている。したがって、半田バンプ２６の半田層２８が溶融して、上側の半田バンプ２６が層間接続用電極パッド２２ｂから脱落することを防止できる。
【００３９】
すなわち、この実施の形態によれば、被接続電極パッド２２ａ，２２ｂ間のオープン不良や隣接電極パッド間のショート不良の発生が効果的に防止される。さらに、半田バンプ２５内には樹脂系ボール２９を設ける一方、半田バンプ２６内には金属ボール２７を設け、層間接続後において金属ボール２７と樹脂系ボール２９とを垂直方向に一直線上に重ねることができる。したがって、表裏両面に複数の半導体チップ２１が実装された中間基板２４を積層して層間接続する場合であっても、比較的小さい半田バンプを用いて十分な実装高さを確保することができる。
【００４０】
以上のごとく、この実施の形態によれば、電極パッドの狭ピッチ化に適し、接続の信頼性に優れた半導体モジュールの積層基板間接続構造を提供することができるのである。
【００４１】
尚、上記実施の形態においては、上記半田バンプ２５には樹脂系ボール２９を内装し、半田バンプ２６には金属ボール２７を内装している。しかしながら、この発明はこれに限定されるものではなく、両半田バンプ２５，２６に内装するボール状の核は、金属ボールおよび樹脂ボールの何れであっても差し支えない。
【００４２】
また、上記実施の形態においては、上記中間基板２４の表裏両面に半導体チップ２１を実装しているが、表面および裏面の何れか一方のみに形成しても一向に差し支えない。また、上記実施の形態においては、上記中間基板２４の表裏両面に層間接続用電極パッド２２ａ，２２ｂを形成しているが、２枚の中間基板２４のみを積層する場合には、片面にのみ層間接続用電極パッド２２を形成しても構わない。
【００４３】
【発明の効果】
以上より明らかなように、この発明の半導体モジュールの積層基板間接続構造は、表面に半田バンプが形成された２以上の基板を、互いの半田バンプを略垂直方向に重ね合わせて融着することによって積層して形成された半導体モジュールにおいて、上記半田バンプを核とこの核よりも低融点の半田層とで構成すると共に、上記融着の際に上側に位置する半田バンプを構成する半田層の融点を下側に位置する半田バンプを構成する半田層の融点よりも高くしたので、上記融着の温度を、下側に位置する半田層の融点以上で且つ上側に位置する半田層の融点未満とすることによって、上記融着の際に、上側に位置する半田バンプを構成する半田層が溶融して上側の半田バンプが脱落することを防止できる。
【００４４】
したがって、被接続電極パッド間のオープン不良や隣接電極パッド間のショート不良の発生を防止することができる。また、上記層間接続後において上側の半田バンプの核と下側の半田バンプの核とを垂直方向に一直線上に重ねることができ、半導体回路素子が上記基板の表裏に実装されていても十分な実装高さ（積層された上記基板の間隔）を確保することができる。
【００４５】
すなわち、この発明によれば、電極パッドの狭ピッチ化に適し、接続の信頼性に優れた半導体モジュールの積層基板間接続構造を提供することができるのである。
【図面の簡単な説明】
【図１】この発明の半導体モジュールの積層基板間接続構造における断面図である。
【図２】図１に示す積層基板間接続構造の形成方法を示す工程図である。
【図３】従来の半導体モジュールの積層基板間接続構造における断面図である。
【図４】図３とは異なる従来の半導体モジュールの積層基板間接続構造における断面図である。
【符号の説明】
２１…半導体チップ、
２２ａ，２２ｂ…層間接続用電極パッド、
２３…ソルダーレジスト、
２４…中間基板、
２５，２６…半田バンプ、
２７…金属ボール、
２８，３０…半田層、
２９…樹脂系ボール。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a connection structure between stacked substrates of a semiconductor module formed by stacking a plurality of intermediate substrates on which a plurality of semiconductor circuit elements are surface-mounted at high density.
[0002]
[Prior art]
In order to meet the recent demand for miniaturization and thinning of electronic devices, as a high-density mounting method for semiconductor integrated circuits, a multi-layer stack of module substrates in which a plurality of semiconductor chips and chip components are mounted on an intermediate substrate is performed. Has been done. In general, as a method of forming such a laminated module, a method of electrically connecting two module substrates facing each other with solder balls is known.
[0003]
Hereinafter, a conventional connection structure between stacked substrates of this type of semiconductor module will be described with reference to FIG. In FIG. 3, 1 is a semiconductor chip, 2 is an intermediate substrate, 3 is an electrode pad for interlayer connection, and 4 is a solder bump.
[0004]
The semiconductor chip 1 is flip-chip mounted on one surface of the intermediate substrate 2, and an electrode (not shown) on the semiconductor chip 1 side and an electrode (not shown) on the intermediate substrate 2 side are electrically connected. Furthermore, electrode pads 3 and 3 for interlayer connection are provided on both front and back surfaces of the peripheral portion of the intermediate substrate 2, and are connected via through holes (not shown) formed in the intermediate substrate 2, so that the module substrate 5 is Is formed. The module substrates 5 and 5 are stacked in the thickness direction of the module substrate 5, and the electrode pads 3 and 3 for interlayer connection of the module substrates 5 and 5 are opposed to each other. The module substrates 5 and 5 are electrically connected by interposing the solder bumps 4 therebetween.
[0005]
Similarly, it is possible to form a multi-stage semiconductor module in which three or more module substrates 5 are stacked.
[0006]
In the connection structure between the stacked substrates of the conventional semiconductor module described above, a single-function device is often configured, and the number of signals and the number of terminals are small. Therefore, the pitch dimension between adjacent electrode pads 3 and 3 is set large. A relatively large amount of solder can be used as each solder bump 4. Therefore, the height between the electrode pads 3 as the interlayer connection terminals can be sufficiently increased, and an open defect between the connected electrode pads 3 and 3 and a short defect between the adjacent electrode pads 3 and 3 at the time of manufacture occur. There are few things.
[0007]
However, the number of circuit elements mounted on the intermediate substrate 2 and the number of electrodes of the individual circuit elements have increased with the recent reduction in size and functionality, and the interlayer connection electrodes provided around the intermediate substrate 2 In contrast to the increase in the number of pads 3, the area of the electrode pad 3 and the pitch between the adjacent electrode pads 3 and 3 tend to be reduced in order to suppress the increase in the area of the intermediate substrate 2 with the increase in the number of electrode pads 3. . For this reason, the height of solder bumps connecting the electrode pads 3 and 3 facing each other between the two intermediate substrates 2 and 2 stacked is reduced, and a sufficient mounting height equal to or greater than the thickness of the semiconductor chip 1 is achieved. It becomes impossible to ensure between the laminated intermediate substrates 2 and 2. Furthermore, it is more difficult to secure the mounting height when stacking module substrates on which circuit elements are mounted on both the front and back surfaces of the intermediate substrate to perform interlayer connection.
[0008]
In order to solve such a problem, there has been proposed a connection structure for components in which solder bumps in a metal core are stacked in two stages in the vertical direction (see, for example, Patent Document 1). This component connection structure has a structure as shown in FIG. 4, 11 is a multi-chip module, 12 is a connection structure, 13 is a motherboard, 14 is a package substrate, 15 is an electronic component, 16a is an electrode pad disposed on the package substrate 14, and 16b is on the motherboard 13. The arranged electrode pads, 17 is a solder layer, and 18a and 18b are metal balls.
[0009]
In the connection structure 12, two metal balls 18a and 18b arranged in a vertical direction between the electrode pads 16a on the package substrate 14 and the electrode pads 16b on the motherboard 13 are soldered with a low melting point. It is configured to be covered with a layer 17. Thus, the electrode pads 16a on the package substrate 14 located on the upper side and the electrode pads 16b on the mother board 13 located on the lower side are mechanically and electrically connected.
[0010]
[Patent Document 1]
JP-A-8-17972 [0011]
[Problems to be solved by the invention]
However, the conventional component connection structure disclosed in Patent Document 1 has the following problems. That is, the connection structure 12 shown in FIG. 4 includes an upper solder bump that houses the metal ball 18a formed on the electrode pad 16a and a lower solder bump that houses the metal ball 18b formed on the electrode pad 16b. The solder layers 17 and 17 of both solder bumps are remelted by reflowing them facing each other.
[0012]
However, when the solder layer 17 is remelted, not all of the metal balls 18a and 18b are aligned in the vertical direction in the plurality of connection structures 12. When there are metal balls 18a and 18b that are not aligned in the vertical direction, when a load is applied to the package substrate 14, the metal that is not aligned in the vertical direction in the molten solder layer 17 is applied. The positional relationship between the balls 18a and 18b is greatly broken, and the metal ball 18a to be positioned on the upper stage may drop off from the electrode pad 16a.
[0013]
In that case, it becomes a factor which causes the open defect between to-be-connected electrode pads 16a and 16b and the short defect between adjacent electrode pads.
[0014]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an inter-laminar substrate connection structure of a semiconductor module that can prevent the upper solder bumps from dropping off during reflow when reflowing solder bumps stacked in the vertical direction to connect the multilayer substrates. It is to provide.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, the present invention fuses two or more substrates on which a semiconductor circuit element is surface-mounted and solder bumps are formed on the surface by superimposing the solder bumps in a substantially vertical direction. In this connection structure, the solder bumps are composed of a core and a solder layer having a melting point lower than that of the core, and are located on the upper side during the fusion. The melting point of the solder layer constituting the solder bump is higher than the melting point of the solder layer constituting the solder bump located on the lower side.
[0016]
According to the above configuration, when the semiconductor bumps formed by stacking the two or more substrates are formed by stacking and welding the solder bumps on the two or more substrates in a substantially vertical direction, the fusion bonding is performed. When the above-mentioned fusion is performed, the solder layer constituting the upper solder bump is melted by setting the temperature of the solder layer to be higher than the melting point of the lower solder layer and lower than the upper melting point of the solder layer. Thus, the upper solder bump is prevented from falling off.
[0017]
In this way, the occurrence of open defects between connected electrode pads and short-circuit defects between adjacent electrode pads can be prevented. Furthermore, the core of the upper solder bump and the core of the lower solder bump can be vertically aligned in a straight line after the interlayer connection, ensuring a sufficient mounting height (interval between the stacked substrates). Is done.
[0018]
In the connection structure between the laminated substrates of the semiconductor module of one embodiment, the melting point of the solder layer constituting the solder bump located on the upper side at the time of the fusion is 220 ° C. or higher.
[0019]
According to this embodiment, since the melting point of the solder layer constituting the solder bump located on the upper side is set to be higher than 220 ° C., the selection range of the melting point of the solder layer constituting the solder bump located on the lower side Is spread. Furthermore, if the melting point of the solder layer constituting the solder bump located on the lower side is set to be low, the difference in melting point between the two solder layers increases, and when the solder bumps on the two or more substrates are overlapped and fused together The influence of the temperature distribution in the reflow furnace is eliminated. Thus, only the lower solder layer is reliably melted without melting the upper solder layer.
[0020]
In the connection structure between the laminated substrates of the semiconductor module of one embodiment, the melting point of the solder layer constituting the solder bump located on the lower side at the time of the fusion is 185 ° C. or less.
[0021]
According to this embodiment, since the melting point of the solder layer constituting the solder bump located on the lower side is set to be lower than 185 ° C., the selection range of the melting point of the solder layer constituting the solder bump located on the upper side Is spread. Furthermore, if the melting point of the solder layer constituting the solder bump located on the upper side is set higher, the difference between the melting points of both solder layers becomes larger, and the influence of the temperature distribution in the reflow furnace is eliminated, and the solder located on the lower side is eliminated. Only the layer is reliably melted.
[0022]
Further, in the connection structure between the stacked substrates of the semiconductor module of one embodiment, the melting point of the solder layer constituting the solder bump located on the upper side at the time of the fusion is 221 ° C., and the nucleus is either copper or nickel One of the metal balls, the melting point of the solder layer constituting the solder bump located on the lower side at the time of the fusion is 183 ° C., and the nucleus is a resin-based ball made of a divinylbenzene crosslinked copolymer. .
[0023]
According to this embodiment, the melting point of the core is higher than the melting point of the solder layer in both the solder bumps located on the upper side and the lower side. Therefore, even if the solder layer is melted when forming both solder bumps on the surface of the substrate, there is no thermal effect on the core, and the function of the core is to secure the mounting height during the fusion. Will never disappear.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 is an enlarged cross-sectional view showing a connection structure between stacked substrates of a semiconductor module according to the present embodiment. In FIG. 1, 21 is a semiconductor chip, 22a and 22b are interlayer connection electrode pads, 23 is a solder resist, 24 is an intermediate substrate, and 25 and 26 are solder bumps.
[0025]
A plurality of semiconductor chips 21 are flip-chip mounted on the front and back surfaces of the intermediate substrate 24. At that time, an electrode (not shown) of the semiconductor chip 21 and an electrode (not shown) of the intermediate substrate 24 are electrically connected, and an underfill material is provided in the gap between the semiconductor chip 21 and the intermediate substrate 24. (Not shown) is injected so that the semiconductor chip 21 is firmly fixed to the intermediate substrate 24. In addition, interlayer connection electrode pads 22a and 22b are formed on the peripheral portions of the front and back surfaces of the intermediate substrate 24, and are electrically connected to the semiconductor chip 21 mounted on the same intermediate substrate 24 by a wiring pattern (not shown). It is connected.
[0026]
Further, solder bumps 25 are formed on the interlayer connection electrode pads 22a provided on the upper surface of the intermediate substrate 24, and solder bumps 25 are formed on the interlayer connection electrode pads 22b provided on the lower surface of the intermediate substrate 24. 26 is formed.
[0027]
The two intermediate substrates 24, 24 configured as described above are arranged so that the interlayer connection electrode pad 22 a in the lower intermediate substrate 24 and the interlayer connection electrode pad 22 b in the upper intermediate substrate 24 face each other. They are aligned and stacked. The interlayer connection is performed by overlapping and connecting the solder bumps 26 formed on the interlayer connection electrode pads 22b and the solder bumps 25 formed on the interlayer connection electrode pads 22a in the vertical direction. Yes.
[0028]
The solder bump 26 has a metal ball 27 as a core, and the periphery thereof is covered with a solder layer 28. As the metal ball 27, copper or nickel having a melting point higher than that of the solder layer 28 and good wettability with respect to the solder is used. On the other hand, the solder bump 25 has a resin ball 29 as a core, and the periphery thereof is covered with a solder layer 30. Note that a material having high heat resistance (for example, divinylbenzene cross-linked copolymer) is used as the resin ball 29 even at the melting point of the solder layer 30. As the material for the solder layers 28 and 30, a material is used in which the melting point of the solder layer 28 is higher than the melting point of the solder layer 30. In that case, it is preferable to select a material having a large difference in melting point between the solder layer 28 and the solder layer 30 in consideration of the influence of the temperature distribution in the reflow furnace.
[0029]
Hereinafter, a method for forming a connection structure between stacked substrates of a semiconductor module having the above configuration will be described. FIG. 2 is a process diagram showing an example in a method for forming a connection structure between stacked substrates of the semiconductor module. First, an intermediate substrate 24 on which a plurality of semiconductor chips 21 are flip-chip mounted is prepared. Then, as shown in FIG. 2A, the solder ball 26 'is mounted by applying flux to the interlayer connection electrode pads 22b with the lower surface facing the upper side when the substrates are laminated. The solder ball 26 ′ has a metal ball 27 made of copper or nickel at the core, and is surrounded by a solder layer 28 having a melting point of 221 ° C.
[0030]
Next, in this state, a reflow process is performed under the condition that the solder layer 28 having a melting point of 221 ° C. is melted. As a result, the solder layer 28 that covers the metal ball 27 in a spherical shape melts and flows downward, filling the space between the metal ball 27 and the interlayer connection electrode pad 22b. Thus, the solder bumps 26 (see FIG. 1) electrically and mechanically connected are formed on the interlayer connection electrode pads 22b. At this time, since the solder resist 23 having poor solder wettability is provided around the interlayer connection electrode pad 22b, the solder that has flowed out is blocked by the interlayer connection electrode pad 22b. Therefore, it is possible to prevent the molten solder from spreading to the adjacent interlayer connection electrode pad and causing a short circuit.
[0031]
Next, as shown in FIG. 2B, the intermediate substrate 24 is turned over so that the interlayer connection electrode pad 22a is on the upper surface. Then, flux is applied to the interlayer connection electrode pads 22a to mount the solder balls 25 '. This solder ball 25 'has a resin-based ball 29 at its core and is covered with a solder layer 30 having a melting point of 183 ° C. In this state, by performing the reflow process at a temperature at which the solder layer 30 is melted and the solder layer 28 of the solder bump 26 is not melted, that is, a temperature condition of 183 ° C. or more and less than 221 ° C., the interlayer connection electrode pad 22a Solder bumps 25 (see FIG. 1) connected electrically and mechanically are formed thereon.
[0032]
Also in this case, as in the case of the solder bump 26, the effect of the solder resist 23 prevents the molten solder from spreading to the adjacent interlayer connection electrode pad and short-circuiting. In this case, the reflow condition is set to be equal to or lower than the melting point of the solder layer 28 of the solder bump 26. Therefore, it can be prevented that the solder layer 28 of the solder bump 26 is remelted and the solder bump 26 is detached from the interlayer connection electrode pad 22b.
[0033]
Next, as shown in FIG. 2C, the two intermediate boards 24 with the solder bumps 25 and 26 formed on the front and back sides as shown in FIG. The interlayer connection electrode pads 22a of the intermediate substrate 24 positioned on the lower side and the interlayer connection electrode pads 22b of the intermediate substrate 24 positioned on the upper side are aligned, and solder bumps are stacked. 26 and the solder bump 25 are overlapped and aligned in a vertical line. The alignment in this case may be performed, for example, by inserting a positioning pin into a through hole provided in each intermediate substrate 24. Note that a flux may be applied between the overlapping solder bumps 26 and the solder bumps 25.
[0034]
Next, by performing the reflow process at a temperature at which the solder layer 30 of the solder bump 25 is remelted while the solder layer 28 of the solder bump 26 is not remelted, that is, a temperature of 183 ° C. or more and less than 221 ° C. The solder layer 30 is remelted. In this case, the reflow condition is set to be lower than the melting point of the solder layer 28 of the solder bump 26. Therefore, it can be prevented that the solder layer 28 of the solder bump 26 is remelted and the solder bump 26 is detached from the interlayer connection electrode pad 22b.
[0035]
After that, the solder layer 30 of the re-melted solder bump 25 rises along the surface of the solder layer 28 as shown in FIG. 1 due to the surface tension and the wettability of the solder bump 26 to the solder layer 28. The solder bumps 26 and the solder bumps 25 are mechanically and electrically connected.
[0036]
As described above, in this embodiment, the interlayer connection electrode pads 22a and 22b are formed on the peripheral portions of the front and back surfaces of the intermediate substrate 24 on which the plurality of semiconductor chips 21 are flip-chip mounted on both the front and back surfaces. Then, a solder bump 25 is formed on the interlayer connection electrode pad 22a by covering the periphery of the resin ball 29 with the solder layer 30, and on the interlayer connection electrode pad 22b, the melting point of the metal ball 27 is a solder layer. A solder bump 26 covered with a solder layer 28 higher than 30 is formed.
[0037]
Then, the solder bumps 25 of one intermediate substrate 24 and the solder bumps 26 of the other intermediate substrate 24 are overlapped and aligned, and the solder bumps 25 and the solder bumps 26 are melted and connected by reflow processing. The interlayer connection electrode pad 22a of the substrate 24 and the interlayer connection electrode pad 22b of the other intermediate substrate 24 are mechanically and electrically connected.
[0038]
At this time, the solder bump 25 having the solder layer 30 having a low melting point is set on the lower side, and the reflow temperature condition is set such that the lower solder layer 30 is melted while the upper solder layer 28 is not melted. Therefore, it is possible to prevent the solder layer 28 of the solder bump 26 from melting and the upper solder bump 26 from dropping from the interlayer connection electrode pad 22b.
[0039]
That is, according to this embodiment, the occurrence of an open defect between the connected electrode pads 22a and 22b and a short defect between adjacent electrode pads are effectively prevented. Further, resin balls 29 are provided in the solder bumps 25, while metal balls 27 are provided in the solder bumps 26, and the metal balls 27 and the resin balls 29 are vertically aligned in a straight line after interlayer connection. Can do. Therefore, even when the intermediate substrate 24 on which the plurality of semiconductor chips 21 are mounted on both the front and back surfaces is laminated and interlayer connection is made, a sufficient mounting height can be ensured by using relatively small solder bumps.
[0040]
As described above, according to this embodiment, it is possible to provide a connection structure between stacked substrates of a semiconductor module that is suitable for narrowing the pitch of electrode pads and excellent in connection reliability.
[0041]
In the above embodiment, the solder bumps 25 are provided with resin balls 29 and the solder bumps 26 are provided with metal balls 27. However, the present invention is not limited to this, and the ball-shaped core provided in both solder bumps 25 and 26 may be either a metal ball or a resin ball.
[0042]
Moreover, in the said embodiment, although the semiconductor chip 21 is mounted in both the front and back of the said intermediate | middle board | substrate 24, even if it forms only in any one of the surface and a back surface, it does not interfere. In the above embodiment, the interlayer connection electrode pads 22a and 22b are formed on both the front and back surfaces of the intermediate substrate 24. However, when only the two intermediate substrates 24 are stacked, the interlayer is formed only on one surface. The connection electrode pad 22 may be formed.
[0043]
【The invention's effect】
As is clear from the above, in the semiconductor module laminated substrate connection structure of the present invention, two or more substrates having solder bumps formed on the surface are fused by superimposing the solder bumps in a substantially vertical direction. In the semiconductor module formed by laminating by the above, the solder bump is composed of a core and a solder layer having a melting point lower than the core, and the solder layer constituting the solder bump located on the upper side at the time of the fusion Since the melting point is higher than the melting point of the solder layer constituting the solder bump located on the lower side, the fusion temperature is higher than the melting point of the lower solder layer and lower than the melting point of the upper solder layer. By doing so, it is possible to prevent the solder layer constituting the solder bump located on the upper side from melting and the upper solder bump from falling off during the fusion.
[0044]
Therefore, it is possible to prevent the occurrence of an open defect between connected electrode pads and a short defect between adjacent electrode pads. In addition, the core of the upper solder bump and the core of the lower solder bump can be vertically aligned in a straight line after the interlayer connection, and it is sufficient even if the semiconductor circuit element is mounted on the front and back of the substrate. The mounting height (interval between the stacked substrates) can be ensured.
[0045]
That is, according to the present invention, it is possible to provide a connection structure between semiconductor substrates for a semiconductor module, which is suitable for narrowing the pitch of electrode pads and excellent in connection reliability.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a connection structure between laminated substrates of a semiconductor module according to the present invention.
2 is a process diagram showing a method for forming the connection structure between laminated substrates shown in FIG. 1; FIG.
FIG. 3 is a cross-sectional view of a connection structure between stacked substrates of a conventional semiconductor module.
4 is a cross-sectional view of a conventional semiconductor module inter-substrate connection structure different from FIG. 3;
[Explanation of symbols]
21 ... Semiconductor chip,
22a, 22b ... interlayer connection electrode pads,
23 ... Solder resist,
24 ... intermediate substrate,
25, 26 ... solder bumps,
27 ... Metal balls,
28, 30 ... solder layer,
29: Resin ball.

Claims (4)

半導体回路素子が表面実装されると共に表面に半田バンプが形成された２以上の基板を、互いの半田バンプを略垂直方向に重ね合わせて融着することによって、積層してなる半導体モジュールの積層基板間接続構造であって、
上記半田バンプは、核とこの核よりも低融点の半田層とで構成されており、
上記融着の際に上側に位置する半田バンプを構成する半田層の融点が、下側に位置する半田バンプを構成する半田層の融点よりも高くなっている
ことを特徴とする半導体モジュールの積層基板間接続構造。A laminated substrate of a semiconductor module in which two or more substrates on which a semiconductor circuit element is surface-mounted and solder bumps are formed on the surface are laminated by fusing the solder bumps in a substantially vertical direction. An inter-connection structure,
The solder bump is composed of a core and a solder layer having a melting point lower than that of the core.
Lamination of a semiconductor module, wherein the melting point of the solder layer constituting the solder bump located on the upper side during the fusion is higher than the melting point of the solder layer constituting the solder bump located on the lower side Board-to-board connection structure. 請求項１に記載の半導体モジュールの積層基板間接続構造において、
上記融着の際に上側に位置する半田バンプを構成する半田層の融点は２２０℃以上である
ことを特徴とする半導体モジュールの積層基板間接続構造。In the connection structure between the laminated substrates of the semiconductor module according to claim 1,
A connection structure between laminated substrates of a semiconductor module, wherein a melting point of a solder layer constituting a solder bump located on the upper side at the time of fusion is 220 ° C. or higher. 請求項１に記載の半導体モジュールの積層基板間接続構造において、
上記融着の際に下側に位置する半田バンプを構成する半田層の融点は１８５℃以下である
ことを特徴とする半導体モジュールの積層基板間接続構造。In the connection structure between the laminated substrates of the semiconductor module according to claim 1,
A connection structure between laminated substrates of a semiconductor module, wherein a melting point of a solder layer constituting a solder bump located on the lower side at the time of fusion is 185 ° C. or less. 請求項１に記載の半導体モジュールの積層基板間接続構造において、
上記融着の際に上側に位置する半田バンプを構成する半田層の融点は２２１℃であり、上記核は銅およびニッケルの何れか一方でなる金属ボールであり、
上記融着の際に下側に位置する半田バンプを構成する半田層の融点は１８３℃であり、上記核はジビニルベンゼン架橋共重合体でなる樹脂系ボールである
ことを特徴とする半導体モジュールの積層基板間接続構造。In the connection structure between the laminated substrates of the semiconductor module according to claim 1,
The melting point of the solder layer constituting the solder bump located on the upper side at the time of fusion is 221 ° C., and the core is a metal ball made of either copper or nickel,
The melting point of the solder layer constituting the solder bump located on the lower side during the fusion is 183 ° C., and the core is a resin-based ball made of a divinylbenzene crosslinked copolymer. Layered substrate connection structure.
JP2003164809A 2003-06-10 2003-06-10 Connection structure between laminated substrates of semiconductor module Pending JP2005005358A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173583A (en) * 2005-12-22 2007-07-05 Olympus Corp Laminated mounting structure
JP2009054684A (en) * 2007-08-24 2009-03-12 Powertech Technology Inc Semiconductor pop device
JP2010153491A (en) * 2008-12-24 2010-07-08 Shinko Electric Ind Co Ltd Electronic apparatus and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173583A (en) * 2005-12-22 2007-07-05 Olympus Corp Laminated mounting structure
JP2009054684A (en) * 2007-08-24 2009-03-12 Powertech Technology Inc Semiconductor pop device
JP2010153491A (en) * 2008-12-24 2010-07-08 Shinko Electric Ind Co Ltd Electronic apparatus and manufacturing method thereof

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