TWI570861B - Package structure and method of manufacture - Google Patents
Package structure and method of manufacture Download PDFInfo
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- TWI570861B TWI570861B TW103141925A TW103141925A TWI570861B TW I570861 B TWI570861 B TW I570861B TW 103141925 A TW103141925 A TW 103141925A TW 103141925 A TW103141925 A TW 103141925A TW I570861 B TWI570861 B TW I570861B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本發明係有關一種封裝結構,尤指一種單層線路層之封裝結構及其製法。 The invention relates to a package structure, in particular to a package structure of a single layer circuit layer and a preparation method thereof.
隨著半導體封裝技術的演進,於智慧型手機、平板、網路、筆記型電腦等產品中,半導體裝置(Semiconductor device)已開發出不同的封裝型態,例如,球柵陣列式(Ball grid array,簡稱BGA)、四方扁平式半導體封裝件(Quad-Flat Package,簡稱QFP)或四方扁平無導腳式(Quad Flat Nonlead Package,簡稱QFN)半導體封裝件等。 With the evolution of semiconductor packaging technology, semiconductor devices (Semiconductor devices) have developed different package types in smart phones, tablets, networks, notebook computers, etc., for example, Ball grid array , referred to as BGA), quad flat package (QFP) or quad flat nonlead package (QFN) semiconductor package.
如第1A圖所示,習知QFP封裝結構1包括:承載座10、位於該承載座10周圍之複數導腳11、黏接至該承載座10上並以複數焊線120電性連接該導腳11之電子元件12、以及包覆該電子元件12、承載座10、焊線120及導腳11之如封裝膠體之絕緣層13,且該導腳11凸伸出該絕緣層13。 As shown in FIG. 1A, the conventional QFP package structure 1 includes a carrier 10, a plurality of pins 11 around the carrier 10, and is bonded to the carrier 10 and electrically connected to the plurality of bonding wires 120. The electronic component 12 of the leg 11 and the insulating layer 13 encapsulating the electronic component 12, the carrier 10, the bonding wire 120 and the lead 11 are encapsulated, and the guiding pin 11 protrudes from the insulating layer 13.
然而,習知QFP封裝結構1之製法中,該承載座10與該些導腳11係來自於導線架,故無法任意佈線,亦即限制線路與接點之設計。例如,習知導線架之一排導腳11 之總長約佔有400um,該承載座10之總長約佔有125um,故已限制該導腳11之I/O數量與長度(pitch)。 However, in the conventional method of manufacturing the QFP package structure 1, the carrier 10 and the leads 11 are derived from the lead frame, so that the wiring cannot be arbitrarily arranged, that is, the design of the line and the contact is restricted. For example, a conventional lead frame has one row of guide pins 11 The total length is about 400um, and the total length of the carrier 10 is about 125um, so the number and pitch of the I/O of the lead 11 has been limited.
再者,於進行封裝時,受限於該導線架之固定尺寸與該焊線120之高度,故習知QFP封裝結構1之整體厚度較厚,且難以薄化。 Moreover, when the package is packaged, it is limited by the fixed size of the lead frame and the height of the bonding wire 120. Therefore, the conventional QFP package structure 1 has a thick overall thickness and is difficult to be thinned.
又,習知QFP封裝結構1中,受限於該導線架之設計,導致其導腳11之數量少,亦即接點數量少,因而難以實現高接點數量與薄型化之需求。 Moreover, in the conventional QFP package structure 1, limited by the design of the lead frame, the number of the lead pins 11 is small, that is, the number of contacts is small, so that it is difficult to achieve the number of high contacts and thinning.
如第1B圖所示,習知BGA封裝結構1’能在相同單位面積之封裝基板上容納更多輸入/輸出接點(I/O connection)以符合高度集積化(Integration)之晶片所需。所述之封裝結構1’包括:於上側10a與下側10b具有一線路層11a,11b之一承載板10’、設於該承載板10’上側10a並以複數導電凸塊120’電性連接該線路層11a之電子元件12、包覆該些導電凸塊120’之如底膠之絕緣層13、以及設於該承載板10’下側10b之線路層11b上之複數如焊球之導電元件14,且該承載板10’中具有電性連接該線路層11a,11b之導電柱100。因此,該電子元件12係以打線接合(wre bonding)或覆晶接合(Flip chip)方式電性連接該承載板10’,再於該承載板10’下側10b之線路層11b植設導電元件14而進行電性外接,以達到高腳數之目的。 As shown in Fig. 1B, the conventional BGA package structure 1' can accommodate more I/O connections on a package substrate of the same unit area to meet the requirements of a highly integrated wafer. The package structure 1 ′ includes: a carrier layer 10 ′ having a circuit layer 11 a , 11 b on the upper side 10 a and the lower side 10 b , and an upper side 10 a of the carrier board 10 ′ and electrically connected by a plurality of conductive bumps 120 ′ The electronic component 12 of the circuit layer 11a, the insulating layer 13 covering the conductive bumps 120', and the circuit layer 11b disposed on the lower side 10b of the carrier 10' are electrically conductive, such as solder balls. The component 14 has a conductive post 100 electrically connected to the circuit layer 11a, 11b. Therefore, the electronic component 12 is electrically connected to the carrier board 10' by wire bonding or flip chip bonding, and the conductive component is implanted on the circuit layer 11b of the lower side 10b of the carrier board 10'. 14 and electrical external connection, in order to achieve the goal of high number of feet.
惟,習知BGA封裝結構1’中,於更高頻使用時或高速操作時,因訊號傳遞路徑過長(即導電元件14、線路層11a,11b與導電柱100)而無法提昇電性表現,以致於該封 裝結構1’之效能有所限制。 However, in the conventional BGA package structure 1', when the signal is transmitted at a higher frequency or at a high speed, the signal transmission path is too long (ie, the conductive element 14, the circuit layers 11a, 11b and the conductive pillar 100) cannot improve the electrical performance. So that the seal The performance of the mounting structure 1' is limited.
再者,習知BGA封裝結構1’需製作至少兩層線路層11a,11b與導電柱100(如鑽孔製程,且於導通孔內鍍上銅材,以作為層與層間之連接),故整體結構不僅難以符合薄化需求,且因生產製程複雜、流程長而難以降低製造成本。 Furthermore, the conventional BGA package structure 1' needs to fabricate at least two circuit layers 11a, 11b and a conductive pillar 100 (such as a drilling process, and a copper material is plated in the via hole as a layer-to-layer connection). The overall structure is not only difficult to meet the thinning requirements, but it is difficult to reduce the manufacturing cost due to the complicated production process and long process.
又,習知BGA封裝結構1’因需製作較多的連接介面(如兩線路層11a,11b與導電柱100之間),且需使用各層材質不相同之複合式承載板10’,故不僅容易發生分層,且大幅增加製造成本。 Moreover, the conventional BGA package structure 1' needs to make more connection interfaces (such as between the two circuit layers 11a, 11b and the conductive pillars 100), and it is necessary to use the composite carrier board 10' with different material layers, so not only It is prone to delamination and greatly increases manufacturing costs.
另外,因該承載板10’係由多層(多種原材料組成)熱膨脹係數(thermal expansion coefficient,簡稱CTE)與電性特質不匹配之複合式材質所構成,特別是材料間之CTE不匹配,故於製程中容易發生翹曲。 In addition, since the carrier plate 10' is composed of a composite material having a thermal expansion coefficient (CTE) which is composed of a plurality of layers (a plurality of materials) and an electrical property mismatch, in particular, the CTE between the materials does not match, so Warpage is prone to occur in the process.
因此,如何避免習知技術中之種種缺失,實已成為目前亟欲解決的課題。 Therefore, how to avoid all kinds of defects in the prior art has become a problem that is currently being solved.
鑑於上述習知技術之種種缺失,本發明提供一種封裝結構,係包括:一絕緣層,係具有相對之第一表面與第二表面;複數導電柱,係嵌埋於該絕緣層中且其端面係外露於該絕緣層之第一表面;一線路層,係嵌設於該絕緣層之第二表面上並電性連接該些導電柱;至少一電子元件,係設於該線路層上並電性連接該線路層;以及一包覆層,係形成於該線路層與該絕緣層之第二表面上並包覆該電子元件。 In view of the above-mentioned various deficiencies of the prior art, the present invention provides a package structure comprising: an insulating layer having opposite first and second surfaces; and a plurality of conductive pillars embedded in the insulating layer and having end faces thereof Exposed on the first surface of the insulating layer; a circuit layer is embedded on the second surface of the insulating layer and electrically connected to the conductive pillars; at least one electronic component is disposed on the circuit layer and electrically And connecting the circuit layer; and a cladding layer formed on the circuit layer and the second surface of the insulating layer and covering the electronic component.
本發明復提供一種封裝結構之製法,係包括:形成複數導電柱於一導體層上;形成一絕緣層於該導體層與該些導電柱上,其中,該絕緣層係具有相對之第一表面與第二表面,且令該些導電柱之端面外露於該絕緣層之第一表面;移除該導體層之部分材質,使該導體層作為線路層;於該線路層上設置至少一電子元件,且該電子元件電性連接該線路層;以及於該線路層與該絕緣層之第二表面上形成一包覆層,使該包覆層包覆該電子元件。 The invention provides a method for fabricating a package structure, comprising: forming a plurality of conductive pillars on a conductor layer; forming an insulating layer on the conductor layer and the conductive pillars, wherein the insulating layer has a first surface opposite to the first surface And a second surface, wherein the end faces of the conductive pillars are exposed on the first surface of the insulating layer; part of the material of the conductor layer is removed, and the conductor layer is used as a circuit layer; at least one electronic component is disposed on the circuit layer And the electronic component is electrically connected to the circuit layer; and a cladding layer is formed on the circuit layer and the second surface of the insulating layer, so that the cladding layer covers the electronic component.
本發明另提供一種封裝結構之製法,係包括:形成複數導電柱於一導體層上;形成一絕緣層於該導體層與該些導電柱上,並使該絕緣層完全包覆該些導電柱,其中,該絕緣層係具有相對之第一表面與第二表面;移除部分的絕緣層,令該些導電柱之端面外露於該絕緣層之第一表面;移除該導體層之部分材質,使該導體層作為線路層;於該線路層上設置至少一電子元件,且該電子元件電性連接該線路層;以及於該線路層與該絕緣層之第二表面上形成一包覆層,使該包覆層包覆該電子元件。 The invention further provides a method for fabricating a package structure, comprising: forming a plurality of conductive pillars on a conductor layer; forming an insulating layer on the conductor layer and the conductive pillars, and completely covering the conductive pillars The insulating layer has a first surface and a second surface opposite to each other; a portion of the insulating layer is removed, the end surfaces of the conductive pillars are exposed on the first surface of the insulating layer; and a part of the material of the conductive layer is removed The conductor layer is used as a circuit layer; at least one electronic component is disposed on the circuit layer, and the electronic component is electrically connected to the circuit layer; and a cladding layer is formed on the circuit layer and the second surface of the insulating layer The cladding is coated with the electronic component.
由上可知,本發明封裝結構及其製法,係藉由僅需製作一層線路層,且以該導電柱作外接墊之設計,使該線路層結合電子元件,而導電柱結合焊球,以縮短訊號傳遞路徑,因而能減少訊號損失,故能提昇電氣特性。 It can be seen from the above that the package structure of the present invention and the method for manufacturing the same are achieved by only making one layer of the circuit layer and designing the conductive column as an external pad, so that the circuit layer is combined with the electronic component, and the conductive column is combined with the solder ball to shorten The signal transmission path can reduce signal loss and improve electrical characteristics.
再者,本發明封裝結構藉由將複數導電柱形成於單一線路層上之設計,使該些導電柱之端面作外接墊,因而無需製作另一層線路,故能省略習知鑽孔製程、填孔製程、 第二線路層之製作等,因而不僅大幅降低封裝結構之厚度以符合薄化之需求,且能大幅降低製造成本。 Furthermore, the package structure of the present invention is formed by forming a plurality of conductive pillars on a single circuit layer, so that the end faces of the conductive pillars are used as external pads, so that it is not necessary to make another layer of wiring, so that the conventional drilling process and filling can be omitted. Hole process, The fabrication of the second circuit layer and the like not only greatly reduces the thickness of the package structure to meet the demand for thinning, but also greatly reduces the manufacturing cost.
又,本發明封裝結構係於單一線路層與該些導電柱間具有連接介面,使其連接介面之數量少於習知技術之連接介面之數量,因而能避免分層問題,且因直接將該導電層圖案化製作成該線路層,故能大幅降低製造成本。 Moreover, the package structure of the present invention has a connection interface between the single circuit layer and the conductive pillars, so that the number of connection interfaces is less than the number of connection interfaces of the prior art, thereby avoiding the delamination problem, and The conductive layer is patterned into the wiring layer, so that the manufacturing cost can be greatly reduced.
另外,本發明之絕緣層係為單一材質,而非習知承載板之複合式材質,故能避免該絕緣層之應力分佈不均而發生翹曲之問題。 In addition, the insulating layer of the present invention is a single material, rather than a composite material of the conventional carrier plate, so that the problem of warpage of the unevenness of the stress distribution of the insulating layer can be avoided.
1、1’、2‧‧‧封裝結構 1, 1', 2‧‧‧ package structure
10‧‧‧承載座 10‧‧‧Hosting
10’‧‧‧承載板 10’‧‧‧Bearing board
10a‧‧‧上側 10a‧‧‧Upper side
10b‧‧‧下側 10b‧‧‧ underside
100‧‧‧導電柱 100‧‧‧conductive column
11‧‧‧導腳 11‧‧‧ lead
11a、11b、20’‧‧‧線路層 11a, 11b, 20’‧‧‧ circuit layer
12、22‧‧‧電子元件 12, 22‧‧‧ Electronic components
120‧‧‧焊線 120‧‧‧welding line
120’、220‧‧‧導電凸塊 120', 220‧‧‧ conductive bumps
13、25‧‧‧絕緣層 13, 25‧‧‧ insulation
14、24‧‧‧導電元件 14, 24‧‧‧ conductive components
20‧‧‧導體層 20‧‧‧Conductor layer
21‧‧‧導電柱 21‧‧‧conductive column
21a‧‧‧端面 21a‧‧‧ end face
23‧‧‧包覆層 23‧‧‧Cladding
25a‧‧‧第一表面 25a‧‧‧ first surface
20b‧‧‧第二表面 20b‧‧‧second surface
200‧‧‧凹狀 200‧‧‧ concave
S‧‧‧切割路徑 S‧‧‧ cutting path
第1A圖係為習知QFP封裝結構的剖視示意圖;第1B圖係為習知BGA封裝結構之剖視示意圖;以及第2A至2H圖係為本發明之封裝結構之製法之剖視示意圖。 1A is a cross-sectional view showing a conventional QFP package structure; FIG. 1B is a cross-sectional view showing a conventional BGA package structure; and FIGS. 2A to 2H are cross-sectional views showing a method of manufacturing the package structure of the present invention.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術 內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. Technology disclosed by the invention The content can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.
第2A至2G圖係為本發明之封裝結構2之製法之剖視示意圖。 2A to 2G are schematic cross-sectional views showing the manufacturing method of the package structure 2 of the present invention.
如第2A圖所示,提供一導體層20。於本實施例中,該導體層20係為金屬材,例如銅,但不限於此。 As shown in FIG. 2A, a conductor layer 20 is provided. In the present embodiment, the conductor layer 20 is a metal material such as copper, but is not limited thereto.
如第2B圖所示,形成複數導電柱21於該導體層20上。 As shown in FIG. 2B, a plurality of conductive pillars 21 are formed on the conductor layer 20.
如第2C圖所示,形成一絕緣層25於該導體層20與該些導電柱21上,並使該絕緣層25完全包覆該些導電柱21,其中,該絕緣層25係具有相對之第一表面25a與第二表面25b。 As shown in FIG. 2C, an insulating layer 25 is formed on the conductive layer 20 and the conductive pillars 21, and the insulating layer 25 is completely covered with the conductive pillars 21, wherein the insulating layer 25 has opposite phases. The first surface 25a and the second surface 25b.
於本實施例中,形成該絕緣層25之材質係為底層塗料(Primer)或介電材料。 In the present embodiment, the material forming the insulating layer 25 is a primer or a dielectric material.
如第2D圖所示,移除該絕緣層25之第一表面25a之部分材質,令該些導電柱21之端面21a外露於該絕緣層25之第一表面25a。 As shown in FIG. 2D, part of the material of the first surface 25a of the insulating layer 25 is removed, so that the end faces 21a of the conductive pillars 21 are exposed on the first surface 25a of the insulating layer 25.
又,於其它實施例中可利用整平製程(如研磨絕緣層25之方式),使該些導電柱之端面齊平該絕緣層之第一表面。 Moreover, in other embodiments, a flattening process (such as grinding the insulating layer 25) may be utilized to make the end faces of the conductive pillars flush the first surface of the insulating layer.
如第2E圖所示,圖案化移除該導體層20之部分材質 與該絕緣層25之第二表面25b之部分材質,使該導體層20作為線路層20’,且令該絕緣層25之第二表面25b露出該線路層20’之部分表面。 As shown in FIG. 2E, part of the material of the conductor layer 20 is removed by patterning The portion of the second surface 25b of the insulating layer 25 is made of the conductor layer 20 as the wiring layer 20', and the second surface 25b of the insulating layer 25 is exposed to a part of the surface of the wiring layer 20'.
於本實施例中,該線路層20’係電性連接該些導電柱21。 In this embodiment, the circuit layer 20' is electrically connected to the conductive pillars 21.
再者,係以蝕刻方式進行圖案化,故該線路層20’之側面會呈現凹狀200。 Further, the patterning is performed by etching, so that the side surface of the wiring layer 20' will have a concave shape 200.
如第2F圖所示,於該線路層20’上設置至少一電子元件22,且該電子元件22電性連接該線路層20’。 As shown in Fig. 2F, at least one electronic component 22 is disposed on the wiring layer 20', and the electronic component 22 is electrically connected to the wiring layer 20'.
於本實施例中,該電子元件22係為主動元件、被動元件或其二者組合,且該主動元件係例如半導體元件(如晶片),而該被動元件係例如電阻、電容及電感。 In this embodiment, the electronic component 22 is an active component, a passive component, or a combination thereof, and the active component is, for example, a semiconductor component (such as a wafer), and the passive component is, for example, a resistor, a capacitor, and an inductor.
再者,該電子元件22係藉由複數導電凸塊220以經由該線路層20’電性連接至該些導電柱21。 Moreover, the electronic component 22 is electrically connected to the conductive pillars 21 via the circuit layer 20' by a plurality of conductive bumps 220.
如第2G圖所示,於該線路層20’與該絕緣層25之第二表面25b上形成一包覆層23,使該包覆層23包覆該電子元件22與該些導電凸塊220。 As shown in FIG. 2G, a cladding layer 23 is formed on the circuit layer 20' and the second surface 25b of the insulating layer 25, so that the cladding layer 23 covers the electronic component 22 and the conductive bumps 220. .
於本實施例中,該包覆層23係以鑄模方式(molding)、塗佈方式或壓合方式形成於該承載板20上,且形成該包覆層23之材質係為鑄模化合物(Molding Compound)、底層塗料(Primer)、或如環氧樹脂(Epoxy)之介電材料。 In the present embodiment, the coating layer 23 is formed on the carrier plate 20 by molding, coating, or pressing, and the material of the coating layer 23 is a mold compound (Molding Compound). ), Primer, or a dielectric material such as Epoxy.
再者,於另一實施例中,該電子元件22之上表面亦可外露於該包覆層23之上表面。 Furthermore, in another embodiment, the upper surface of the electronic component 22 may also be exposed on the upper surface of the cladding layer 23.
又,於其它實施例中,亦可先形成底膠(圖略)以包 覆該些導電凸塊220,再形成該包覆層23。 Moreover, in other embodiments, the primer (not shown) may be formed first. The conductive bumps 220 are covered, and the cladding layer 23 is formed.
如第2H圖所示,形成複數如焊球之導電元件24於該絕緣層25之第一表面25a上,且沿如第2G圖所示之切割路徑S進行切單製程,以獲得複數封裝結構2。 As shown in FIG. 2H, a plurality of conductive elements 24 such as solder balls are formed on the first surface 25a of the insulating layer 25, and a singulation process is performed along the cutting path S as shown in FIG. 2G to obtain a plurality of package structures. 2.
於本實施例中,該些導電元件24係結合並電性連接該些導電柱21之端面21a,以藉由該些導電元件24堆疊結合其它電子裝置(圖略)。 In this embodiment, the conductive elements 24 are bonded and electrically connected to the end faces 21a of the conductive pillars 21 to be combined with other electronic devices (not shown) by the conductive components 24.
本發明封裝結構2之製法中,係藉由僅需製作一層線路層20’,且以該導電柱21作外接墊,使該線路層20’結合該電子元件22,而該些導電柱21結合該些導電元件24,以縮短訊號傳遞路徑,因而能減少訊號損失,故能提昇電氣特性。 In the manufacturing method of the package structure 2, the wiring layer 20' is bonded to the electronic component 22 by using only one wiring layer 20', and the conductive pillar 21 is used as an external pad, and the conductive pillars 21 are combined. The conductive elements 24 are used to shorten the signal transmission path, thereby reducing signal loss and thereby improving electrical characteristics.
再者,本發明封裝結構2藉由將複數導電柱21形成於單一線路層20’上之設計,使該些導電柱21之端面21a作外接墊,因而無需製作另一層線路,故能省略習知鑽孔製程、填孔製程、第二線路層之製作等,因而不僅大幅降低該封裝結構2之整體厚度以符合薄化之需求,且能大幅降低製造成本。 Furthermore, the package structure 2 of the present invention has the design of the plurality of conductive pillars 21 formed on the single circuit layer 20', so that the end faces 21a of the conductive pillars 21 are used as external pads, so that it is not necessary to make another layer of wiring, so that the description can be omitted. Knowing the drilling process, the hole filling process, the fabrication of the second circuit layer, and the like, thereby not only greatly reducing the overall thickness of the package structure 2 to meet the demand for thinning, but also greatly reducing the manufacturing cost.
又,本發明封裝結構2係於單一線路層20’與該些導電柱21間具有連接介面,使其連接介面之數量少於習知技術之連接介面之數量,因而能降低分層之風險,故可靠度提高,且因直接將該導體層20圖案化製作成該線路層20’,故能大幅降低製造成本。 Moreover, the package structure 2 of the present invention has a connection interface between the single circuit layer 20' and the conductive pillars 21, and the number of connection interfaces is less than the number of connection interfaces of the prior art, thereby reducing the risk of delamination. Therefore, the reliability is improved, and the conductor layer 20 is directly patterned to form the wiring layer 20', so that the manufacturing cost can be greatly reduced.
另外,本發明之絕緣層25係為單一材質,而非習知承 載板之複合式材質,故能避免該絕緣層25之應力分佈不均而發生翹曲之問題。 In addition, the insulating layer 25 of the present invention is a single material, rather than a conventional The composite material of the carrier plate can avoid the problem of warpage caused by uneven stress distribution of the insulating layer 25.
本發明復提供一種封裝結構2,係包括:一絕緣層25、複數導電柱21、一線路層20’、至少一電子元件22、以及一包覆層23。 The present invention further provides a package structure 2 comprising: an insulating layer 25, a plurality of conductive pillars 21, a wiring layer 20', at least one electronic component 22, and a cladding layer 23.
所述之絕緣層25係具有相對之第一表面25a及第二表面25b。 The insulating layer 25 has opposite first and second surfaces 25a, 25b.
所述之導電柱21係嵌埋於該絕緣層25中且其端面21a係外露於該絕緣層25之第一表面25a。 The conductive pillar 21 is embedded in the insulating layer 25 and its end surface 21a is exposed on the first surface 25a of the insulating layer 25.
所述之線路層20’係嵌設於該絕緣層25之第二表面25b上並電性連接該些導電柱21。 The circuit layer 20' is embedded on the second surface 25b of the insulating layer 25 and electrically connected to the conductive pillars 21.
所述之電子元件22係設於該線路層20’上並電性連接該線路層20’。例如,該電子元件22係為主動元件、被動元件或其二者組合,且該電子元件22係以覆晶方式電性連接該線路層20’。 The electronic component 22 is disposed on the circuit layer 20' and electrically connected to the circuit layer 20'. For example, the electronic component 22 is an active component, a passive component, or a combination thereof, and the electronic component 22 is electrically connected to the wiring layer 20' in a flip chip manner.
所述之包覆層23係形成於該線路層20’與該絕緣層25之第二表面25b上並包覆該電子元件22。 The cladding layer 23 is formed on the wiring layer 20' and the second surface 25b of the insulating layer 25 and covers the electronic component 22.
於一實施例中,該線路層20’係定義供電性連接該電子元件22,且該些導電柱21之端面21a係定義為外接墊。 In one embodiment, the circuit layer 20' defines a power supply connection to the electronic component 22, and the end faces 21a of the conductive pillars 21 are defined as external pads.
於一實施例中,該導電柱之端面係齊平該絕緣層之第一表面(圖略)。 In one embodiment, the end surface of the conductive post is flush with the first surface of the insulating layer (not shown).
於一實施例中,所述之封裝結構2復包括複數導電元件24,係結合於該絕緣層25之第一表面25a上並電性連接該些導電柱21之端面21a。 In one embodiment, the package structure 2 includes a plurality of conductive elements 24 bonded to the first surface 25a of the insulating layer 25 and electrically connected to the end faces 21a of the conductive pillars 21.
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
2‧‧‧封裝結構 2‧‧‧Package structure
20’‧‧‧線路層 20’‧‧‧Line layer
21‧‧‧導電柱 21‧‧‧conductive column
21a‧‧‧端面 21a‧‧‧ end face
22‧‧‧電子元件 22‧‧‧Electronic components
220‧‧‧導電凸塊 220‧‧‧Electrical bumps
23‧‧‧包覆層 23‧‧‧Cladding
24‧‧‧導電元件 24‧‧‧Conducting components
25‧‧‧絕緣層 25‧‧‧Insulation
25a‧‧‧第一表面 25a‧‧‧ first surface
25b‧‧‧第二表面 25b‧‧‧second surface
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TW201011936A (en) * | 2008-09-05 | 2010-03-16 | Advanced Optoelectronic Tech | Light emitting device and fabrication thereof |
TW201409632A (en) * | 2012-08-22 | 2014-03-01 | 矽品精密工業股份有限公司 | Method of forming package substrate |
TW201436132A (en) * | 2012-12-28 | 2014-09-16 | Zhen Ding Technology Co Ltd | Package substrate, method for manufacturing same and package structure |
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TW201409632A (en) * | 2012-08-22 | 2014-03-01 | 矽品精密工業股份有限公司 | Method of forming package substrate |
TW201436132A (en) * | 2012-12-28 | 2014-09-16 | Zhen Ding Technology Co Ltd | Package substrate, method for manufacturing same and package structure |
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