TWI621224B - Package structure and manufacturing method thereof - Google Patents

Abstract

A packaging structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a wafer, a circuit layer structure, and an insulating protective layer. The composite layer of non-conductive inorganic material and organic material is disposed on the metal layer. The sealant is bonded to the composite layer of non-conducting inorganic material and organic material. The chip is embedded in the sealant, and the chip has a plurality of electrode pads. The circuit layer structure is formed on the sealant and the wafer. The circuit layer structure includes at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the circuit layer is located on the dielectric layer, and the bottommost circuit layer is electrically connected to the electrode pad through the conductive blind holes . The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has a plurality of openings, so that part of the surface of the circuit layer structure is exposed in the openings.

Description

Packaging structure and its manufacturing method

The invention relates to a packaging structure and a manufacturing method thereof.

With the evolution of semiconductor packaging technology, in addition to the traditional wire bonding semiconductor packaging technology, currently semiconductor devices (Semiconductor device) have developed different packaging types, such as directly embedded in the package substrate (package substrate) and The semiconductor chip with integrated circuit is electrically integrated to reduce the overall volume and enhance the electrical function.

In order to meet the requirements of shortening the length of wires and reducing the thickness of the overall structure, and responding to the trend of high frequency and miniaturization, a method for processing embedded wafer substrates on a coreless carrier board has been developed. However, due to the lack of a hard core plate body for the support board without a core layer, which results in insufficient strength, the overall structure is prone to warpage.

In view of this, one object of the present invention is to propose a packaging structure and a manufacturing method thereof that can solve the above problems.

In order to achieve the above object, according to one embodiment of the present invention, A packaging structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a wafer, a circuit layer structure, and an insulating protective layer. The composite layer of non-conductive inorganic material and organic material is disposed on the metal layer. The sealant is bonded to the composite layer of non-conducting inorganic material and organic material. The chip is embedded in the sealant, and the chip has a plurality of electrode pads, the electrode pads are exposed to the sealant. The circuit layer structure is formed on the sealant and the wafer. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has a plurality of conductive blind holes. The circuit layer is located on the dielectric layer and extends into the conductive blind holes. The bottommost circuit layer is electrically conductive. The blind hole is electrically connected to the electrode pad. The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has a plurality of openings, so that part of the surface of the circuit layer structure is exposed in the openings.

In one or more embodiments of the present invention, the above-mentioned wafer has a bottom surface of the wafer, and the bottom surface of the wafer is exposed to the sealant.

In one or more embodiments of the present invention, the material of the composite layer of the non-conductive inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.

In one or more embodiments of the present invention, the aforementioned ceramic material includes zirconia, alumina, silicon nitride, silicon carbide, silicon oxide, or a combination of the foregoing, and the polymer material includes epoxy resin, polyacrylamide Amine, liquid crystal polymer, methacrylate resin, vinyl phenyl resin, allyl resin, polyacrylate resin, polyether resin, polyolefin resin, polyamine resin, polysiloxane Type resin or a combination of the foregoing.

In one or more embodiments of the present invention, the composite layer of the non-conductive inorganic material and the organic material is a pearl-like layer.

According to another embodiment of the present invention, a packaging structure is manufactured The manufacturing method includes the following steps. First, a carrier board is provided. The carrier board includes a supporting layer having two opposite surfaces, a peeling layer disposed on both surfaces, and a metal layer disposed on the peeling layer. Next, a composite layer of a non-conductive inorganic material and an organic material is arranged on the metal layer. Then, the embedded wafer substrate is combined on the composite layer of non-conducting inorganic material and organic material, wherein the embedded wafer substrate includes a plurality of chips and a sealant, the chip is embedded in the sealant, and the chip has a plurality of electrode pads, electrodes The pad is exposed to the sealant. Next, a circuit layer structure is formed on the embedded chip substrate, wherein the circuit layer structure includes at least one dielectric layer and at least one circuit layer, wherein the dielectric layer has a plurality of conductive blind holes, and the circuit layer is located on the dielectric layer and extends To these conductive blind holes, the bottommost circuit layer is electrically connected to the electrode pad through the conductive blind holes. Then, an insulating protective layer is formed on the circuit layer structure, wherein the insulating protective layer has a plurality of openings, so that part of the surface of the circuit layer structure is exposed in the openings. Finally, the support layer and the peeling layer are removed to form two package substrates, and the package substrate is cut to obtain a plurality of package structures.

In one or more embodiments of the present invention, the above-mentioned sealant has a bottom surface of the sealant and the wafer has a bottom surface of the wafer. The above steps include the following steps. Grinding the bottom surface of the sealant to expose the bottom surface of the wafer to form a polished embedded wafer substrate; and combining the polished embedded wafer substrate on the composite layer of non-conducting inorganic material and organic material.

In one or more embodiments of the present invention, the material of the composite layer of the non-conductive inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.

In one or more embodiments of the present invention, the above-mentioned ceramic material The material includes zirconia, alumina, silicon nitride, silicon carbide, silicon oxide, or a combination of the foregoing, and the polymer material includes epoxy resin, polyimide, liquid crystal polymer, methacrylate resin, vinylbenzene Base resin, allyl resin, polyacrylate resin, polyether resin, polyolefin resin, polyamine resin, polysiloxane resin, or a combination of the foregoing.

In one or more embodiments of the present invention, the composite layer of the non-conductive inorganic material and the organic material is a pearl-like layer.

In summary, the packaging structure and manufacturing method of the present invention form a packaging substrate on the composite layer of non-conducting inorganic material and organic material, that is to say, the composite layer of non-conducting inorganic material and organic material can be regarded as one The reinforcement layer has a higher hardness than ordinary dielectric layers and packaging materials. Therefore, the packaging structure and manufacturing method of the present invention can strengthen the overall structural strength through the composite layer of non-conducting inorganic materials and organic materials to prevent the warpage of the carrier board, thereby not only improving the yield of the process, but also Improve the reliability of the packaging structure.

The above is only for explaining the problem to be solved by the present invention, the technical means for solving the problem, and the resulting effect, etc. The specific details of the present invention will be described in detail in the following embodiments and related drawings.

10‧‧‧ bearing plate

100‧‧‧Support layer

100A, 100B‧‧‧surface

102‧‧‧ Stripped layer

104‧‧‧Metal layer

106‧‧‧Composite layer of non-conducting inorganic and organic materials

108‧‧‧First dielectric layer

108H‧‧‧The first conductive blind hole

110‧‧‧ First circuit layer

112‧‧‧Insulation protective layer

112O‧‧‧ opening

12‧‧‧Embedded wafer substrate

12A‧‧‧Embedded wafer substrate after grinding

12S‧‧‧Bottom of substrate

120‧‧‧chip

120P‧‧‧electrode pad

120S‧‧‧Bottom of chip

122‧‧‧Sealing

122S‧‧‧Seal bottom

14‧‧‧ circuit layer structure

16‧‧‧Package substrate

18.18A‧‧‧Package structure

208‧‧‧Second dielectric layer

208H‧‧‧Second conductive blind hole

210‧‧‧ Second circuit layer

In order to make the above and other objects, features, advantages and embodiments of the present invention more obvious and understandable, the drawings are described as follows: FIGS. 1A to 1G are the steps of the manufacturing method of the packaging structure according to an embodiment of the present invention Section view.

2A-2B are cross-sectional views of partial steps of a method of manufacturing a package structure according to another embodiment of the invention.

FIG. 3 is a cross-sectional view of the package structure obtained according to the manufacturing method of FIGS. 2A-2B.

In the following, a plurality of embodiments of the present invention will be disclosed in the form of diagrams. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventional structures and elements will be shown in a simple schematic manner in the drawings.

FIGS. 1A to 1G are cross-sectional views of the steps of the method for manufacturing the package structure 18 according to an embodiment of the present invention. First, as shown in FIG. 1A, a carrier board 10 is provided. The carrier board 10 includes a support layer 100 having opposing surfaces 100A, 100B, a peeling layer 102 disposed on the opposing surfaces 100A, 100B, and a peeling layer 102.上 的 金属 层 104。 The upper metal layer 104. The material of the support layer 100 can be, for example, an organic polymer material such as bisimide bisimide / Bismaleimide triazine (BT), etc., and the support layer 100 can also be a combination of 100A and 100B on opposite surfaces. Copper Clad Laminate (CCL) (not shown) of electrical materials (for example, prepreg). The release layer 102 can be a release film, or other techniques can be used to provide the release layer 102, such as: copper foil bonded release layers provided by companies such as Mitsui, Nippon-Denk, Furukawa, or Olin. The thickness of the metal layer 104 may be selected from 1 micron To the range of 10 microns, and the material of the metal layer 104 may be copper.

In some embodiments, another metal layer may be included between the opposing surfaces 100A, 100B of the support layer 100 and the peeling layer 102, and the thickness of the other metal layer may be selected from the range of 5 microns to 40 microns. The material may be the same as or different from the metal layer 104, and may be copper, for example.

Next, as shown in FIG. 1B, a composite layer 106 of a non-conductive inorganic material and an organic material is arranged on the metal layer 104.

Further, the material of the composite layer 106 of the non-conductor inorganic material and the organic material in this embodiment is, for example, a composite material composed of a ceramic material and a polymer material, wherein the ceramic material includes zirconia, alumina, and nitrogen Silicon carbide, silicon carbide, silicon oxide, or a combination of the foregoing, and the polymer materials include epoxy resin, polyimide, liquid crystal polymer, methacrylate resin, vinyl phenyl resin, allyl resin, Polyacrylate resin, polyether resin, polyolefin resin, polyamine resin, polysiloxane resin, or a combination of the foregoing. The ceramic material may be a ceramic laminate or ceramic powder, but the ceramic material in this embodiment is not limited thereto.

In the embodiment of the ceramic powder, the method for manufacturing the composite layer 106 of the non-conductor inorganic material and the organic material may use vacuum impregnation technology to impregnate the polymer material into the ceramic powder to prepare a composite composed of the ceramic powder and the polymer material A composite layer 106 of a non-conductive inorganic material and an organic material composed of materials. The polymer material is an example of a photosensitive resin composition of an epoxy resin and an imide resin, for example, a non-conductive inorganic material and an organic material are irradiated by ultraviolet light and heating after thermal compression bonding or vacuum immersion The composite layer 106 is disposed on the metal layer 104.

In the embodiment of the ceramic laminate, the method for manufacturing the composite layer 106 of non-conductor inorganic material and organic material can use vacuum impregnation technology to impregnate the polymer material into the ceramic laminate to prepare the ceramic laminate and the polymer material A composite layer 106 of a non-conducting inorganic material and an organic material composed of a composite material. However, the manufacturing method of the composite layer 106 of the non-conductor inorganic material and the organic material in this embodiment is not limited to this, and other methods that can form a composite material of a polymer material and a ceramic material can also be used. In the ceramic laminate embodiment, in more detail, the composite layer 106 of non-conducting inorganic material and organic material includes a composite composition of organic matter and inorganic matter (for example, a composite composition of a polymer material and a ceramic laminate), based on organic matter versus inorganic matter. Adhesion, the ceramic layer of the composite layer 106 of non-conductor inorganic material and organic material has a micro-layered structure of sheet, brick or combination arrangement. This arrangement suppresses the transmission of lateral cracking force, which significantly increases its hardness degree. In this way, the material is strong and elastic, which can improve the strength of the ceramic and improve the brittleness of the ceramic, while having excellent toughness. The composite layer 106 of the non-conductor inorganic material and the organic material may be an imitation nacreous layer.

Here, the Young's coefficient of the composite layer 106 of the non-conductive inorganic material and the organic material is, for example, between 20 GPa and 100 GPa. Compared to conventionally used dielectric layers (with a Young's coefficient of no greater than 10 GPa) and packaging materials (with a Young's coefficient of no greater than 20 GPa), the composite layer 106 of non-conducting inorganic and organic materials in this embodiment has The excellent hardness can effectively strengthen the structural strength of the packaging structure.

Then, as shown in FIG. 1C, the embedded wafer substrate 12 is combined on the composite layer 106 of non-conductive inorganic material and organic material, in which the embedded wafer substrate 12 includes a plurality of wafers 120 and an encapsulant 122. The chips 120 are embedded in the encapsulant 122, and each wafer 120 has a plurality of electrode pads 120P. The electrode pads 120P are exposed to the encapsulant 122.

The method of combining the embedded wafer substrate 12 on the composite layer 106 of non-conducting inorganic material and organic material can be performed by, for example, an adhesive layer (not shown). Specifically, the adhesive layer may be adhered to the bottom surface 12S of the embedded wafer substrate 12, and then the embedded wafer substrate 12 may be bonded to the composite layer 106 of the non-conducting inorganic material and the organic material. The above adhesive layer may include a heat dissipation agent with high heat dissipation or high temperature resistance, but the invention is not limited thereto.

Next, as shown in FIGS. 1D to 1E, a circuit layer structure 14 is formed on the embedded wafer substrate 12, wherein each circuit layer structure 14 includes at least one dielectric layer and at least one circuit layer, and each dielectric layer has a plurality of conductive layers In the blind hole, each circuit layer is located on each dielectric layer and extends into the conductive blind hole, and the bottommost circuit layer is electrically connected to the electrode pad 120P through the conductive blind hole.

The smallest unit constituting the circuit layer structure 14 is at least one dielectric layer and at least one circuit layer. Those with ordinary knowledge in the technical field of the present invention can flexibly select the number of dielectric layers and circuit layers according to actual needs. In this embodiment, the circuit layer structure 14 will include two dielectric layers (first dielectric layer 108 and second dielectric layer 208) and two circuit layers (first circuit layer 110 and second circuit layer 210) ) As an example.

First, as shown in FIG. 1D, a first dielectric layer 108 is formed on the embedded wafer substrate 12, wherein each first dielectric layer 108 has a plurality of first conductive blind holes 108H. The material of the first dielectric layer 108 may include resin and glass fiber. The resin may be phenolic resin, epoxy resin, polyimide resin or polytetrafluoroethylene. Alternatively, the material of the first dielectric layer 108 may also include a photosensitive dielectric material (Photoimageable Dielectric, PID). The method for forming the first dielectric layer 108 may be, for example, lamination. The forming method of the first conductive blind hole 108H includes, but is not limited to, laser ablation of the first dielectric layer 108, or the material of the first dielectric layer 108 is a photosensitive dielectric material to be exposed and developed to form the first A conductive blind hole 108H.

Please continue to refer to Figure 1D. Then, a first circuit layer 110 is formed on the first dielectric layer 108, and the first circuit layer 110 extends into the first conductive blind hole 108H, so that the first circuit layer 110 is electrically connected through the first conductive blind hole 108H The electrode pad 120P. The forming method of the first circuit layer 110 may be, for example, first: forming a photoresist layer (not shown) such as a dry film on the first dielectric layer 108, and then patterning the photoresist layer through a lithography process to expose a portion of the photoresist layer A dielectric layer 108, followed by an electroplating process and a photoresist layer removal process to form the first circuit layer 110. The material of the first circuit layer 110 may be copper, for example.

In some embodiments, before forming the first circuit layer 110, a seed layer may be formed on the first dielectric layer 108. The seed layer may be a single-layer structure or a multi-layer structure composed of sub-layers of different materials, for example, it may be a metal layer including a titanium layer and a copper layer on the titanium layer. The method for forming the seed layer includes, but is not limited to, a physical method, such as sputtering titanium copper, or a chemical method, such as electroless palladium copper plus electroplated copper.

Next, as shown in FIG. 1E, a second dielectric layer 208 is formed on the first dielectric layer 108 and the first circuit layer 110, wherein the second dielectric layer 208 has a plurality of second conductive blind holes 208H. Then, a second circuit layer 210 is formed on the second dielectric layer 208, and the second circuit layer 210 extends to the second conductive blind hole 208H In this way, the second circuit layer 210 is electrically connected to the first circuit layer 110 through the second conductive blind hole 208H.

In this way, the circuit layer structure 14 is formed on the embedded chip substrate 12, wherein the circuit layer structure 14 includes the first dielectric layer 108, the first circuit layer 110, the second dielectric layer 208 and the second circuit layer 210. The first dielectric layer 108 has a plurality of first conductive blind holes 108H, and the first circuit layer 110 is electrically connected to the electrode pad 120P through the first conductive blind holes 108H. The second dielectric layer 208 has a plurality of second conductive blind holes 208H, and the second circuit layer 210 is electrically connected to the first circuit layer 110 through the second conductive blind holes 208H. That is to say, the circuit layer structure 14 includes at least one dielectric layer (first dielectric layer 108, second dielectric layer 208) and at least one circuit layer (first circuit layer 110, second circuit layer 210), each of which is The electrical layer has a plurality of conductive blind holes (first conductive blind hole 108H, second conductive blind hole 208H), each circuit layer is located on each dielectric layer, and extends into the conductive blind hole, and the bottommost circuit layer ( The first circuit layer 110) is electrically connected to the electrode pad 120P through a conductive blind hole (first conductive blind hole 108H).

The method and material for forming the second dielectric layer 208, the second circuit layer 210, and the second conductive blind hole 208H can be, for example, the same as those of the first dielectric layer 108, the first circuit layer 110, and the first conductive blind hole 108H, respectively. The forming method is the same as the material, and will not be described here. In addition, before the second circuit layer 210 is formed, the aforementioned seed layer may also be formed on the second dielectric layer 208, which will not be repeated here.

Please continue to refer to Figure 1E. Then, an insulating protective layer 112 is formed on the circuit layer structure 14, wherein each insulating protective layer 112 has a plurality of openings 112O, so that a part of the surface of the circuit layer structure 14 is exposed in the opening 112O. Specifically, as shown in FIG. 1E, the second circuit layer of the outermost layer of the circuit layer structure 14 Part of the surface of 210 is exposed in the opening 112O.

The material of the insulating protection layer 112 may be a solder-proof material or a resin material, such as epoxy resin. Alternatively, the material of the insulating protection layer 112 may also be the same as the material of the first dielectric layer 108 or the second dielectric layer 208 described above. The method for forming the insulating protective layer 112 can be bonding, printing, or coating.

Next, as shown in FIG. 1F, the support layer 100 and the peeling layer 102 are removed to form two package substrates 16. Therefore, compared to the conventional single-sided fabrication, warpage is likely to occur due to the asymmetry of the structure. In this embodiment, the same process is performed on the two opposite surfaces 100A, 100B of the support layer 100 to form two packages that are symmetrical up and down. The substrate 16 can avoid warping at both ends of the support layer 100, so as to improve the reliability of the overall packaging structure.

Finally, as shown in FIG. 1G, the packaging substrate 16 is cut to obtain a plurality of packaging structures 18. It can be seen that if each package substrate 16 can generate N package structures 18, the two package substrates 16 formed by the manufacturing method shown in FIGS. 1A to 1F can generate 2N package structures 18, which can be effectively improved The number of products produced.

In this way, the packaging structure 18 of the present embodiment is completed, which includes the metal layer 104, the composite layer 106 of the non-conducting inorganic material and the organic material, the sealant 122, the wafer 120, the circuit layer structure 14, and the insulating protection layer 112. The composite layer 106 of the non-conductor inorganic material and the organic material is disposed on the metal layer 104. The sealant 122 is bonded to the composite layer 106 of the non-conductive inorganic material and the organic material. The chip 120 is embedded in the sealant 122, and the chip 120 has a plurality of electrode pads 120P, and the electrode pads 120P are exposed to the sealant 122. The circuit layer structure 14 is formed on the sealant 122 and the wafer 120. The circuit layer structure 14 includes at least one dielectric layer and At least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the circuit layer is located on the dielectric layer and extends into the conductive blind holes, and the bottommost circuit layer is electrically connected to the electrode pad 120P through the conductive blind holes. The insulating protection layer 112 is formed on the circuit layer structure 14. The insulating protection layer 112 has a plurality of openings 112O, so that part of the surface of the circuit layer structure 14 is exposed in the openings 112O.

The packaging structure 18 and its manufacturing method of the present invention form the packaging substrate 16 on the composite layer 106 of non-conducting inorganic material and organic material, that is, the composite layer 106 of non-conducting inorganic material and organic material can be regarded as a reinforcement The layer has a higher hardness than the normal dielectric layer and encapsulation material. Therefore, the packaging structure 18 and its manufacturing method of the present invention can strengthen the overall structural strength through the composite layer 106 of non-conducting inorganic materials and organic materials to prevent the warpage of the carrier board, thereby not only improving the yield of the process, The reliability of the packaging structure 18 can also be improved.

Not only that, since the bottom of the packaging structure 18 has a metal layer 104, the heat energy generated by the chip 120 can be eliminated by the conduction of the metal layer 104, thereby achieving the effect of heat dissipation.

2A to 2B are cross-sectional views of partial steps of a method for manufacturing a package structure 18A according to another embodiment of the present invention. FIG. 3 is a cross-sectional view of the package structure 18A obtained according to the manufacturing method of FIGS. 2A-2B. The manufacturing method of the packaging structure 18A of this embodiment is similar to the manufacturing method of the packaging structure 18 described above. The difference between the two is that the step of combining the embedded wafer substrate 12 on the composite layer 106 of non-conducting inorganic material and organic material further includes The sub-step of grinding the bottom surface 122S of the sealant to expose the bottom surface 120S of the wafer.

Please refer to Figure 2A and Figure 1C at the same time. This embodiment and The difference in the steps shown in FIG. 1C is that before the embedded wafer substrate 12 is bonded to the composite layer 106 of non-conductive inorganic and organic materials, the bottom surface 122S of the sealant is polished to the exposed bottom surface 120S of the wafer to form a polish The wafer substrate 12A is embedded afterwards. The method of grinding the bottom surface 122S of the sealant may be, for example, chemical-mechanical polishing (CMP).

Next, as shown in FIG. 2B, the polished embedded wafer substrate 12A is bonded to the composite layer 106 of a non-conductive inorganic material and an organic material. That is to say, when the polished embedded wafer substrate 12A is bonded to the composite layer 106 of non-conductive inorganic material and organic material, the bottom surface 120S of the wafer is exposed to the sealant 122.

Here, the method of combining the polished embedded wafer substrate 12A on the composite layer 106 of non-conducting inorganic material and organic material can be performed by, for example, an adhesive layer (not shown). For specific steps, refer to the previous embodiment. I will not repeat them here.

Then, following the steps in FIGS. 1D to 1G, the package structure 18A shown in FIG. 3 can be obtained. In this embodiment, since the bottom surface 120S of the wafer is exposed to the sealant 122, the metal layer 104 can more effectively conduct the heat energy generated by the wafer 120, further improving the heat dissipation effect, and also reducing the thickness of the packaging structure 18A For the thin design of the product.

From the above detailed description of the specific embodiments of the present invention, it can be clearly seen that the packaging structure and manufacturing method of the present invention form a packaging substrate on a composite layer of non-conducting inorganic material and organic material, that is, The composite layer of non-conducting inorganic material and organic material is regarded as a strengthening layer, which has a higher hardness than the general dielectric layer and encapsulation material. Therefore, the packaging structure and manufacturing method of the present invention can pass through the recombination of non-conducting inorganic materials and organic materials The layer strengthens the overall structural strength to prevent the carrier board from warping, which can not only improve the yield of the process, but also improve the reliability of the packaging structure.

Although the present invention has been disclosed as above in an embodiment, it is not intended to limit the present invention. Any person skilled in this art can make various changes and modifications within the spirit and scope of the present invention, so the protection of the present invention The scope shall be determined by the scope of the attached patent application.

Claims (10)

An encapsulation structure includes: a metal layer; a composite layer of non-conductor inorganic material and organic material, disposed on the metal layer; a sealant, bonded to the composite layer of non-conductor inorganic material and organic material, wherein the seal One surface of the composite layer bonded to the non-conductor inorganic material and the organic material is completely covered by the composite layer of the non-conductor inorganic material and the organic material; Some electrode pads are exposed on the sealant; a circuit layer structure is formed on the sealant and the chip, wherein the circuit layer structure includes at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blinds Hole, the circuit layer is located on the dielectric layer and extends into the conductive blind holes, and the bottommost circuit layer is electrically connected to the electrode pads through the conductive blind holes; and an insulating protective layer , Formed on the circuit layer structure, wherein the insulating protective layer has a plurality of openings, so that part of the surface of the circuit layer structure is exposed in the openings. The packaging structure according to claim 1, wherein the chip has a bottom surface of the chip, and the bottom surface of the chip is exposed to the sealing compound. The packaging structure according to any one of claims 1 to 2, wherein the material of the composite layer of the non-conductor inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material. The packaging structure according to claim 3, wherein the ceramic material includes zirconia, alumina, silicon nitride, silicon carbide, silicon oxide, or a combination of the foregoing, and the polymer material includes epoxy resin, polyimide, Liquid crystal polymer, methacrylate resin, vinyl phenyl resin, allyl resin, polyacrylate resin, polyether resin, polyolefin resin, polyamine resin, polysiloxane resin Or a combination of the foregoing. The packaging structure according to claim 1, wherein the composite layer of the non-conductor inorganic material and the organic material is a pearl-like layer. A manufacturing method of a packaging structure includes: providing a carrier board, the carrier board including a support layer having two opposite surfaces, a peeling layer disposed on each of the two surfaces, and one disposed on each of the peeling layers A metal layer; disposing a composite layer of non-conducting inorganic material and organic material on each of the metal layers; combining a embedded wafer substrate on each composite layer of non-conducting inorganic material and organic material, in which each of these is embedded The embedded chip substrate includes a plurality of chips and a sealant, the chips are embedded in the sealant, and each of the chips has a plurality of electrode pads, the electrode pads are exposed to the sealant; forming a circuit layer structure in Each of the embedded chip substrates, wherein each of the circuit layer structures includes at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the circuit layer is located on the dielectric layer, and Extending into the conductive blind holes, and the bottommost circuit layer is electrically connected to the electrode pads through the conductive blind holes; forming an insulating protective layer on each of the circuit layer structures, each of which The edge protection layer has a plurality of openings, so that part of the surfaces of the circuit layer structures are exposed in the openings; removing the supporting layer and the peeling layers to form two package substrates; and cutting each of the package substrates, to A plurality of packaging structures are obtained. The manufacturing method according to claim 6, wherein each of the sealants has a bottom surface of the sealant, and each of the wafers has a bottom surface of the wafer, wherein the embedded wafer substrates are combined with the non-conductive inorganic materials and the organic The steps on the composite layer of materials include: grinding the bottom surface of the sealant to expose the bottom surface of the wafer to form a polished embedded wafer substrate; and combining the polished embedded wafer substrate with each of the non-conducting inorganic materials On the composite layer with organic materials. The manufacturing method according to any one of claims 6 to 7, wherein the material of the composite layer of each of the non-conductor inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material. The manufacturing method according to claim 8, wherein the ceramic material includes zirconia, alumina, silicon nitride, silicon carbide, silicon oxide, or a combination of the foregoing, and the polymer material includes epoxy resin, polyimide, Liquid crystal polymer, methacrylate resin, vinyl phenyl resin, allyl resin, polyacrylate resin, polyether resin, polyolefin resin, polyamine resin, polysiloxane resin Or a combination of the foregoing. The manufacturing method according to claim 6, wherein the composite layer of each of the non-conductor inorganic material and the organic material is a pearl-like layer.