TWI713185B - Package structure and manufacturing method thereof - Google Patents

Abstract

A package structure includes a metal layer, an insulating composite layer, a sealant, a chip, a circuit layer structure, and a protective layer. The insulating composite layer is disposed on the metal layer. The sealant is bonded to the insulating composite layer. The chip is embedded in the sealant and has a plurality of conductive pads exposed from the sealant. The circuit layer structure is formed on the sealant and the chip. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has a plurality of conductive vias. The dielectric layer and the sealant are made of the same material. The circuit layer is located on the dielectric layer and extends to conductive via, and the bottommost circuit layer is electrically connected to the conductive pads through the conductive vias. The protective layer is formed on the circuit layer structure. The protective layer has a plurality of openings, which expose a portion of surface of the circuit layer structure.

Description

Packaging structure and manufacturing method thereof

The invention relates to a packaging structure and a manufacturing method thereof.

With the evolution of semiconductor packaging technology, in addition to the traditional wire bonding semiconductor packaging technology, the current semiconductor device (Semiconductor device) has developed different packaging types, such as directly embedded and integrated in the package substrate. Electrically integrate semiconductor chips with integrated circuits to reduce the overall volume and improve electrical functions.

In order to meet the requirements of shortening the length of the wire and reducing the overall structure thickness, and in response to the trend of high frequency and miniaturization, a method for processing embedded chip substrates on a coreless carrier board has been developed. However, the bearing plate without the core layer lacks a hard core plate for support, resulting in insufficient strength, and therefore the overall structure is prone to warpage.

In view of this, one purpose of the present invention is to provide a package structure and a manufacturing method thereof that can solve the above-mentioned problems.

In order to achieve the above objective, one aspect of the present invention is to provide a Kind of packaging structure. The package structure includes a metal layer, an insulating composite layer, a sealing compound, a chip, a circuit layer structure, and a protective layer. The insulating composite layer is configured on the metal layer. The sealant is bonded to the insulating composite layer. The chip is embedded in the sealing compound. The chip has a plurality of electrode pads, and the electrode pads are exposed outside the sealing compound. The circuit layer structure is formed on the sealing compound and the wafer. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has a plurality of conductive blind holes. The dielectric layer and the sealing compound have the same material composition. The circuit layer is located on the dielectric layer and extends into the conductive blind hole, and the bottom circuit layer is electrically connected to the electrode pad through the conductive blind hole. The protective layer is formed on the circuit layer structure. The protective layer has a plurality of openings, so that part of the surface of the circuit layer structure is exposed in the openings.

According to one or more embodiments of the present invention, the materials of the dielectric layer and the molding compound include resin, glass fiber, and photosensitive dielectric material.

According to one or more embodiments of the present invention, the resin includes phenolic resin, epoxy resin, polyimide resin, and polytetrafluoroethylene.

According to one or more embodiments of the present invention, the chip has a bottom surface of the chip, and the bottom surface of the chip is exposed from the encapsulant.

According to one or more embodiments of the present invention, the insulating composite layer includes a composite material, and the composite material includes an insulating inorganic material and an organic material.

According to one or more embodiments of the present invention, the insulating composite layer is an imitation pearl layer.

Another aspect of the present invention is to provide a manufacturing method of a package structure, including the following steps: providing a carrier board, the carrier board includes a support layer, a first peeling layer, a second peeling layer and a plurality of metal layers, the first peeling layer and The second peeling layer is respectively configured on two opposite surfaces of the support layer, and the metal layer is configured on the first peeling On the separation layer and the second peeling layer; disposing an insulating composite layer on each metal layer; combining an embedded chip substrate on each insulating composite layer, wherein each embedded chip substrate includes a chip and a sealant, and the chip is embedded In the encapsulant, and the chip has a plurality of electrode pads, and the electrode pads are exposed outside the encapsulant; forming a circuit layer structure on each embedded chip substrate, wherein each circuit layer structure includes at least one dielectric layer and at least one circuit layer, The dielectric layer has a plurality of conductive blind holes, the dielectric layer and the encapsulant have the same material composition, the circuit layer is located on the dielectric layer and extends into the conductive blind holes, and the circuit layer is electrically connected to the conductive blind vias Electrode pad; forming a protective layer on the circuit layer structure, wherein the protective layer has a plurality of openings, so that part of the surface of the circuit layer structure is exposed in the openings; remove the support layer, the first peeling layer and the second peeling layer to form Two packaging substrates; and cutting the packaging substrate to obtain multiple packaging structures.

According to one or more embodiments of the present invention, the step of arranging the embedded chip substrate on the insulating composite layer includes: grinding a bottom surface of the encapsulant embedded in the chip substrate to a bottom surface of the exposed chip to form a polished Embedded chip substrate; and arranging the polished embedded chip substrate on the insulating composite layer.

According to one or more embodiments of the present invention, the materials of the dielectric layer and the molding compound include resin, glass fiber, and photosensitive dielectric material.

According to one or more embodiments of the present invention, the resin includes phenolic resin, epoxy resin, polyimide resin, and polytetrafluoroethylene.

10‧‧‧Method

100‧‧‧Packaging substrate

100A‧‧‧Packaging structure

100B‧‧‧Packaging structure

110‧‧‧Carrier plate

112‧‧‧Support layer

114‧‧‧First peeling layer

116‧‧‧Second peeling layer

118‧‧‧Metal layer

120‧‧‧Insulation composite layer

130‧‧‧Sealant

130S‧‧‧Bottom

140‧‧‧chip

140a‧‧‧First surface

140b‧‧‧Second surface (bottom surface)

142‧‧‧Chip substrate

144‧‧‧electrode pad

150‧‧‧First circuit layer structure

152‧‧‧First dielectric layer

152a‧‧‧The first conductive blind hole

154‧‧‧First circuit layer

20‧‧‧embedded chip substrate

250‧‧‧Second circuit layer structure

252‧‧‧Second dielectric layer

252a‧‧‧Second conductive blind hole

254‧‧‧Second circuit layer

160‧‧‧Protection layer

162‧‧‧Open

CL‧‧‧Tangling

S01~S07‧‧‧Step

In order to make the above and other objectives, features, advantages and embodiments of the present invention more comprehensible, the description of the accompanying drawings is as follows: Figure 1 shows a flowchart of a manufacturing method of a package structure according to an embodiment of the present invention.

Figures 2-9 show schematic cross-sectional views of each process stage in the manufacturing method of one embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view of a package structure according to another embodiment of the present invention.

Hereinafter, a number of embodiments of the present invention will be disclosed in the form of drawings. For clear description, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventionally used structures and elements will be shown in a simple schematic manner in the drawings.

One aspect of the present invention is to provide a manufacturing method of a package structure. The package structure obtained by the manufacturing method has high structural strength and can prevent warping of the carrier board, thereby improving the process yield and the package structure The reliability. FIG. 1 shows a flowchart of a manufacturing method 10 of a package structure 100 according to an embodiment of the present invention, and FIGS. 2-9 show schematic cross-sectional views of each process stage in the method 10. As shown in Figure 1, the method 10 includes steps S01 to S07.

Step S01 is executed first. As shown in Figure 2, a carrier plate 110 is provided. Specifically, the carrier board 110 includes a supporting layer 112, a first peeling layer 114, a second peeling layer 116 and a plurality of metal layers 118. The first peeling layer 114 and the second peeling layer 116 are respectively disposed on two opposite surfaces of the supporting layer 112, and the metal layer 118 is disposed on the first peeling layer 114 and the second peeling layer 116. In some embodiments, the material of the support layer 112 can be, for example, an organic polymer material such as bismaleimide triazine (Bismaleimide triazine, BT), and the support layer 112 can also have two opposite surfaces. Copper Clad Laminate (CCL) (not shown in the figure) integrated with a dielectric material (for example, prepreg). In some embodiments, the first release layer 114 and the second release layer 116 may each be a release film, or other technologies may be used to provide the release layer 114/116, such as: Mitsui, Nippon-Denk, Furukawa, or Olin and other companies provide copper foil bonding peeling layer and other materials. In some embodiments, the thickness of the metal layer 118 can be selected from the range of 1 micron to 10 microns, but is not limited thereto, and the material of the metal layer 118 can be, for example, copper, aluminum, nickel, silver, gold or alloys thereof. , But not limited to this. In other embodiments, the metal layer 118 is not limited to a single layer, and may also be a stack of multiple metal layers 118.

In some other embodiments, another metal layer (not shown) may also be included between the two opposite surfaces of the support layer 112 and the first peeling layer 114 or the second peeling layer 116. The thickness of the above-mentioned another metal layer may be 5 μm to 40 μm, and the material may be the same or different from that of the metal layer 118, for example, it may be copper, aluminum, nickel, silver, gold or alloys thereof, but is not limited thereto.

Then step S02 is executed. As shown in FIG. 3, the insulating composite layer 120 is disposed on the metal layer 118. It can be understood that step S02 and subsequent steps S03 to S07 can be formed on a certain surface of the carrying board 110 or on two opposite surfaces of the carrying board 110. In this embodiment, the double-sided fabrication of the carrier plate 110 will be described as an example. In various embodiments, the insulating composite layer 120 includes a composite material, and the composite material includes an insulating inorganic material. Materials and organic materials. Furthermore, the insulating inorganic material can be a ceramic material, such as zirconia, silicon carbide, silicon nitride, aluminum oxide, silicon oxide, or a combination of the foregoing, and the organic material can be a polymer material, such as epoxy, poly Amide, liquid crystal polymer, methacrylate type resin, polyacrylate type resin, allyl type resin, vinyl phenyl type resin, polysiloxane type resin, polyolefin type resin, polyamine type resin, Polyether resin or a combination of the foregoing. In an embodiment, the ceramic material may be ceramic laminates, ceramic powder, ceramic micro-particles or ceramic nano-particles, etc., but the ceramic material in this embodiment is not limited to this.

In the ceramic powder embodiment, the manufacturing method of the insulating composite layer 120 can use vacuum impregnation technology to impregnate polymer materials in the ceramic powder to prepare an insulating composite layer composed of a composite material composed of ceramic powder and polymer materials. 120. In the embodiment where the polymer material is a photosensitive resin composition of epoxy resin and imine resin, for example, the insulating composite layer 120 is disposed on the insulating composite layer 120 by means of thermocompression bonding or vacuum immersion followed by irradiation of ultraviolet light and heating. On the metal layer 118.

In the ceramic layer embodiment, the insulating composite layer 120 can be, for example, an imitation nacreous layer. The method of making the insulating composite layer 120 can use vacuum impregnation technology to impregnate the polymer material into the ceramic layer to prepare a ceramic layer. The insulating composite layer 120 is composed of a composite material composed of a laminate and a polymer material. However, the manufacturing method of the insulating composite layer 120 of the present embodiment is not limited to this, and other methods that can make the polymer material and the ceramic material form a composite material can also be used. In the ceramic laminate embodiment, in more detail, the insulating composite layer 120 includes a composite composition of organic and inorganic substances (for example, high-score The composite composition of the sub-material and the ceramic layer), based on the adhesion of organic matter to inorganic matter, the ceramic layer of the insulating composite layer 120 has a microscopic laminated structure arranged in a sheet, brick or combination arrangement. This arrangement suppresses the transverse fracture force The conduction, and then significantly increase its hardness. In this way, the material is stronger and has a higher elastic modulus, which can increase the strength of the ceramic and improve the brittleness of the ceramic, while having excellent toughness.

Here, the Young's coefficient of the insulating composite layer 120 is, for example, between 20 GPa and 100 GPa. Compared with the conventionally used dielectric layer (whose Young's coefficient is not more than 10 GPa) and packaging materials (whose Young's coefficient is not more than 20 GPa), the insulating composite layer 120 of this embodiment has excellent hardness and can be effective Strengthen the structural strength of the package structure.

Step S03 is executed. Referring to FIG. 4, the embedded chip substrate 20 is bonded to the insulating composite layer 120. Specifically, the embedded chip substrate 20 may be respectively disposed on two opposite surfaces of the insulating composite layer 120 on both sides. The embedded chip substrate 20 includes an encapsulant 130 and a chip 140. The chip 140 is embedded in the encapsulant 130 and has a first surface 140a and a second surface 140b opposite to the first surface 140a. The chip 140 includes a chip substrate 142 and a plurality of electrode pads 144. In various embodiments, the electrode pad 144 is exposed on the first surface 140 a, and the second surface 140 b is covered by the sealing compound 130. It is worth noting that the electrode pad 144 is also exposed from the sealing compound 130. The chip 140 can be, for example, an active element or a passive element, an electronic cormponents such as an integrated circuit such as a digital circuit or an analog circuit, an embedded chip module (ECM), a dynamic random access Memory (DRAM) components, static random access memory (SRAM) components, optoelectronic components (opto electronic devices), Micro Electro Mechanical Systems (MEMS), micro fluidic systems, or physical sensors that use changes in physical quantities such as heat, light, and pressure to measure, and radio frequency components (RF Circuits, accelerators, gyroscopes, micro actuators, surface acoustic wave components, pressure sensors, etc., but not limited to these. The chip 140 in FIG. 4 is only for illustration, and the actual length, width, and height are adjusted according to product requirements, and not limited to this.

In various embodiments, the material of the sealant 130 may include resin and glass fiber. For example, the resin may be phenolic resin, epoxy resin, polyimide resin or polytetrafluoroethylene. Alternatively, the material of the encapsulant 130 may also include Photo-imageable Dielectric.

In some embodiments, the method of bonding the embedded chip substrate 20 on the insulating composite layer 120 can be performed by, for example, an adhesive layer (not shown). Specifically, the adhesive layer can be adhered to the bottom surface 20S of the embedded chip substrate 20 first, and then the embedded chip substrate 20 is bonded to the insulating composite layer 120. In one embodiment, the above-mentioned adhesive layer may include a heat dissipation agent with strong heat dissipation or high temperature resistance, but the invention is not limited thereto.

Step S04 is executed. Referring to FIG. 5, a first circuit layer structure 150 is formed on the embedded chip substrate 20. The first circuit layer structure 150 includes at least one first dielectric layer 152 and at least one first circuit layer 154. It can be understood that the minimum unit constituting the circuit layer structure 150 is a dielectric layer and a circuit layer. Those skilled in the art to which the present invention belongs can flexibly select the number of dielectric layers and circuit layers according to actual needs. The first dielectric layer 152 has more One first conductive blind hole 152a. The first circuit layer 154 is located on the first dielectric layer 152 and is connected to or extends into the first blind conductive hole 152a. The bottom first circuit layer 154 is electrically connected to the electrode pad 144 through the first conductive blind hole 152a.

In various embodiments, the material of the first dielectric layer 152 may include resin and glass fiber. For example, the resin may be phenolic resin, epoxy resin, polyimide resin or polytetrafluoroethylene. Alternatively, the material of the first dielectric layer 152 may also include a photosensitive dielectric material (Photo-imageable Dielectric). It is worth noting that in the present invention, the encapsulant 130 and the first dielectric layer 152 have the same material composition. Compared with the traditional technique in which the molding compound and the dielectric layer are made of heterogeneous materials, the present invention can avoid cross-sections between the contact surfaces of the heterogeneous materials by making the molding compound 130 and the first dielectric layer 152 have the same material composition. The resulting uneven tension problem increases the strength of the overall structure, so that when the embedded chip substrate is processed in the subsequent manufacturing process, the package structure is not prone to warpage.

In some embodiments, the method of forming the first dielectric layer 152 may be, for example, lamination, coating, or other suitable processes. In some embodiments, the method for forming the blind holes required to make the first conductive blind hole 152a includes, but is not limited to, using laser ablation to form the blind hole on the first dielectric layer 152, or as the first When a photosensitive dielectric material is selected as the material of the dielectric layer 152, exposure and development are used to form blind holes for making the first conductive blind holes 152a.

In some embodiments, the method of forming the first circuit layer 154 includes, but is not limited to, first forming a photoresist layer (not shown), such as a dry film, on the first dielectric layer 152, and then resisting the photoresist through a photolithography process. Layer is patterned to A portion of the first dielectric layer 152 is exposed. Then, an electroplating process is performed to form the first circuit layer 154. The patterned photoresist layer is then removed. In an embodiment, the material of the first circuit layer 154 and the first blind conductive via 152a may be copper, for example. In other embodiments, a seed layer (not shown) may be formed on the first dielectric layer 152 before forming the first circuit layer 154. The seed layer may be a single-layer structure or a multi-layer structure composed of sub-layers of different materials. For example, it may be a metal layer including a titanium layer and a copper layer on the titanium layer. The method for forming the seed layer includes, but is not limited to, physical methods, such as sputtering titanium copper, or chemical methods, such as electroplating palladium copper plus electroplating copper.

It is worth noting that, as shown in FIG. 6, in other embodiments, the method 10 may also include forming a second circuit layer structure 250 on the embedded chip substrate 20. Specifically, the second circuit layer structure 250 includes at least one second dielectric layer 252 and at least one second circuit layer 254. The second dielectric layer 252 has a plurality of second conductive blind holes 252a. The second circuit layer 254 is located on the second dielectric layer 252 and is connected or extends into the second blind conductive hole 252a, and the bottom second circuit layer 254 is electrically connected to the electrode pad through the second blind conductive hole 252a 144. It is understandable that the minimum number of layers constituting the second circuit layer structure 250 is a dielectric layer and a circuit layer. Those skilled in the art to which the present invention pertains can flexibly choose the dielectric layer and the circuit layer according to actual needs. Number of layers.

The formation method and material of the second dielectric layer 252, the second circuit layer 254, and the second conductive blind hole 252a can be compared with the aforementioned first dielectric layer 152, the first circuit layer 154, and the first conductive blind hole 152a, respectively. The forming method and the material are the same, so I will not repeat them here. In other words, in the present invention, the sealant 130, the first dielectric layer 152 and the second dielectric layer 252 may have the same material composition.

Then step S05 is executed. As shown in FIG. 7, a protective layer 160 is formed on the second circuit layer structure 250. The protection layer 160 has a plurality of openings 162 such that part of the surface of the second circuit layer structure 250 is exposed in the openings 162. Specifically, as shown in FIG. 9, part of the surface of the second circuit layer 254 of the outermost layer of the second circuit layer structure 250 is exposed in the opening 162. In many embodiments, the material of the protective layer 160 may be a solder mask material, or a resin material, such as epoxy resin. Alternatively, the material of the protective layer 160 can also be the same as the material of the first dielectric layer 152 or the second dielectric layer 252 described above. The formation method of the protective layer 160 may be, for example, laminating, printing or coating.

Then, step S06 is executed. As shown in FIG. 8, the support layer 112, the first peeling layer 114 and the second peeling layer 116 are removed to form two packaging structures 100. Therefore, compared with the traditional single-sided manufacturing, which is prone to warping due to the asymmetry of the structure, the method 10 of the present invention simultaneously performs the same process on the opposite surfaces of the support layer 112 to form two symmetrical top and bottom surfaces. The packaging structure 100 can avoid warping at both ends of the support layer 112, thereby improving the reliability of the overall packaging structure. Moreover, since the bottom of the package structure 100 has a metal layer 118, the heat generated by the chip 140 can be removed by the conduction of the metal layer 118, thereby achieving the effect of heat dissipation.

Next, step S07 is executed. As shown in FIG. 9, each package substrate 100 is cut to obtain a plurality of package structures 100A. In some embodiments, the method of cutting each package substrate 100 includes following the cut line CL in FIG. 8 Each package substrate 100 is cut to obtain a plurality of package structures 100A. It should be understood that if each package substrate 100 can produce N package structures 100A, the two package substrates 100 formed by the above-mentioned manufacturing method 10 can produce 2N package structures 100A, which can effectively improve product production. Quantity.

Another aspect of the present invention is to provide a package structure. FIG. 9 is a schematic cross-sectional view of a package structure 100A according to an embodiment of the present invention. The packaging structure 100A includes a metal layer 118, an insulating composite layer 120, an encapsulant 130, a chip 140, a first circuit layer structure 150 and a protective layer 160. The insulating composite layer 120 is disposed on the metal layer 118. The sealant 130 is bonded to the insulating composite layer 120. The chip 140 is embedded in the sealing compound 130. The chip 140 has a plurality of electrode pads 144, and the electrode pads 144 are exposed from the encapsulant 130. The first circuit layer structure 150 is formed on the encapsulant 130 and the chip 140. The first circuit layer structure 150 includes at least one first dielectric layer 152 and at least one first circuit layer 154. The first dielectric layer 152 has a plurality of first conductive blind holes 152a. The first dielectric layer 152 and the encapsulant 130 have the same material composition. The first circuit layer 154 is located on the first dielectric layer 152 and extends into the first blind conductive hole 152a, and the bottom first circuit layer 154 is electrically connected to the electrode pad 144 through the first blind conductive hole 152a. It can be understood that the minimum number of layers constituting the first circuit layer structure 150 is a dielectric layer and a circuit layer. Those skilled in the art to which the present invention belongs can flexibly choose the dielectric layer and the circuit layer according to actual needs. Number of layers. The protection layer 160 is formed on the first circuit layer 154 structure. The protection layer 160 has a plurality of openings 162 such that part of the surface of the first circuit layer 154 structure is exposed in the openings 162.

The formation method and material of the metal layer 118, the insulating composite layer 120, the encapsulant 130, the chip 140, the first circuit layer structure 150, and the protective layer 160 It has been clearly described above and will not be repeated here. It is worth noting that in the present invention, the encapsulant 130 and the first dielectric layer 152 have the same material composition. Compared with the traditional technique in which the molding compound and the dielectric layer are made of heterogeneous materials, the present invention can avoid cross-sections between the contact surfaces of the heterogeneous materials by making the molding compound 130 and the first dielectric layer 152 have the same material composition. The resulting uneven tension problem increases the strength of the overall structure, so that when the embedded chip substrate is processed in the subsequent manufacturing process, the package structure is not prone to warpage.

In other embodiments, the package structure 100A includes a second circuit layer structure 250. The second circuit layer structure 250 is located above the embedded chip substrate 20. The second circuit layer structure 250 includes at least one second dielectric layer 252 and at least one second circuit layer 254. The second dielectric layer 252 has a plurality of second conductive blind holes 252a. The second circuit layer 254 is located on the second dielectric layer 252 and is connected or extends into the second blind conductive hole 252a, and the bottom second circuit layer 254 is electrically connected to the electrode pad through the second blind conductive hole 252a 144. It is understandable that the minimum number of layers constituting the second circuit layer structure 250 is a dielectric layer and a circuit layer. Those skilled in the art to which the present invention pertains can flexibly choose the dielectric layer and the circuit layer according to actual needs. Number of layers. The encapsulant 130, the first dielectric layer 152, and the second dielectric layer 252 may have the same material composition.

FIG. 10 is a schematic cross-sectional view of a package structure 100B according to another embodiment of the present invention. The manufacturing method of the package structure 100B of this embodiment is similar to the manufacturing method of the package structure 100A described above. The difference between the two is that in step S03 shown in FIG. 4, when the embedded chip substrate 20 is bonded to the insulating composite layer 120 , Further including the following sub-steps: grinding a bottom surface 130S of the sealing compound 130 to expose a bottom surface (second surface) 140b of the wafer 140; and configuring the polished The embedded chip substrate 20 is embedded on the insulating composite layer 120 to form a ground embedded chip substrate 12A. The method of polishing the bottom surface 130S of the sealant includes, but is not limited to, Chemical-Mechanical Polishing (CMP). The method of bonding the polished embedded wafer substrate 12A to the insulating composite layer 120 includes, but is not limited to, disposing an adhesive layer (not shown) between the polished embedded wafer substrate 12A and the insulating composite layer 120.

It is worth noting that in the package structure 100B of this embodiment, since the bottom surface (second surface) 140b of the chip is exposed from the encapsulant 130, not only the metal layer 118 can more effectively conduct the heat generated by the chip 140, thereby further The heat dissipation effect is improved, and the thickness of the packaging structure 100B is also reduced, which is conducive to the thin design of the product.

To sum up, in the packaging structure and manufacturing method of the present invention, since the molding compound, the first dielectric layer, and the second dielectric layer have the same material composition, compared with the conventional technology, the molding compound and the dielectric The layer is made of heterogeneous materials, the packaging structure of the present invention can avoid the problem of uneven tension caused by cross-sections between the contact surfaces of heterogeneous materials, thereby increasing the strength of the overall structure, so that the embedded chip substrate is processed in the subsequent manufacturing process. During processing, the package structure is not prone to warpage.

In addition, the packaging structure and its manufacturing method of the present invention form a packaging substrate on the insulating composite layer, that is, the insulating composite layer can be regarded as a strengthening layer, which has a relatively high performance compared with general dielectric layers and packaging materials. High hardness. Therefore, the packaging structure and the manufacturing method of the present invention can strengthen the overall structural strength through the insulating composite layer to prevent warping of the carrier board, thereby not only improving the process yield, but also improving the reliability of the packaging structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone who is familiar with the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be subject to the scope of the attached patent application.

100A‧‧‧Packaging structure

118‧‧‧Metal layer

120‧‧‧Insulation composite layer

130‧‧‧Sealant

140‧‧‧chip

142‧‧‧Chip substrate

144‧‧‧electrode pad

150‧‧‧First circuit layer structure

152‧‧‧First dielectric layer

152a‧‧‧The first conductive blind hole

154‧‧‧First circuit layer

20‧‧‧embedded chip substrate

250‧‧‧Second circuit layer structure

252‧‧‧Second dielectric layer

252a‧‧‧Second conductive blind hole

254‧‧‧Second circuit layer

160‧‧‧Protection layer

162‧‧‧Open

Claims (8)

A packaging structure includes: a metal layer; an insulating composite layer disposed on the metal layer; a sealant bonded to the insulating composite layer; a chip embedded in the sealant, and the chip has multiple Electrode pads, the electrode pads are exposed to the encapsulant; a circuit layer structure formed on the encapsulant and the chip, wherein the circuit layer structure includes at least one dielectric layer and at least one circuit layer, the dielectric layer It has a plurality of conductive blind holes, the dielectric layer and the sealing compound have the same material composition, and the materials of the dielectric layer and the sealing compound include resin and glass fiber or the materials of the dielectric layer and the sealing compound include A photosensitive dielectric material, the circuit layer is located on the dielectric layer and extends into the conductive blind holes, and the bottom circuit layer is electrically connected to the electrode pads through the conductive blind holes; and a The protective layer is formed on the circuit layer structure, wherein the protective layer has a plurality of openings, so that part of the surface of the circuit layer structure is exposed in the openings. The package structure according to claim 1, wherein the resin comprises phenolic resin, epoxy resin, polyimide resin and polytetrafluoroethylene. The package structure according to claim 1, wherein the chip has a chip bottom surface, and the chip bottom surface is exposed from the encapsulant. The package structure according to claim 1, wherein the insulating composite layer comprises a composite material, and the composite material comprises an insulating inorganic material And an organic material. The package structure according to claim 1, wherein the insulating composite layer is an imitation nacre layer. A method of manufacturing a package structure includes: providing a carrier board, the carrier board comprising a support layer, a first peeling layer, a second peeling layer, and a plurality of metal layers, the first peeling layer and the second peeling layer Are respectively arranged on two opposite surfaces of the support layer, and the metal layer is arranged on the first peeling layer and the second peeling layer; an insulating composite layer is arranged on each of the metal layers; an embedded chip substrate is combined with On each of the insulating composite layers, each of the embedded chip substrates includes a chip and a sealant, the chip is embedded in the sealant, and the chip has a plurality of electrode pads, and the electrode pads are exposed outside the sealant Form a circuit layer structure on each of the embedded chip substrates, wherein each of the circuit layer structure includes at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the dielectric layer and the The encapsulant has the same material composition, and the dielectric layer and the encapsulant are made of resin and glass fiber or the dielectric layer and the encapsulant include photosensitive dielectric materials, and the circuit layer is located in the dielectric layer And extend into the conductive blind holes, and the circuit layer is electrically connected to the electrode pads through the conductive blind holes; forming a protective layer on the circuit layer structure, wherein the protective layer has a plurality of openings , Making part of the surface of the circuit layer structure exposed in the openings; removing the support layer, the first peeling layer and the second peeling layer to form two packaging substrates; and The packaging substrates are cut to obtain multiple packaging structures. The method according to claim 6, wherein the step of arranging the embedded chip substrate on the insulating composite layer comprises: grinding a bottom surface of the encapsulant of the embedded chip substrate to expose a bottom surface of the chip to form A polished embedded wafer substrate; and arranging the polished embedded wafer substrate on the insulating composite layer. The method according to claim 6, wherein the resin comprises phenolic resin, epoxy resin, polyimide resin and polytetrafluoroethylene.

Images