CN112435930A - Package structure and method for manufacturing the same - Google Patents
Package structure and method for manufacturing the same Download PDFInfo
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- CN112435930A CN112435930A CN201910791239.8A CN201910791239A CN112435930A CN 112435930 A CN112435930 A CN 112435930A CN 201910791239 A CN201910791239 A CN 201910791239A CN 112435930 A CN112435930 A CN 112435930A
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- layer
- circuit
- chip
- circuit layer
- insulating composite
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Abstract
The invention discloses a packaging structure which comprises a metal layer, an insulating composite layer, a sealing compound, a chip, a circuit layer structure and a protective layer. The insulating composite layer is configured on the metal layer. The sealant is bonded on the insulating composite layer. The chip is embedded in the sealant and has a plurality of electrode pads exposed out of the sealant. The circuit layer structure is formed on the sealing compound and the chip. The circuit layer structure comprises a dielectric layer and a circuit layer. The dielectric layer has a plurality of conductive blind holes and has the same material composition as the sealing compound. The circuit layer is located on the dielectric layer and extends into the conductive blind hole, and the circuit layer at the bottommost layer is electrically connected with the electrode pad through the conductive blind hole. The protective layer is formed on the circuit layer structure. The protective layer is provided with a plurality of openings, so that part of the surface of the circuit layer structure is exposed in the openings. The packaging structure avoids the problem of uneven tension, increases structural strength and is not easy to warp.
Description
Technical Field
The invention relates to the technical field of printed circuit boards, in particular to a packaging structure and a manufacturing method thereof.
Background
With the evolution of Semiconductor packaging technology, in addition to the conventional Wire bonding (Wire bonding) Semiconductor packaging technology, different packaging types have been developed for Semiconductor devices (Semiconductor devices), such as directly embedding and electrically integrating a Semiconductor chip with an integrated circuit (ic) in a package substrate (package substrate) to reduce the overall volume and improve the electrical performance.
In order to meet the requirements of shortening the length of the conductive wire, reducing the thickness of the whole structure, and responding to the trend of high frequency and miniaturization, a method for processing the embedded chip substrate on an additional circuit board without a core layer (core) is developed. However, the additional circuit board without core layer lacks a rigid core board body for supporting, so that the strength is insufficient, and the whole structure is easy to warp (warp).
Disclosure of Invention
In view of the above, an objective of the present invention is to provide a package structure and a manufacturing method thereof, so as to solve the problem that the overall structure is easily warped due to insufficient strength caused by the lack of support of a rigid core board of an additional circuit board without a core layer.
In order to achieve the above objective, an embodiment of the present invention provides a package structure. The packaging structure comprises a metal layer, an insulating composite layer, a sealant, a chip, a circuit layer structure and a protective layer. The insulating composite layer is configured on the metal layer. The sealant is bonded on the insulating composite layer. The chip is embedded in the sealant. The chip is provided with a plurality of electrode pads, and the electrode pads are exposed out of the sealing compound. The circuit layer structure is formed on the sealing compound and the chip. The circuit layer structure comprises at least one dielectric layer and at least one circuit layer. The dielectric layer has a plurality of conductive blind vias. The dielectric layer and the molding compound have the same material composition. The circuit layer is located on the dielectric layer and extends into the conductive blind hole, and the circuit layer at the bottommost layer is electrically connected with the electrode pad through the conductive blind hole. The protective layer is formed on the circuit layer structure. The protective layer is provided with a plurality of openings, so that part of the surface of the circuit layer structure is exposed in the openings.
According to one or more embodiments of the present invention, the dielectric layer and the molding compound are made of a resin, a glass fiber, and a photosensitive dielectric material.
According to one or more embodiments of the present invention, the resin includes phenol resin, epoxy resin, polyimide resin, and polytetrafluoroethylene.
According to one or more embodiments of the present invention, the chip has a chip bottom surface exposed from the encapsulant.
According to one or more embodiments of the present invention, the insulating composite layer comprises a composite material comprising an insulating inorganic material and an organic material.
According to one or more embodiments of the present invention, the insulating composite layer is a nacreous layer.
Another embodiment of the present invention provides a method for manufacturing a package structure, comprising the steps of: providing an additional circuit board, wherein the additional circuit board comprises a support layer, a first stripping layer, a second stripping layer and a plurality of metal layers, the first stripping layer and the second stripping layer are respectively arranged on two opposite surfaces of the support layer, and the metal layers are arranged on the first stripping layer and the second stripping layer; configuring an insulating composite layer on each metal layer; embedding chip substrates are combined on the insulation composite layers, wherein each embedded chip substrate comprises a chip and sealing glue, the chip is embedded in the sealing glue, the chip is provided with a plurality of electrode pads, and the electrode pads are exposed out of the sealing glue; forming a circuit layer structure on each embedded chip substrate, wherein each circuit layer structure comprises at least one dielectric layer and at least one circuit layer, the dielectric layer is provided with a plurality of conductive blind holes, the dielectric layer and the sealing compound are made of the same material, the circuit layer is positioned on the dielectric layer and extends into the conductive blind holes, and the circuit layer is electrically connected with the electrode pad through the conductive blind holes; forming a protective layer on the circuit layer structure, wherein the protective layer is provided with a plurality of openings so that part of the surface of the circuit layer structure is exposed out of the openings; removing the support layer, the first stripping layer and the second stripping layer to form two packaging substrates; and cutting the packaging substrate to obtain a plurality of packaging structures.
According to one or more embodiments of the present invention, the step of disposing the embedded chip substrate on the insulating composite layer includes: grinding the bottom surface of the sealing glue of the embedded chip substrate to the bottom surface of the exposed chip to form a ground embedded chip substrate; and disposing the ground embedded chip substrate on the insulating composite layer.
According to one or more embodiments of the present invention, the dielectric layer and the molding compound are made of a resin, a glass fiber, and a photosensitive dielectric material.
According to one or more embodiments of the present invention, the resin includes phenol resin, epoxy resin, polyimide resin, and polytetrafluoroethylene.
In summary, the present invention has the following advantages:
in the packaging structure and the manufacturing method thereof, the sealing compound, the first dielectric layer and the second dielectric layer are made of the same material, so compared with the method that the sealing compound and the dielectric layer are made of heterogeneous materials in the prior art, the packaging structure can avoid the problem of uneven tension caused by the section between the contact surfaces of the heterogeneous materials, thereby increasing the strength of the whole structure, and ensuring that the packaging structure is not easy to warp (warp) when the embedded chip substrate is processed in the subsequent process.
In addition, the package structure and the manufacturing method thereof form the package substrate on the insulating composite layer, that is, the insulating composite layer can be used as a strengthening layer, which has higher hardness compared with the common dielectric layer and the package material. Therefore, the packaging structure and the manufacturing method thereof can strengthen the overall structural strength through the insulating composite layer to prevent the additional circuit board from warping, thereby not only improving the process yield, but also improving the reliability of the packaging structure.
Drawings
In order to make the aforementioned and other objects, features, and advantages of the invention, as well as others which will become apparent, reference is made to the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a flow chart illustrating a method for fabricating a package structure according to an embodiment of the invention;
FIGS. 2-9 are schematic cross-sectional views illustrating various stages of the manufacturing method according to one embodiment of the present invention;
fig. 10 is a schematic cross-sectional view illustrating a package structure according to another embodiment of the invention.
[ description of main element symbols ]
10 method
100 package substrate
100A packaging structure
100B packaging structure
110 additional circuit board
112 support layer
114 first release layer
116 second release layer
118 metal layer
120 insulating composite layer
130 sealing compound
130S bottom surface
140 chip
140a first surface
140b second surface (bottom surface)
142 chip substrate
144 electrode pad
150 first line layer structure
152 first dielectric layer
152a first conductive via
154 first wiring layer
20 embedded chip substrate
250 second circuit layer structure
252 second dielectric layer
252a second conductive blind via
254 second circuit layer
160 protective layer
162 opening
CL tangent line
S01-S07
Detailed Description
In the following description, for purposes of explanation, numerous implementation details are set forth in order to provide a thorough understanding of the various embodiments of the present invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such implementation details are not necessary. In addition, for the sake of simplifying the drawings, some prior art structures and elements will be shown in the drawings in a simple schematic manner.
An embodiment of the present invention provides a method for manufacturing a package structure, wherein the package structure obtained by the method has a higher structural strength, and can prevent an additional circuit board from warping, thereby improving the yield of the manufacturing process and the reliability of the package structure. Fig. 1 is a flow chart illustrating a method 10 for manufacturing a package structure 100 according to an embodiment of the invention, and fig. 2-9 are schematic cross-sectional views illustrating various stages of the method 10. As shown in fig. 1, the method 10 includes steps S01 through S07.
Step S01 is performed first. As shown in fig. 2, an additional circuit board 110 is provided. Specifically, the additional circuit board 110 includes a support layer 112, a first release layer 114, a second release layer 116, and a plurality of metal layers 118. The first peeling layer 114 and the second peeling layer 116 are disposed on two opposite surfaces of the supporting layer 112, respectively, and the metal layer 118 is disposed on the first peeling layer 114 and the second peeling layer 116. In some embodiments, the material of the supporting layer 112 may be, for example, an organic polymer material such as Bismaleimide Triazine (BT), and the supporting layer 112 may also be a Copper Clad Laminate (CCL) having a dielectric material (e.g., prepreg) bonded to the entire surface of the opposite surfaces (not shown). In some embodiments, the first release layer 114 and the second release layer 116 may each be a release film (release film), or other techniques may be used to provide the release layer 114/116, such as: mitsui, Nippon-Denk, Furukawa, Olin, or the like. In some embodiments, the thickness of the metal layer 118 may be selected from a range of 1 to 10 micrometers, but is not limited thereto, and the material of the metal layer 118 may be copper, aluminum, nickel, silver, gold, or an alloy thereof, but is not limited thereto. In other embodiments, metal layer 118 is not limited to a single layer, and may be a stack of multiple metal layers 118.
In some other embodiments, another metal layer (not shown) may be included between the opposite surfaces of the support layer 112 and the first release layer 114 or the second release layer 116. The thickness of the another metal layer may be 5 to 40 micrometers, and the material thereof may be the same as or different from the metal layer 118, such as copper, aluminum, nickel, silver, gold, or an alloy thereof, but is not limited thereto.
Step S02 is then performed. As shown in fig. 3, an insulating composite layer 120 is disposed on the metal layer 118. It is understood that the step S02 and its subsequent steps S03 to S07 may be formed on one surface of the additional circuit board 110, or may be formed on opposite surfaces of the additional circuit board 110. In the present embodiment, the double-sided production of the additional circuit board 110 will be described as an example. In various embodiments, the insulating composite layer 120 comprises a composite material, and the composite material comprises an insulating inorganic material and an organic material. Further, the insulating inorganic material may be a ceramic material, for example, including zirconia, silicon carbide, silicon nitride, alumina, silicon oxide, or a combination of the foregoing, and the organic material may be a polymer material, for example, including epoxy resin, polyimide, liquid crystal polymer, methacrylate type resin, polyacrylate type resin, allyl type resin, vinylphenyl type resin, polysiloxane type resin, polyolefin type resin, polyamine type resin, polyether type resin, or a combination of the foregoing. In an embodiment, the ceramic material may be a ceramic layer, a ceramic powder, a ceramic microparticle or a ceramic nanoparticle, but the ceramic material of the embodiment is not limited thereto.
In the embodiment of the ceramic powder, the method for manufacturing the insulating composite layer 120 may use a vacuum impregnation technique to impregnate the polymer material into the ceramic powder, so as to prepare the insulating composite layer 120 made of the composite material composed of the ceramic powder and the polymer material. In an embodiment in which the polymer material is a photosensitive resin composition of, for example, an epoxy resin and an imide resin, the insulating composite layer 120 is disposed on the metal layer 118 by, for example, thermal compression bonding or vacuum impregnation, followed by irradiation with ultraviolet light and heating.
In the embodiment of the ceramic layer, the insulating composite layer 120 may be, for example, a pearl-like layer (an insulation layer), and the manufacturing method thereof may be to impregnate the polymer material into the ceramic layer by using a vacuum impregnation technique to prepare the insulating composite layer 120 formed by the composite material of the ceramic layer and the polymer material. However, the manufacturing method of the insulating composite layer 120 of the present embodiment is not limited thereto, and other methods capable of forming a composite material of a polymer material and a ceramic material may be adopted. In the embodiment of the ceramic layer, more specifically, the insulating composite layer 120 includes a composite composition of organic and inorganic substances (e.g., a composite composition of a polymer material and a ceramic layer), and the ceramic layer of the insulating composite layer 120 has a micro-laminated structure of a sheet, a brick or a combination thereof, which inhibits the conduction of the transverse rupture force and significantly increases the hardness thereof, based on the adhesion of the organic substance to the inorganic substance. Therefore, the material is firm and has high elastic modulus, the ceramic strength can be improved, the ceramic brittleness can be improved, and meanwhile, the toughness is very good.
Here, the young's modulus of the insulating composite layer 120 is, for example, between 20GPa and 100 GPa. Compared with the dielectric layer (the young's modulus is not greater than 10GPa) and the package material (the young's modulus is not greater than 20GPa) commonly used in the prior art, the insulating composite layer 120 of the embodiment has excellent hardness, and can effectively strengthen the structural strength of the package structure.
Step S03 is executed. Referring to fig. 4, the embedded chip substrate 20 is bonded to the insulating composite layer 120. Specifically, the embedded chip substrates 20 may be disposed on two opposite surfaces of the two-sided insulating composite layer 120, respectively. The embedded chip substrate 20 includes an encapsulant 130 and a chip 140. The chip 140 is embedded in the molding compound 130 and has a first surface 140a and a second surface 140b opposite to the first surface 140 a. The chip 140 includes a chip substrate 142 and a plurality of electrode pads 144. In various embodiments, the electrode pad 144 is exposed at the first surface 140a, and the second surface 140b is covered by the molding compound 130. It is noted that the electrode pads 144 are also exposed from the molding compound 130. The chip 140 may be, for example, an active element (active elements) or a passive element (passive elements), an electronic element (electronic components) of an integrated circuit such as a digital circuit or an analog circuit, an Embedded Chip Module (ECM), a Dynamic Random Access Memory (DRAM) element, a Static Random Access Memory (SRAM) element, an optoelectronic element (opto-electronic device), a Micro-Electro Mechanical system (MEMS), a Micro-fluidic system (Micro), or a physical sensor (physical sensors) that measures a change in physical quantity such as heat, light, and pressure, a radio frequency element (RF circuits), an accelerometer (accelerometers), a gyroscope (gyroscopic), a Micro actuator (Micro actuators), a surface acoustic wave element, a pressure sensor (pressure sensors), etc., but is not limited thereto. The chip 140 in fig. 4 is only shown schematically, and the actual length, width and height dimensions are adjusted according to the product requirements, but not limited thereto.
In various embodiments, the material of the encapsulant 130 may include resin and glass fiber. For example, the resin may be a phenolic resin, an epoxy resin, a polyimide resin, or polytetrafluoroethylene. Alternatively, the material of the encapsulant 130 may also include a Photo-electrically-sensitive Dielectric (Photo-electrically) material.
In some embodiments, the method of bonding the embedded chip substrate 20 on the insulating composite layer 120 may be performed by an adhesive layer (not shown), for example. Specifically, the adhesive layer can be adhered to the bottom surface 20S of the embedded chip substrate 20, and then the embedded chip substrate 20 is bonded to the insulating composite layer 120. In an embodiment, the adhesive layer may include a heat dissipating agent with high heat dissipation performance or high temperature resistance, but the invention is not limited thereto.
Step S04 is executed. Referring to fig. 5, a first wiring layer structure 150 is formed on the embedded chip substrate 20. The first circuit layer structure 150 includes at least one first dielectric layer 152 and at least one first circuit layer 154. It is understood that the minimum units constituting the circuit layer structure 150 are a dielectric layer and a circuit layer, and those skilled in the art can flexibly select the number of dielectric layers and circuit layers according to the actual requirement. The first dielectric layer 152 has a plurality of first conductive blind vias 152 a. The first circuit layer 154 is disposed on the first dielectric layer 152 and connected to or extended into the first conductive via hole 152 a. The first circuit layer 154 at the bottom layer is electrically connected to the electrode pad 144 through the first conductive via hole 152 a.
In various embodiments, the material of the first dielectric layer 152 may include resin and glass fiber. For example, the resin may be a phenolic resin, an epoxy resin, a polyimide resin, or polytetrafluoroethylene. Alternatively, the material of the first Dielectric layer 152 may also include a Photo-electrically-sensitive Dielectric material (Photo-electrically). It is noted that, in the present invention, the molding compound 130 and the first dielectric layer 152 have the same material composition. Compared with the method of using heterogeneous sealant and dielectric layer in the prior art, the method of the invention can avoid the problem of uneven tension caused by the section between the contact surfaces of the heterogeneous materials by making the sealant 130 and the first dielectric layer 152 have the same material composition, thereby increasing the strength of the whole structure and ensuring that the packaging structure is not easy to warp (warp) when the embedded chip substrate is processed in the subsequent process.
In some embodiments, the first dielectric layer 152 may be formed by Lamination (deposition), coating, or other suitable processes. In some embodiments, the blind via formation required for forming the first conductive blind via 152a includes, but is not limited to, forming the blind via by Laser ablation (Laser ablation) on the first dielectric layer 152, or forming the blind via by exposure and development when the material of the first dielectric layer 152 is selected from photosensitive dielectric materials, for forming the first conductive blind via 152 a.
In some embodiments, the first circuit layer 154 is formed by, but not limited to, forming a photoresist layer (not shown) such as a dry film on the first dielectric layer 152, and patterning the photoresist layer by a photolithography process to expose a portion of the first dielectric layer 152. Then, an electroplating process is performed to form the first circuit layer 154. The patterned photoresist layer is then removed. In one embodiment, the material of the first circuit layer 154 and the first conductive via 152a may be copper, for example. In other embodiments, a seed layer (not shown) may be formed on the first dielectric layer 152 before the first circuit layer 154 is formed. The seed layer may be a single layer or a multi-layer structure composed of sublayers of different materials, such as a metal layer comprising a titanium layer and a copper layer on the titanium layer. The seed layer may be formed by, but is not limited to, physical means such as sputtering titanium copper or chemical means such as palladium copper and electrolytic copper.
It is noted that, as shown in fig. 6, in other embodiments, the method 10 may also include forming a second circuit layer structure 250 above the embedded chip substrate 20. Specifically, the second circuit layer structure 250 includes at least one second dielectric layer 252 and at least one second circuit layer 254. The second dielectric layer 252 has a plurality of second conductive blind vias 252 a. The second circuit layer 254 is disposed on the second dielectric layer 252 and connected to or extended into the second conductive via 252a, and the second circuit layer 254 at the bottom layer is electrically connected to the electrode pad 144 through the second conductive via 252 a. It is understood that the minimum number of layers constituting the second circuit layer structure 250 is one dielectric layer and one circuit layer, and those skilled in the art can flexibly select the number of dielectric layers and circuit layers according to the actual requirement.
The formation methods and materials of the second dielectric layer 252, the second circuit layer 254 and the second conductive via 252a are the same as those of the first dielectric layer 152, the first circuit layer 154 and the first conductive via 152a, respectively, and thus are not repeated herein. In other words, in the present invention, the molding compound 130, the first dielectric layer 152 and the second dielectric layer 252 may have the same material composition.
Step S05 is then performed. As shown in fig. 7, the protective layer 160 is formed on the second line layer structure 250. The passivation layer 160 has a plurality of openings 162, such that a portion of the surface of the second circuit layer structure 250 is exposed in the openings 162. Specifically, as shown in fig. 9, a portion of the surface of the second circuit layer 254 at the outermost layer of the second circuit layer structure 250 is exposed in the opening 162. In various embodiments, the material of the protection layer 160 may be a solder mask material, or may be a resin material, such as epoxy resin. Alternatively, the material of the passivation layer 160 may be the same as the material of the first dielectric layer 152 or the second dielectric layer 252. The protective layer 160 may be formed by, for example, bonding, printing, or coating.
Next, step S06 is executed. As shown in fig. 8, the supporting layer 112, the first peeling layer 114 and the second peeling layer 116 are removed to form two package structures 100. Therefore, compared to the problem that the warpage is easily caused by the asymmetry of the structure in the conventional single-sided fabrication, the method 10 of the present invention forms two package structures 100 that are symmetrical up and down by performing the same process on the two opposite surfaces of the supporting layer 112 at the same time, so as to prevent the warpage at the two ends of the supporting layer 112, thereby improving the reliability of the entire package structure. Moreover, since the bottom of the package structure 100 has the metal layer 118, the heat generated by the chip 140 can be dissipated by the conduction of the metal layer 118, thereby achieving the effect of heat dissipation.
Next, step S07 is executed. As shown in fig. 9, each package substrate 100 is diced to obtain a plurality of package structures 100A. In some embodiments, the cutting of each package substrate 100 includes cutting each package substrate 100 along a cutting line CL in fig. 8 to obtain a plurality of package structures 100A. It should be understood that if each package substrate 100 is capable of generating N package structures 100A, two package substrates 100 formed by the above-mentioned manufacturing method 10 can generate 2N package structures 100A, thereby effectively increasing the number of product production.
Another embodiment of the present invention provides a package structure. Fig. 9 is a schematic cross-sectional view illustrating a package structure 100A according to an embodiment of the invention. The package structure 100A includes a metal layer 118, an insulating composite layer 120, a sealant 130, a chip 140, a first circuit layer structure 150, and a protection layer 160. The insulating composite layer 120 is disposed on the metal layer 118. The molding compound 130 is bonded to the insulating composite layer 120. The chip 140 is embedded in the encapsulant 130. The chip 140 has a plurality of electrode pads 144, and the electrode pads 144 are exposed from the molding compound 130. The first circuit layer structure 150 is formed on the encapsulant 130 and the chip 140. The first circuit layer structure 150 includes at least one first dielectric layer 152 and at least one first circuit layer 154. The first dielectric layer 152 has a plurality of first conductive blind vias 152 a. The first dielectric layer 152 and the molding compound 130 have the same material composition. The first circuit layer 154 is disposed on the first dielectric layer 152 and extends into the first conductive via 152a, and the first circuit layer 154 at the bottom layer is electrically connected to the electrode pad 144 through the first conductive via 152 a. It is understood that the minimum number of layers constituting the first circuit layer structure 150 is one dielectric layer and one circuit layer, and those skilled in the art can flexibly select the number of dielectric layers and circuit layers according to the actual requirement. The passivation layer 160 is formed on the first circuit layer 154 structure. The passivation layer 160 has a plurality of openings 162 such that a portion of the surface of the first circuit layer 154 is exposed in the openings 162.
The forming methods and materials of the metal layer 118, the insulating composite layer 120, the encapsulant 130, the chip 140, the first circuit layer structure 150, and the protection layer 160 are described above clearly, and are not described herein again. It is noted that, in the present invention, the molding compound 130 and the first dielectric layer 152 have the same material composition. Compared with the method of using heterogeneous sealant and dielectric layer in the prior art, the method of the invention can avoid the problem of uneven tension caused by the section between the contact surfaces of the heterogeneous materials by making the sealant 130 and the first dielectric layer 152 have the same material composition, thereby increasing the strength of the whole structure and ensuring that the packaging structure is not easy to warp (warp) when the embedded chip substrate is processed in the subsequent process.
In other embodiments, the package structure 100A includes a second circuit layer structure 250. The second circuit layer structure 250 is located above the embedded chip substrate 20. The second circuit layer structure 250 includes at least one second dielectric layer 252 and at least one second circuit layer 254. The second dielectric layer 252 has a plurality of second conductive blind vias 252 a. The second circuit layer 254 is disposed on the second dielectric layer 252 and connected to or extended into the second conductive via 252a, and the second circuit layer 254 at the bottom layer is electrically connected to the electrode pad 144 through the second conductive via 252 a. It is understood that the minimum number of layers constituting the second circuit layer structure 250 is one dielectric layer and one circuit layer, and those skilled in the art can flexibly select the number of dielectric layers and circuit layers according to the actual requirement. The molding compound 130, the first dielectric layer 152 and the second dielectric layer 252 may have the same material composition.
Fig. 10 is a cross-sectional view of a package structure 100B according to another embodiment of the invention. The manufacturing method of the package structure 100B according to the present embodiment is similar to the manufacturing method of the package structure 100A described above, and the difference between the two methods is that in step S03 shown in fig. 4, when the embedded chip substrate 20 is bonded to the insulating composite layer 120, the method further includes the following sub-steps: polishing the bottom surface 130S of the molding compound 130 to expose the bottom surface (second surface) 140b of the chip 140; and disposing the ground embedded chip substrate 20 on the insulating composite layer 120 to form a ground embedded chip substrate 12A. The method of Polishing the bottom surface 130S of the encapsulant includes, but is not limited to, Chemical-Mechanical Polishing (CMP). The method of bonding the ground embedded chip substrate 12A to the insulating composite layer 120 includes, but is not limited to, disposing an adhesive layer (not shown) between the ground embedded chip substrate 12A and the insulating composite layer 120.
It is noted that in the package structure 100B of the present embodiment, since the bottom surface (the second surface) 140B of the chip is exposed to the encapsulant 130, the metal layer 118 can conduct the heat generated by the chip 140 more effectively, so as to further enhance the heat dissipation effect, and reduce the thickness of the package structure 100B, which is beneficial to the thin design of the product.
In summary, in the package structure and the manufacturing method thereof of the present invention, since the sealing compound, the first dielectric layer and the second dielectric layer have the same material composition, compared with the method in which the sealing compound and the dielectric layer are made of heterogeneous materials in the conventional technology, the package structure of the present invention can avoid the problem of uneven tension caused by the presence of a cross section between the contact surfaces of the heterogeneous materials, thereby increasing the strength of the overall structure, so that the package structure is not easily warped (warp) when the embedded chip substrate is processed in the subsequent process.
In addition, the package structure and the manufacturing method thereof form the package substrate on the insulating composite layer, that is, the insulating composite layer can be used as a strengthening layer, which has higher hardness compared with the common dielectric layer and the package material. Therefore, the packaging structure and the manufacturing method thereof can strengthen the overall structural strength through the insulating composite layer to prevent the additional circuit board from warping, thereby not only improving the process yield, but also improving the reliability of the packaging structure.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A package structure, comprising:
a metal layer;
an insulating composite layer disposed on the metal layer;
the sealing glue is combined on the insulating composite layer;
a chip embedded in the encapsulant, the chip having a plurality of electrode pads exposed out of the encapsulant;
a circuit layer structure formed on the molding compound and the chip, wherein the circuit layer structure includes at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the dielectric layer and the molding compound have the same material composition, the circuit layer is located on the dielectric layer and extends into the plurality of conductive blind holes, and the circuit layer at the bottom layer is electrically connected to the plurality of electrode pads through the plurality of conductive blind holes; and
and the protective layer is formed on the circuit layer structure and provided with a plurality of openings, so that part of the surface of the circuit layer structure is exposed out of the plurality of openings.
2. The package structure of claim 1, wherein the dielectric layer and the encapsulant comprise a resin, a glass fiber, and a photosensitive dielectric material.
3. The package structure of claim 2, wherein the resin comprises phenolic resin, epoxy resin, polyimide resin, and polytetrafluoroethylene.
4. The package structure of claim 1, wherein the chip has a chip bottom surface exposed from the encapsulant.
5. The package structure of claim 1, wherein the insulating composite layer comprises a composite material comprising an insulating inorganic material and an organic material.
6. The package structure of claim 1, wherein the insulating composite layer is a nacreous layer.
7. A method of fabricating a package structure, comprising:
providing an additional circuit board, wherein the additional circuit board comprises a support layer, a first stripping layer, a second stripping layer and a plurality of metal layers, the first stripping layer and the second stripping layer are respectively arranged on two opposite surfaces of the support layer, and the metal layers are arranged on the first stripping layer and the second stripping layer;
disposing an insulating composite layer on each of the metal layers;
embedding chip substrates are combined on the insulating composite layers, wherein each embedded chip substrate comprises a chip and sealing glue, the chip is embedded in the sealing glue, the chip is provided with a plurality of electrode pads, and the electrode pads are exposed out of the sealing glue;
forming a circuit layer structure on each embedded chip substrate, wherein each circuit layer structure comprises at least one dielectric layer and at least one circuit layer, the dielectric layer is provided with a plurality of conductive blind holes, the dielectric layer and the sealing compound are made of the same material, the circuit layer is positioned on the dielectric layer and extends into the conductive blind holes, and the circuit layer is electrically connected with the electrode pads through the conductive blind holes;
forming a protective layer on the circuit layer structure, wherein the protective layer has a plurality of openings, so that part of the surface of the circuit layer structure is exposed in the plurality of openings;
removing the support layer, the first peeling layer and the second peeling layer to form two package substrates; and
and cutting the plurality of packaging substrates to obtain a plurality of packaging structures.
8. The method of claim 7, wherein disposing the embedded chip substrate on the insulating composite layer comprises:
grinding the bottom surface of the sealing glue of the embedded chip substrate to expose the bottom surface of the chip to form a ground embedded chip substrate; and
and arranging the ground embedded chip substrate on the insulating composite layer.
9. The method of claim 7, wherein the materials of the dielectric layer and the encapsulant comprise a resin, a glass fiber, and a photosensitive dielectric material.
10. The method of claim 9, wherein the resin comprises phenolic resin, epoxy resin, polyimide resin, and polytetrafluoroethylene.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910791239.8A CN112435930A (en) | 2019-08-26 | 2019-08-26 | Package structure and method for manufacturing the same |
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| CN201910791239.8A CN112435930A (en) | 2019-08-26 | 2019-08-26 | Package structure and method for manufacturing the same |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202394963U (en) * | 2011-12-28 | 2012-08-22 | 日月光半导体制造股份有限公司 | Multi-chip wafer-level semiconductor packaging structure |
| CN102751203A (en) * | 2011-04-22 | 2012-10-24 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation structure and manufacture method of semiconductor encapsulation structure |
| TW201342559A (en) * | 2012-04-02 | 2013-10-16 | 矽品精密工業股份有限公司 | Package structure, semiconductor package and fabrication method thereof |
| CN109273426A (en) * | 2017-07-18 | 2019-01-25 | 欣兴电子股份有限公司 | Encapsulating structure and its manufacturing method |
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2019
- 2019-08-26 CN CN201910791239.8A patent/CN112435930A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751203A (en) * | 2011-04-22 | 2012-10-24 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation structure and manufacture method of semiconductor encapsulation structure |
| CN202394963U (en) * | 2011-12-28 | 2012-08-22 | 日月光半导体制造股份有限公司 | Multi-chip wafer-level semiconductor packaging structure |
| TW201342559A (en) * | 2012-04-02 | 2013-10-16 | 矽品精密工業股份有限公司 | Package structure, semiconductor package and fabrication method thereof |
| CN109273426A (en) * | 2017-07-18 | 2019-01-25 | 欣兴电子股份有限公司 | Encapsulating structure and its manufacturing method |
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