CN109273426B - Package structure and method for manufacturing the same - Google Patents

Package structure and method for manufacturing the same Download PDF

Info

Publication number
CN109273426B
CN109273426B CN201710587742.2A CN201710587742A CN109273426B CN 109273426 B CN109273426 B CN 109273426B CN 201710587742 A CN201710587742 A CN 201710587742A CN 109273426 B CN109273426 B CN 109273426B
Authority
CN
China
Prior art keywords
layer
type resin
circuit layer
composite
organic material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710587742.2A
Other languages
Chinese (zh)
Other versions
CN109273426A (en
Inventor
杨凯铭
林晨浩
蔡王翔
柯正达
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unimicron Technology Corp
Original Assignee
Unimicron Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unimicron Technology Corp filed Critical Unimicron Technology Corp
Priority to CN201710587742.2A priority Critical patent/CN109273426B/en
Publication of CN109273426A publication Critical patent/CN109273426A/en
Application granted granted Critical
Publication of CN109273426B publication Critical patent/CN109273426B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention discloses a packaging structure and a manufacturing method thereof. The composite layer of the non-conductor inorganic material and the organic material is configured on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the molding compound and has a plurality of electrode pads. The circuit layer structure is formed on the sealing compound and the wafer. The circuit layer structure comprises at least one dielectric layer and at least one circuit layer, wherein the dielectric layer is provided with a plurality of conductive blind holes, the circuit layer is positioned on the dielectric layer, and the circuit layer at the bottommost layer is electrically connected with the electrode pad through the conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protection layer is provided with a plurality of openings, so that part of the surface of the circuit layer structure is exposed in the openings. The invention can strengthen the whole structure strength to prevent the generation of warping phenomenon.

Description

Package structure and method for manufacturing the same
Technical Field
The invention relates to a packaging structure and a manufacturing method thereof.
Background
With the evolution of Semiconductor packaging technology, in addition to the conventional Wire bonding (Wire bonding) Semiconductor packaging technology, different packaging types have been developed for Semiconductor devices (Semiconductor devices), such as directly embedding and electrically integrating a Semiconductor chip with an integrated circuit (ic) in a package substrate (package substrate) to reduce the overall volume and improve the electrical performance.
In order to meet the requirements of shortening the length of the conductive lines, reducing the thickness of the overall structure, and meeting the trend of high frequency and miniaturization, a method for processing the embedded chip substrate on a carrier without a core layer (core) has been developed. However, the carrier plate without the core layer lacks a rigid core plate for supporting, which results in insufficient strength, and thus the whole structure is prone to warp (warp).
Disclosure of Invention
In view of the above, an objective of the present invention is to provide a package structure and a method for manufacturing the same, which can enhance the overall structural strength and prevent the occurrence of warpage.
To achieve the above objects, according to one embodiment of the present invention, a package structure includes a metal layer, a composite layer of a non-conductive inorganic material and an organic material, a molding compound, a chip, a circuit layer structure, and an insulating protection layer. The composite layer of the non-conductor inorganic material and the organic material is configured on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the molding compound and has a plurality of electrode pads exposed from the molding compound. The circuit layer structure is formed on the sealing compound and the wafer. The circuit layer structure comprises at least one dielectric layer and at least one circuit layer, the dielectric layer is provided with a plurality of conductive blind holes, the circuit layer is positioned on the dielectric layer and extends into the conductive blind holes, and the circuit layer at the bottommost layer is electrically connected with the electrode pad through the conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protection layer is provided with a plurality of openings, so that part of the surface of the circuit layer structure is exposed in the openings.
In one or more embodiments of the present invention, the chip has a bottom surface, and the bottom surface of the chip is exposed from the encapsulant.
In one or more embodiments of the present invention, the material of the composite layer of the non-conductive inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.
In one or more embodiments of the present invention, the ceramic material comprises zirconia, alumina, silicon nitride, silicon carbide, silicon oxide, or a combination of the foregoing, and the polymer material comprises epoxy resin, polyimide, liquid crystal polymer, methacrylate type resin, vinyl phenyl type resin, allyl type resin, polyacrylate type resin, polyether type resin, polyolefin type resin, polyamine type resin, polysiloxane type resin, or a combination of the foregoing.
In one or more embodiments of the present invention, the composite layer of the non-conductive inorganic material and the organic material is a nacreous layer.
According to another embodiment of the present invention, a method for manufacturing a package structure includes the following steps. First, a carrier is provided, wherein the carrier includes a support layer having two opposite surfaces, a peeling layer disposed on the two surfaces, and a metal layer disposed on the peeling layer. Next, a composite layer of a non-conductive inorganic material and an organic material is disposed on the metal layer. Then, an embedded chip substrate is combined on the composite layer of the non-conductor inorganic material and the organic material, wherein the embedded chip substrate comprises a plurality of chips and sealing glue, the chips are embedded in the sealing glue, and the chips are provided with a plurality of electrode pads which are exposed out of the sealing glue. And forming a circuit layer structure on the embedded wafer substrate, wherein the circuit layer structure comprises at least one dielectric layer and at least one circuit layer, the dielectric layer is provided with a plurality of conductive blind holes, the circuit layer is positioned on the dielectric layer and extends into the conductive blind holes, and the circuit layer at the bottommost layer is electrically connected with the electrode pad through the conductive blind holes. And then, forming an insulating protection layer on the circuit layer structure, wherein the insulating protection layer is provided with a plurality of openings, so that part of the surface of the circuit layer structure is exposed out of the openings. Finally, the supporting layer and the stripping layer are removed to form two packaging substrates, and the packaging substrates are cut to obtain a plurality of packaging structures.
In one or more embodiments of the present invention, the molding compound has a molding compound bottom surface, the chip has a chip bottom surface, and the step of bonding the embedded chip substrates on the composite layer of the non-conductive inorganic material and the organic material includes the following steps. Grinding the bottom surface of the encapsulant to expose the bottom surface of the chip to form a ground embedded chip substrate; and combining the ground embedded wafer substrate on a composite layer of a non-conductor inorganic material and an organic material.
In one or more embodiments of the present invention, the material of the composite layer of the non-conductive inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.
In one or more embodiments of the present invention, the ceramic material comprises zirconia, alumina, silicon nitride, silicon carbide, silicon oxide, or a combination of the foregoing, and the polymer material comprises epoxy resin, polyimide, liquid crystal polymer, methacrylate type resin, vinyl phenyl type resin, allyl type resin, polyacrylate type resin, polyether type resin, polyolefin type resin, polyamine type resin, polysiloxane type resin, or a combination of the foregoing.
In one or more embodiments of the present invention, the composite layer of the non-conductive inorganic material and the organic material is a nacreous layer.
In summary, the package structure and the manufacturing method thereof of the present invention form the package substrate on the composite layer of the non-conductive inorganic material and the organic material, that is, the composite layer of the non-conductive inorganic material and the organic material can be regarded as a strengthening layer, which has higher hardness than the common dielectric layer and the package material. Therefore, the packaging structure and the manufacturing method thereof can strengthen the integral structural strength through the composite layer of the non-conductor inorganic material and the organic material so as to prevent the bearing plate from warping, thereby not only improving the process qualification rate, but also improving the reliability of the packaging structure.
The foregoing is merely illustrative of the problems to be solved, solutions to problems, and effects produced by the present invention, and specific details thereof are set forth in the following description and the related drawings.
Drawings
The above and other objects, features, and advantages of the present invention will become more apparent from the following description of the embodiments taken in conjunction with the accompanying drawings in which:
fig. 1A to 1G are cross-sectional views illustrating steps of a method for manufacturing a package structure according to an embodiment of the invention.
Fig. 2A to 2B are cross-sectional views of partial steps of a method for manufacturing a package structure according to another embodiment of the invention.
Fig. 3 is a cross-sectional view of a package structure obtained by the manufacturing method of fig. 2A to 2B.
Detailed Description
In the following description, numerous implementation details are set forth in order to provide a thorough understanding of the present invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such implementation details are not necessary. In addition, for the sake of simplicity, some conventional structures and elements are shown in the drawings in a simple schematic manner.
Fig. 1A to 1G are cross-sectional views illustrating steps of a method for manufacturing a package structure 18 according to an embodiment of the invention. First, as shown in fig. 1A, a carrier 10 is provided, wherein the carrier 10 includes a support layer 100 having two opposite surfaces 100A and 100B, a peeling layer 102 disposed on the two opposite surfaces 100A and 100B, and a metal layer 104 disposed on the peeling layer 102. The material of the support layer 100 may be, for example, an organic polymer material such as Bismaleimide/triazine (BT), and the support layer 100 may also be a Copper Clad Laminate (CCL) (not shown) having a dielectric material (e.g., prepreg) bonded to the entire surfaces of the opposite surfaces 100A and 100B. The release layer 102 may be a release film (release film), or other techniques may be used to provide the release layer 102, such as: mitsui, Nippon-Denk, Furukawa, Olin, or the like. The thickness of the metal layer 104 may be selected from a range of 1 micron to 10 microns, and the material of the metal layer 104 may be copper.
In some embodiments, another metal layer may be included between the release layer 102 and the opposite surfaces 100A, 100B of the support layer 100, and the thickness of the another metal layer may be selected from the range of 5 microns to 40 microns, and the material may be the same as or different from the metal layer 104, for example, copper.
Next, as shown in fig. 1B, a composite layer 106 of a non-conductive inorganic material and an organic material is disposed on the metal layer 104.
Further, the composite layer 106 of the non-conductive inorganic material and the organic material in the embodiment is made of a composite material of a ceramic material and a polymer material, wherein the ceramic material comprises zirconia, alumina, silicon nitride, silicon carbide, silicon oxide or a combination thereof, and the polymer material comprises epoxy resin, polyimide, liquid crystal polymer, methacrylate type resin, vinyl phenyl type resin, allyl type resin, polyacrylate type resin, polyether type resin, polyolefin type resin, polyamine type resin, polysiloxane type resin or a combination thereof. The ceramic material may be a ceramic layer or a ceramic powder, but the ceramic material of the embodiment is not limited thereto.
In the embodiment of the ceramic powder, the method for manufacturing the composite layer 106 of the non-conductive inorganic material and the organic material may be to impregnate the polymer material into the ceramic powder by using a vacuum impregnation technique, so as to prepare the composite layer 106 of the non-conductive inorganic material and the organic material, which is formed by the composite material of the ceramic powder and the polymer material. In the embodiment of the photosensitive resin composition in which the polymer material is, for example, an epoxy resin or an imide resin, the composite layer 106 of the non-conductive inorganic material and the organic material is disposed on the metal layer 104 by, for example, thermal compression bonding or vacuum impregnation, followed by irradiation with ultraviolet light and heating.
In the embodiment of the ceramic layer, the method for manufacturing the composite layer 106 of the non-conductive inorganic material and the organic material may be to impregnate the polymer material into the ceramic layer by using a vacuum impregnation technique, so as to prepare the composite layer 106 of the non-conductive inorganic material and the organic material, which is formed by the composite material composed of the ceramic layer and the polymer material. However, the method for manufacturing the composite layer 106 of the non-conductive inorganic material and the organic material in the present embodiment is not limited thereto, and other methods capable of forming a composite material of a polymer material and a ceramic material may be used. In the embodiment of the ceramic layer, more specifically, the composite layer 106 of the non-conductive inorganic material and the organic material comprises a composite composition of organic matter and inorganic matter (for example, a composite composition of a polymer material and a ceramic layer), and the ceramic layer of the composite layer 106 of the non-conductive inorganic material and the organic material has a micro-laminated structure of a sheet shape, a brick shape or a combination thereof, which inhibits the transmission of the transverse rupture force and significantly increases the rigidity thereof, based on the adhesion of the organic matter to the inorganic matter. Therefore, the material is firm and elastic, the ceramic strength can be improved, the ceramic brittleness can be improved, and the toughness is excellent. The composite layer 106 of non-conductive inorganic material and organic material may be a simulated pearl layer (imitative pearl layer).
Here, the young's modulus of the composite layer 106 of the non-conductive inorganic material and the organic material is, for example, between 20GPa and 100 GPa. Compared with the conventional dielectric layer (the Young's modulus of which is not greater than 10GPa) and the packaging material (the Young's modulus of which is not greater than 20GPa), the composite layer 106 of the non-conductive inorganic material and the organic material of the embodiment has excellent hardness, and can effectively strengthen the structural strength of the packaging structure.
Then, as shown in fig. 1C, the embedded chip substrate 12 is bonded on the composite layer 106 of the non-conductive inorganic material and the organic material, wherein the embedded chip substrate 12 includes a plurality of chips 120 and a molding compound 122, the chips 120 are embedded in the molding compound 122, each chip 120 has a plurality of electrode pads 120P, and the electrode pads 120P are exposed from the molding compound 122.
The method of bonding the embedded wafer substrate 12 to the composite layer 106 of non-conductive inorganic material and organic material may be performed, for example, by an adhesive layer (not shown). Specifically, the adhesive layer may be adhered to the bottom surface 12S of the embedded chip substrate 12, and then the embedded chip substrate 12 may be bonded to the composite layer 106 of the non-conductive inorganic material and the organic material. The adhesive layer may include a heat dissipating agent with high heat dissipation or high temperature resistance, but the invention is not limited thereto.
Next, as shown in fig. 1D to fig. 1E, a circuit layer structure 14 is formed on the embedded chip substrate 12, wherein each circuit layer structure 14 includes at least one dielectric layer and at least one circuit layer, each dielectric layer has a plurality of conductive blind vias, each circuit layer is located on each dielectric layer and extends into the conductive blind vias, and the circuit layer at the bottom layer is electrically connected to the electrode pad 120P through the conductive blind vias.
The minimum unit constituting the circuit layer structure 14 is at least one dielectric layer and at least one circuit layer, and those skilled in the art can flexibly select the number of the dielectric layers and the circuit layers according to actual needs. In the present embodiment, the circuit layer structure 14 including two dielectric layers (the first dielectric layer 108, the second dielectric layer 208) and two circuit layers (the first circuit layer 110, the second circuit layer 210) will be described as an example.
First, as shown in fig. 1D, a first dielectric layer 108 is formed on the embedded wafer substrate 12, wherein each first dielectric layer 108 has a plurality of first conductive vias 108H. The material of the first dielectric layer 108 may include resin and glass fiber. The resin may be a phenolic resin, an epoxy resin, a polyimide resin, or polytetrafluoroethylene. Alternatively, the material of the first dielectric layer 108 may also include a photosensitive dielectric material (PID). The first dielectric layer 108 may be formed by Lamination (plating), for example. The first conductive via 108H is formed by, but not limited to, Laser ablation (Laser ablation) on the first dielectric layer 108, or by exposing and developing a photosensitive dielectric material selected from the first dielectric layer 108 to form the first conductive via 108H.
Please continue to refer to fig. 1D. Then, a first circuit layer 110 is formed on the first dielectric layer 108, and the first circuit layer 110 extends into the first conductive via 108H, such that the first circuit layer 110 is electrically connected to the electrode pad 120P through the first conductive via 108H. The first circuit layer 110 may be formed by, for example: a photoresist layer (not shown) such as a dry film is formed on the first dielectric layer 108, and then a photolithography process is performed to pattern the photoresist layer to expose a portion of the first dielectric layer 108, and then an electroplating process and a photoresist layer removing process are performed to form a first circuit layer 110. The material of the first circuit layer 110 may be copper, for example.
In some embodiments, a seed layer may be formed on the first dielectric layer 108 before the first circuit layer 110 is formed. The seed layer may be a single layer or a multi-layer structure composed of sublayers of different materials, such as a metal layer comprising a titanium layer and a copper layer on the titanium layer. The seed layer may be formed by, but is not limited to, physical means such as sputtering titanium copper or chemical means such as palladium copper and electrolytic copper.
Next, as shown in fig. 1E, a second dielectric layer 208 is formed on the first dielectric layer 108 and the first circuit layer 110, wherein the second dielectric layer 208 has a plurality of second conductive vias 208H. Then, a second circuit layer 210 is formed on the second dielectric layer 208, and the second circuit layer 210 extends into the second conductive via 208H, such that the second circuit layer 210 is electrically connected to the first circuit layer 110 through the second conductive via 208H.
Thus, a circuit layer structure 14 is formed on the embedded wafer substrate 12, wherein the circuit layer structure 14 includes a first dielectric layer 108, a first circuit layer 110, a second dielectric layer 208 and a second circuit layer 210. The first dielectric layer 108 has a plurality of first conductive vias 108H, and the first circuit layer 110 is electrically connected to the electrode pad 120P through the first conductive vias 108H. The second dielectric layer 208 has a plurality of second conductive vias 208H, and the second circuit layer 210 is electrically connected to the first circuit layer 110 through the second conductive vias 208H. That is, the circuit layer structure 14 includes at least one dielectric layer (the first dielectric layer 108, the second dielectric layer 208) and at least one circuit layer (the first circuit layer 110, the second circuit layer 210), each dielectric layer has a plurality of conductive blind vias (the first conductive blind via 108H, the second conductive blind via 208H), each circuit layer is located on each dielectric layer and extends into the conductive blind via, and the circuit layer (the first circuit layer 110) at the bottom layer is electrically connected to the electrode pad 120P through the conductive blind via (the first conductive blind via 108H).
The formation methods and materials of the second dielectric layer 208, the second circuit layer 210 and the second conductive via 208H are the same as those of the first dielectric layer 108, the first circuit layer 110 and the first conductive via 108H, respectively, and thus are not repeated herein. In addition, before the second circuit layer 210 is formed, the seed layer may be formed on the second dielectric layer 208, which is not described herein.
Please continue to refer to fig. 1E. Then, insulating protection layers 112 are formed on the circuit layer structure 14, wherein each insulating protection layer 112 has a plurality of openings 112O, so that a portion of the surface of the circuit layer structure 14 is exposed in the openings 112O. Specifically, as shown in fig. 1E, a portion of the surface of the second circuit layer 210 at the outermost layer of the circuit layer structure 14 is exposed in the opening 112O.
The material of the insulating protection layer 112 may be solder resist material, or may be resin material, such as epoxy resin. Alternatively, the material of the insulating protection layer 112 may be the same as the material of the first dielectric layer 108 or the second dielectric layer 208. The insulating protection layer 112 may be formed by bonding, printing, or coating.
Next, as shown in fig. 1F, the supporting layer 100 and the peeling layer 102 are removed to form two package substrates 16. Therefore, compared to the conventional single-sided fabrication that is easily warped due to the asymmetry of the structure, the present embodiment forms the two vertically symmetric package substrates 16 by performing the same process on the two opposite surfaces 100A and 100B of the support layer 100 at the same time, so as to avoid the warping at the two ends of the support layer 100, and improve the reliability of the entire package structure.
Finally, as shown in fig. 1G, the package substrate 16 is diced to obtain a plurality of package structures 18. It can be seen that if N package structures 18 can be produced for each package substrate 16, 2N package structures 18 can be produced for two package substrates 16 formed by the manufacturing method of fig. 1A to 1F, and thus the number of product production can be effectively increased.
Thus, the package structure 18 of the present embodiment is completed, which includes: a metal layer 104, a composite layer 106 of non-conductive inorganic material and organic material, a molding compound 122, a wafer 120, a circuit layer structure 14, and an insulating protection layer 112. A composite layer 106 of a non-conductive inorganic material and an organic material is disposed on the metal layer 104. The encapsulant 122 is bonded to the composite layer 106 of non-conductive inorganic material and organic material. The chip 120 is embedded in the molding compound 122, and the chip 120 has a plurality of electrode pads 120P, and the electrode pads 120P are exposed from the molding compound 122. The circuit layer structure 14 is formed on the molding compound 122 and the chip 120. The circuit layer structure 14 includes at least one dielectric layer having a plurality of conductive blind vias and at least one circuit layer located on the dielectric layer and extending into the conductive blind vias, wherein the circuit layer at the bottom layer is electrically connected to the electrode pad 120P through the conductive blind vias. An insulating protection layer 112 is formed on the wiring layer structure 14. The insulating protection layer 112 has a plurality of openings 112O, such that a portion of the surface of the circuit layer structure 14 is exposed in the openings 112O.
The package structure 18 and the method for fabricating the same according to the present invention form the package substrate 16 on the composite layer 106 of the non-conductive inorganic material and the organic material, that is, the composite layer 106 of the non-conductive inorganic material and the organic material can be regarded as a strengthening layer, which has higher hardness than the common dielectric layer and the package material. Therefore, the package structure 18 and the manufacturing method thereof of the present invention can enhance the overall structural strength by the composite layer 106 of the non-conductive inorganic material and the organic material to prevent the carrier from warping, thereby not only improving the process qualification, but also improving the reliability of the package structure 18.
Moreover, since the bottom of the package structure 18 has the metal layer 104, the heat generated by the wafer 120 can be dissipated by the conduction of the metal layer 104, thereby achieving the heat dissipation effect.
Fig. 2A to 2B are cross-sectional views of partial steps of a method for manufacturing a package structure 18A according to another embodiment of the invention. Fig. 3 is a cross-sectional view of the package structure 18A obtained according to the manufacturing method of fig. 2A to 2B. The manufacturing method of the package structure 18A of the present embodiment is similar to the manufacturing method of the package structure 18 described above, and the difference between the two methods is: the step of bonding the embedded chip substrate 12 on the composite layer 106 of the non-conductive inorganic material and the organic material further includes the sub-step of polishing the bottom surface 122S of the encapsulant to expose the bottom surface 120S of the chip.
Please refer to fig. 2A and fig. 1C simultaneously. The difference between this embodiment and the step shown in fig. 1C is that before the embedded wafer substrate 12 is bonded to the composite layer 106 of non-conductive inorganic material and organic material, the bottom surface 122S of the encapsulant is polished to expose the bottom surface 120S of the wafer to form a polished embedded wafer substrate 12A. The bottom surface 122S of the encapsulant may be polished by Chemical-Mechanical Polishing (CMP), for example.
Next, as shown in fig. 2B, the buried wafer substrate 12A after polishing is bonded to the composite layer 106 of the non-conductive inorganic material and the organic material. That is, when the polished embedded wafer substrate 12A is bonded to the composite layer 106 of non-conductive inorganic material and organic material, the bottom surface 120S of the wafer is exposed to the encapsulant 122.
The method for combining the polished embedded wafer substrate 12A on the composite layer 106 of the non-conductive inorganic material and the organic material may be performed by an adhesive layer (not shown), for example, and the specific steps may refer to the previous embodiment and will not be described herein again.
Then, the steps shown in fig. 1D to fig. 1G are continued to obtain the package structure 18A shown in fig. 3. In the present embodiment, since the bottom surface 120S of the wafer is exposed to the encapsulant 122, the metal layer 104 can conduct the heat generated by the wafer 120 more effectively, so as to further enhance the heat dissipation effect, and reduce the thickness of the package structure 18A, which is beneficial to the thin design of the product.
As is apparent from the above detailed description of the embodiments of the invention, the package structure and the manufacturing method thereof according to the present invention form the package substrate on the composite layer of the non-conductive inorganic material and the organic material, that is, the composite layer of the non-conductive inorganic material and the organic material can be regarded as a strengthening layer, which has higher hardness than the common dielectric layer and the package material. Therefore, the packaging structure and the manufacturing method thereof can strengthen the integral structural strength through the composite layer of the non-conductor inorganic material and the organic material so as to prevent the bearing plate from warping, thereby not only improving the process qualification rate, but also improving the reliability of the packaging structure.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims (10)

1. A package structure, comprising:
a metal layer;
a composite layer of a non-conductive inorganic material and an organic material disposed on the metal layer, wherein the composite layer of the non-conductive inorganic material and the organic material is a single-layer mixed structure prepared by impregnating the organic material into the non-conductive inorganic material;
the sealing glue is combined on the composite layer of the non-conductor inorganic material and the organic material;
a chip embedded in the encapsulant, the chip having a plurality of electrode pads exposed out of the encapsulant;
a circuit layer structure formed on the encapsulant and the chip, wherein the circuit layer structure includes at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the circuit layer is located on the dielectric layer and extends into the plurality of conductive blind holes, and the circuit layer at the bottom layer is electrically connected to the plurality of electrode pads through the plurality of conductive blind holes; and
and the insulating protection layer is formed on the circuit layer structure and is provided with a plurality of openings, so that part of the surface of the circuit layer structure is exposed out of the plurality of openings.
2. The package structure of claim 1, wherein the die has a die bottom surface exposed from the encapsulant.
3. The package structure according to any one of claims 1 to 2, wherein the material of the composite layer of the non-conductive inorganic material and the organic material comprises a composite material composed of a ceramic material and a polymer material.
4. The package structure of claim 3, wherein the ceramic material comprises zirconia, alumina, silicon nitride, silicon carbide, silicon oxide, or a combination of the foregoing, and the polymeric material comprises an epoxy resin, a polyimide, a liquid crystal polymer, a methacrylate type resin, a vinyl phenyl type resin, an allyl type resin, a polyacrylate type resin, a polyether type resin, a polyolefin type resin, a polyamine type resin, a polysiloxane type resin, or a combination of the foregoing.
5. The package structure of claim 1, wherein the composite layer of the non-conductive inorganic material and the organic material is a nacreous layer.
6. A method of manufacturing a package structure, comprising:
providing a bearing plate, wherein the bearing plate comprises a supporting layer with two opposite surfaces, stripping layers arranged on the two surfaces, and metal layers arranged on the stripping layers;
disposing a composite layer of a non-conductive inorganic material and an organic material on each of the metal layers, wherein the composite layer of the non-conductive inorganic material and the organic material is a single-layer mixed structure prepared by impregnating the organic material into the non-conductive inorganic material;
combining embedded wafer substrates on the composite layer of the non-conductor inorganic material and the organic material, wherein each embedded wafer substrate comprises a plurality of wafers and sealing glue, the wafers are embedded in the sealing glue, each wafer is provided with a plurality of electrode pads, and the electrode pads are exposed out of the sealing glue;
forming a circuit layer structure on each embedded wafer substrate, wherein each circuit layer structure comprises at least one dielectric layer and at least one circuit layer, the dielectric layer is provided with a plurality of conductive blind holes, the circuit layer is positioned on the dielectric layer and extends into the conductive blind holes, and the circuit layer at the bottommost layer is electrically connected with the electrode pads through the conductive blind holes;
forming an insulating protection layer on each circuit layer structure, wherein each insulating protection layer is provided with a plurality of openings, so that part of the surface of each circuit layer structure is exposed out of the plurality of openings;
removing the support layer and the stripping layers to form two packaging substrates; and
and cutting each packaging substrate to obtain a plurality of packaging structures.
7. The method of claim 6, wherein each encapsulant has an encapsulant bottom surface, each die has a die bottom surface, and wherein bonding each embedded die substrate on each composite layer of non-conductive inorganic material and organic material comprises:
grinding the bottom surface of the sealing compound to expose the bottom surface of the wafer so as to form a ground embedded wafer substrate; and
and bonding the polished embedded wafer substrate on each composite layer of the non-conductor inorganic material and the organic material.
8. The method according to any one of claims 6 to 7, wherein a material of each of the composite layers of the non-conductive inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.
9. The method of claim 8, wherein the ceramic material comprises zirconia, alumina, silicon nitride, silicon carbide, silicon oxide, or a combination of the foregoing, and the polymeric material comprises an epoxy resin, a polyimide, a liquid crystal polymer, a methacrylate-type resin, a vinyl phenyl-type resin, an allyl-type resin, a polyacrylate-type resin, a polyether-type resin, a polyolefin-type resin, a polyamine-type resin, a polysiloxane-type resin, or a combination of the foregoing.
10. The method of claim 6, wherein each of said composite layers of non-conductive inorganic material and organic material is a nacreous layer.
CN201710587742.2A 2017-07-18 2017-07-18 Package structure and method for manufacturing the same Active CN109273426B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710587742.2A CN109273426B (en) 2017-07-18 2017-07-18 Package structure and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710587742.2A CN109273426B (en) 2017-07-18 2017-07-18 Package structure and method for manufacturing the same

Publications (2)

Publication Number Publication Date
CN109273426A CN109273426A (en) 2019-01-25
CN109273426B true CN109273426B (en) 2020-08-18

Family

ID=65152972

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710587742.2A Active CN109273426B (en) 2017-07-18 2017-07-18 Package structure and method for manufacturing the same

Country Status (1)

Country Link
CN (1) CN109273426B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112435930A (en) * 2019-08-26 2021-03-02 欣兴电子股份有限公司 Package structure and method for manufacturing the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI575684B (en) * 2011-06-13 2017-03-21 矽品精密工業股份有限公司 Chip-scale package structure
US11127664B2 (en) * 2011-10-31 2021-09-21 Unimicron Technology Corp. Circuit board and manufacturing method thereof
KR20150047879A (en) * 2013-10-25 2015-05-06 삼성전기주식회사 Printed curcuit board and manufacturing method of the same
CN106206945A (en) * 2016-09-08 2016-12-07 京东方科技集团股份有限公司 A kind of flexible base board and preparation method thereof, flexible display apparatus

Also Published As

Publication number Publication date
CN109273426A (en) 2019-01-25

Similar Documents

Publication Publication Date Title
US8115297B2 (en) Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
US20080099912A1 (en) Packaging with base layers comprising alloy 42
WO2021196351A1 (en) Embedded chip package and manufacturing method therefor
TWI405309B (en) Heat dissipating substrate and method of manufacturing the same
US11895780B2 (en) Manufacturing method of package structure
TWI670814B (en) Single layer coreless substrate
TW201301466A (en) Bumpless build-up layer package warpage reduction
JP2013243345A (en) Ultrathin buried die module and method of manufacturing the same
TWI409923B (en) Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
TWI621224B (en) Package structure and manufacturing method thereof
CN109273426B (en) Package structure and method for manufacturing the same
JP3841079B2 (en) Wiring substrate, semiconductor package, substrate insulating film, and method of manufacturing wiring substrate
KR20180077115A (en) Manufacturing method of pcb and semiconductor package using transparent carrier
US20220375919A1 (en) Manufacturing method of package structure
JP2005019754A (en) Composite component and its manufacturing method
TWI663693B (en) Package structure and manufacturing method thereof
JP4457943B2 (en) Wiring board and method for manufacturing wiring board
US11393761B2 (en) Circuit board and its manufacturing method
US20220238474A1 (en) Electronic component embedded substrate and circuit module using the same
CN111341750B (en) Component carrier comprising an electrically conductive base structure and method of manufacture
CN108012402B (en) Circuit board and manufacturing method thereof
KR100547349B1 (en) Semiconductor packaging substrate and manufacturing method thereof
TWI713185B (en) Package structure and manufacturing method thereof
US20200068721A1 (en) Package structure and manufacturing method thereof
CN113133178A (en) Arrangement with a central carrier and two opposite layer stacks, component carrier and method for producing the component carrier

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant