TW201301466A - Bumpless build-up layer package warpage reduction - Google Patents

Bumpless build-up layer package warpage reduction Download PDF

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Publication number
TW201301466A
TW201301466A TW101120105A TW101120105A TW201301466A TW 201301466 A TW201301466 A TW 201301466A TW 101120105 A TW101120105 A TW 101120105A TW 101120105 A TW101120105 A TW 101120105A TW 201301466 A TW201301466 A TW 201301466A
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Taiwan
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layer
microelectronic device
microelectronic
package
thermal expansion
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TW101120105A
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Chinese (zh)
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TWI578469B (en
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Pramod Malatkar
Drew W Delaney
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Intel Corp
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Abstract

The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.

Description

無凸塊增層式封裝體翹曲降低技術 Bumpless build-up package warpage reduction technology

本發明係有關於一種無凸塊增層式封裝體翹曲降低技術。 The present invention relates to a bumpless build-up package warp reduction technique.

本發明之實施例係大致有關於微電子裝置封裝體設計且，更特別地，係有關於具有一無凸塊增層式(BBUL)設計之一微電子裝置封裝體。 Embodiments of the present invention are generally related to microelectronic device package designs and, more particularly, to a microelectronic device package having a bumpless build-up (BBUL) design.

依據本發明之一實施例，係特地提出一種微電子封裝體，包含：一微電子裝置，其具有一主動表面，一相對背面，及至少一側；及一翹曲控制結構，其與該微電子裝置背面相鄰，其中該翹曲控制結構包括一高熱膨脹係數材料層及一高彈性模數材料層。 According to an embodiment of the present invention, a microelectronic package is specifically provided, comprising: a microelectronic device having an active surface, an opposite back surface, and at least one side; and a warpage control structure, and the micro The back side of the electronic device is adjacent, wherein the warp control structure comprises a layer of high coefficient of thermal expansion material and a layer of high modulus of elasticity material.

依據本發明之一實施例，係特地提出一種製造一微電子封裝體之方法，包含：形成一微電子裝置，且該微電子裝置具有一主動表面，一相對背面，及至少一側；及形成一與該微電子裝置背面相鄰之翹曲控制結構，其包含形成與一高彈性模數材料層相鄰之一高熱膨脹係數材料層。 According to an embodiment of the present invention, a method for fabricating a microelectronic package includes: forming a microelectronic device having an active surface, an opposite back surface, and at least one side; and forming A warp control structure adjacent the back of the microelectronic device includes a layer of high coefficient of thermal expansion material adjacent to a layer of high modulus of elasticity material.

依據本發明之一實施例，係特地提出一種製造一微電子封裝體之方法，包含：提供一載體；在該載體上形成一微電子裝置附接墊，其中該微電子裝置附接墊包括一高彈性模數材料層；附接具有一主動表面，一相對背面，及至少一側之一微電子裝置在該微電子裝置附接墊上，其中附 接該微電子裝置之步驟包括將一高熱膨脹係數材料層設置在該微電子裝置背面與該微電子裝置附接墊之間；將一封裝材料設置成與該微電子裝置主動表面之至少一部份及至少一微電子裝置側之至少一部份相鄰；及移除該載體。 According to an embodiment of the present invention, a method for fabricating a microelectronic package includes: providing a carrier; forming a microelectronic device attachment pad on the carrier, wherein the microelectronic device attachment pad includes a a layer of high modulus of elasticity material; attached with an active surface, an opposite back surface, and at least one of the microelectronic devices on the microelectronic device attachment pad, wherein The step of connecting the microelectronic device includes disposing a layer of high coefficient of thermal expansion material between the back surface of the microelectronic device and the microelectronic device attachment pad; and setting a package material to at least one of the active surface of the microelectronic device And at least a portion of the at least one microelectronic device side being adjacent; and removing the carrier.

圖式簡單說明 Simple illustration

本發明之標的物係在說明書之結論部份中特別指出且清楚地請求。本發明之前述及其他將可配合附圖，由以下說明及附加申請專利範圍更完整地了解。應了解的是該等附圖只顯示依據本發明之數個實施例且因此不應被視為限制其範圍。本揭露將透過利用附圖以另外之特性及細節說明，使得本發明之優點可以更輕易地確定，其中：第1圖顯示依據本發明一實施例之一無凸塊增層式無核心微電子封裝體的側橫截面圖。 The subject matter of the present invention is specifically indicated and clearly claimed in the conclusion of the specification. The foregoing and other aspects of the present invention will be more fully understood from the following description and the appended claims. It is to be understood that the appended claims The disclosure will make the advantages of the present invention more easily determined by using other features and details of the drawings, wherein: FIG. 1 shows a bumpless build-up coreless microelectronic according to an embodiment of the invention. Side cross-sectional view of the package.

第2圖顯示依據本發明另一實施例之一無凸塊增層式無核心微電子封裝體的側橫截面圖。 2 is a side cross-sectional view showing a bumpless build-up coreless microelectronic package in accordance with another embodiment of the present invention.

第3-13圖顯示依據本發明一實施例之形成一凹孔型無凸塊增層式無核心微電子封裝體之一製程的橫截面圖。 3-13 are cross-sectional views showing a process for forming a recessed-type bumpless build-up coreless microelectronic package in accordance with an embodiment of the present invention.

第14-20圖顯示依據本發明一實施例之形成一埋入型無凸塊增層式無核心微電子封裝體之一製程的橫截面圖。 14-20 illustrate cross-sectional views of a process for forming a buried bumpless build-up coreless microelectronic package in accordance with an embodiment of the present invention.

詳細說明 Detailed description

在以下詳細說明中，參照藉由舉例說明顯示可實施之請求標的物的特定實施例。這些實施例係充分詳細地說明以使所屬技術領域中具有通常知識者可實施該標的物。應 了解的是各種實施例雖然不同，但不一定是互相排他的。例如，在此關於一實施例所述之特定特徵、結構或特性可在不偏離所請求之標的物之精神及範疇之情形下，在其他實施例內實施。在這說明書內提及之“一個實施例”或“一實施例”表示關於該實施例所述之一特定特徵、結構或特性包含在本發明之至少一個實施例中。因此，使用該片語“在一個實施例中”或“在一實施例中”的出現不一定指的是相同實施例。此外，應了解的是在各揭露實施例內之個別元件之位置及配置可在不偏離該請求之標的物之情形下修改。因此，以下詳細說明不應一限制方式解釋，且該標的物之範疇係只由附加之申請專利範圍以及附加之申請專利範圍所賦予之等效物之全部範圍界定，及適當地判讀。在圖式中，類似符號表示在全部數個圖中相同或類似元件或功能性，且其中所示之元件不一定互相成比例，而是個別元件可放大或縮小以便更容易地了解在此說明之上下文中的元件。 In the following detailed description, reference is made to the specific embodiments that illustrate the subject matter that can be implemented by way of example. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the subject matter. should It is understood that the various embodiments are different, but are not necessarily mutually exclusive. For example, the particular features, structures, or characteristics described herein may be practiced in other embodiments without departing from the spirit and scope of the claimed subject matter. The phrase "one embodiment" or "an embodiment" as used in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearance of the phrase "in one embodiment" or "in an embodiment" does not necessarily mean the same embodiment. In addition, it is to be understood that the location and configuration of the individual elements in the various embodiments disclosed herein can be modified without departing from the scope of the claimed subject matter. Therefore, the following detailed description is not to be construed as a limitation, and the scope of the subject matter of the invention is defined by the scope of the appended claims and the scope of the appended claims. In the drawings, like reference numerals indicate the same or similar elements or functions in the various figures, and the elements shown in the figures are not necessarily to scale to each other, but the individual elements can be enlarged or reduced to make it easier to understand the description here. The components in the context.

本發明之實施例係有關於製造微電子封裝體及其製造之領域，其中一微電子裝置可在一無凸塊增層式無核心(BBUL-C)微電子封裝體內形成且其中一翹曲控制結構可設置在該微電子裝置之一背面上。該翹曲控制結構可以是一層結構，且該層結構包含包括但不限於一填二氧化矽環氧樹脂材料之至少一高熱膨脹係數材料層，及例如一金屬層之至少一高彈性模數材料層。這翹曲控制結構可以在室溫(大約攝氏25度)及在迴焊溫度(例如，大約攝氏260度)均 有效地減少該無凸塊增層式無核心微電子封裝體之翹曲。迴焊溫度係互連焊料結構被加熱到將該微電子封裝體附接在例如一母板之外部裝置上的溫度。 Embodiments of the present invention relate to the field of fabricating microelectronic packages and their fabrication, wherein a microelectronic device can be formed in a bumpless build-up coreless (BBUL-C) microelectronic package with one of the warps The control structure can be disposed on the back side of one of the microelectronic devices. The warp control structure may be a layer structure, and the layer structure includes at least one layer of high thermal expansion coefficient material including, but not limited to, a cerium oxide-filled epoxy resin material, and at least one high elastic modulus material such as a metal layer. Floor. This warpage control structure can be at room temperature (about 25 degrees Celsius) and at reflow temperature (for example, about 260 degrees Celsius). The warpage of the bumpless build-up coreless microelectronic package is effectively reduced. The reflow temperature is the temperature at which the interconnect solder structure is heated to attach the microelectronic package to an external device such as a motherboard.

如所屬技術領域中具有通常知識者可了解地，減少翹曲可減少微電子裝置損壞之可能性及在將該微電子封裝體附接在外部裝置上時之連接問題。此外，由於因翹曲減少而減少在該等微電子裝置內之電晶體上的平面內壓力，因此可改善在該等微電子封裝體內之微電子裝置的效能。 As will be appreciated by those of ordinary skill in the art, reducing warpage can reduce the likelihood of damage to the microelectronic device and the connection problems when attaching the microelectronic package to an external device. In addition, the efficiency of the microelectronic devices in the microelectronic packages can be improved by reducing the in-plane pressure on the transistors within the microelectronic devices due to reduced warpage.

第1圖顯示一凹孔型無凸塊增層式無核心(BBUL-C)微電子封裝體之一實施例的橫截面圖。如第1圖所示，一微電子封裝體100可包括實質被包封在一封裝材料112中之一微電子裝置102，其中該封裝材料112可抵靠該微電子裝置102之一主動表面104之至少一部份及該微電子裝置102之至少一側110。該微電子主動表面104可具有形成於其中及/或其上之至少一接觸焊墊106。該微電子裝置102可以是任何所需裝置，包括但不限於一微處理器(單核心或多核心)，一記憶體裝置，一晶片組，一繪圖裝置，一特殊應用積體電路等。該封裝材料112可以是一填二氧化矽環氧樹脂，例如由日本210-0801川崎市川崎區鈴木鎮1-2之Ajinomoto Fine-Techno公司(Ajinomoto ABF-GX13，Ajinomoto GX92等)取得之增層薄膜。 Figure 1 shows a cross-sectional view of one embodiment of a recessed bumpless build-up coreless (BBUL-C) microelectronic package. As shown in FIG. 1, a microelectronic package 100 can include a microelectronic device 102 that is substantially encapsulated in a package material 112, wherein the package material 112 can abut an active surface 104 of the microelectronic device 102. At least a portion and at least one side 110 of the microelectronic device 102. The microelectronic active surface 104 can have at least one contact pad 106 formed therein and/or thereon. The microelectronic device 102 can be any desired device, including but not limited to a microprocessor (single core or multi-core), a memory device, a chip set, a graphics device, a special application integrated circuit, and the like. The encapsulating material 112 may be a ruthenium dioxide-filled epoxy resin, for example, a layer obtained by Ajinomoto Fine-Techno Co., Ltd. (Ajinomoto ABF-GX13, Ajinomoto GX92, etc.), 1-2, Suzuki Town, Kawasaki-ku, Kawasaki, Japan 210-0801. film.

一增層122可形成在靠近該微電子裝置主動表面104之該封裝材料112之一第一表面114上。該增層122可包含多數介電層，且多數導電線路與各介電層相鄰地形成，並且多 數導電通孔延伸穿過各介電層以連接在不同層上之導電線路。請參閱第1圖，該增層122可包含至少一第一層導電線路132，且一第一增建介電層134與該第一層導電線路132及該封裝材料112相鄰地形成。至少一線路至裝置導電通孔136可延伸穿過該第一增建介電層134以連接至少一第一層導電線路132與至少一微電子裝置接觸焊墊106。至少一第二層導電線路142可與該第一增建介電層134相鄰地形成且一第二增建介電層144可與該第二層導電線路142及該第一增建介電層134相鄰地形成。至少一線路至線路導電通孔146可延伸穿過該第一增建介電層134以連接至少一第一層導電線路132與至少一第二層導電線路142。至少一第三層導電線路152可形成在該第二增建介電層144上且至少一線路至線路導電通孔146可延伸穿過該第二增建介電層144以連接至少一第二層導電線路142與第三層導電線路152。一阻焊材料154可在該第二增建介電層144及第三層導電線路152上圖案化，且具有至少一暴露該第三層導電線路152之一部份之開口156。應了解的是例如焊料球之多數互連結構(未顯示)可形成在該(等)第三層導電線路152穿過該(等)阻焊材料開口156。 A build-up layer 122 can be formed on a first surface 114 of the encapsulation material 112 adjacent the active surface 104 of the microelectronic device. The build-up layer 122 can include a plurality of dielectric layers, and a plurality of conductive traces are formed adjacent to the respective dielectric layers, and A number of conductive vias extend through the dielectric layers to connect the conductive traces on the different layers. Referring to FIG. 1 , the build-up layer 122 can include at least one first conductive trace 132 , and a first build-up dielectric layer 134 is formed adjacent to the first conductive trace 132 and the encapsulation material 112 . At least one line-to-device conductive via 136 may extend through the first build-up dielectric layer 134 to connect the at least one first conductive trace 132 to the at least one microelectronic device contact pad 106. At least one second conductive layer 142 may be formed adjacent to the first additional dielectric layer 134 and a second additional dielectric layer 144 may be coupled to the second conductive layer 142 and the first additional dielectric Layers 134 are formed adjacent to each other. At least one line-to-line conductive via 146 may extend through the first build-up dielectric layer 134 to connect the at least one first conductive trace 132 and the at least one second conductive trace 142. At least one third layer of conductive traces 152 may be formed on the second build-up dielectric layer 144 and at least one trace-to-line conductive via 146 may extend through the second build-up dielectric layer 144 to connect at least a second Layer conductive line 142 and third layer conductive line 152. A solder resist material 154 can be patterned over the second build-up dielectric layer 144 and the third layer of conductive traces 152 and has at least one opening 156 that exposes a portion of the third layer of conductive traces 152. It will be appreciated that a majority of interconnect structures (not shown), such as solder balls, may be formed through the (or the same) third layer of conductive traces 152 through the (and the same) solder resist opening 156.

至少一疊合式封裝(PoP)墊162可形成在該封裝材料112之一第二表面116(實質相對該封裝材料第一表面114)上及/或中。該疊合式封裝墊162可與至少一第一層導電線路132電連接。如所屬技術領域中具有通常知識者可了解地，該等疊合式封裝墊可用來在不需要貫穿矽通孔之情形下， 以一z方向在微電子裝置封裝體之間形成多數連接部以便堆疊(例如，所謂3D堆疊)。 At least one stacked package (PoP) pad 162 may be formed on and/or in a second surface 116 of the encapsulation material 112 (substantially opposite the first surface 114 of the encapsulation material). The stacked package pad 162 can be electrically connected to at least one first layer of conductive traces 132. As will be appreciated by those of ordinary skill in the art, the stacked package pads can be used without the need to penetrate through the through holes. A plurality of connections are formed between the microelectronic device packages in a z-direction for stacking (eg, a so-called 3D stack).

如第1圖所示，例如由日本910-0381 Fukui Sakai Maruoka Funayose 110-1-1之Nitto Denko取得之Nitto NX2 DBF材料，可設置在該微電子裝置102之背面108上。一翹曲控制結構180可包含一設置在該晶粒背側薄膜172上之高熱膨脹係數(CTE)材料層182及一設置在該高CTE材料層182上之高彈性模數材料層184。該高CTE材料層182可包括，但不限於填充環氧樹脂，例如一填二氧化矽環氧樹脂，包括但不限於由日本210-0801川崎市川崎區鈴木鎮1-2之Ajinomoto Fine-Techno公司的Ajinomoto ABF-GX13，Ajinomoto GX92等。該高彈性模數材料層184可包括，但不限於一金屬層，例如銅、鎳、鋁及其合金等。在一實施例中，該高CTE材料層182及該高彈性模數材料層184可以與供該微電子封裝體100之其他區域使用之材料相同或類似，且實質上使該微電子封裝體100更對稱(例如，比較不會翹曲)。在一實施例中，該翹曲控制結構180包含一含有厚度在大約5μm與50μm之間，且厚度特別為30μm之填二氧化矽環氧樹脂的該高CTE材料層182及含有厚度大約在大約5μm與50μm之間的該高彈性模數材料層184。 As shown in Fig. 1, a Nitto NX2 DBF material obtained, for example, by Nitto Denko of Japan 910-0381 Fukui Sakai Maruoka Funayose 110-1-1, may be disposed on the back surface 108 of the microelectronic device 102. A warpage control structure 180 can include a high coefficient of thermal expansion (CTE) material layer 182 disposed on the die backside film 172 and a high modulus of elasticity material layer 184 disposed on the high CTE material layer 182. The high CTE material layer 182 may include, but is not limited to, a filled epoxy resin, such as a ruthenium dioxide-filled epoxy resin, including but not limited to Ajinomoto Fine-Techno, 1-2, Suzuki Town, Kawasaki-ku, Kawasaki, Japan 210-0801 The company's Ajinomoto ABF-GX13, Ajinomoto GX92 and so on. The high modulus of elasticity material layer 184 can include, but is not limited to, a metal layer such as copper, nickel, aluminum, alloys thereof, and the like. In one embodiment, the high CTE material layer 182 and the high elastic modulus material layer 184 may be the same or similar to those used for other regions of the microelectronic package 100, and substantially the microelectronic package 100 More symmetrical (for example, less warped). In one embodiment, the warp control structure 180 comprises a high CTE material layer 182 comprising a cerium oxide filled epoxy having a thickness between about 5 μm and 50 μm and a thickness of typically 30 μm and having a thickness of about The layer 184 of high modulus of elasticity material between 5 μm and 50 μm.

設置在一微電子裝置上之具有一高CTE材料層及一高彈性模數材料層兩者的一層結構應產生一較低封裝體翹曲。在一實施例中，該高CTE材料層182可大於大約25微米每米每攝氏度(“ppm/℃”)且該高彈性模數材料層184可大於 大約5京帕斯卡(GPa”)。在此應了解的是該必要之最小CTE及彈性模數值可隨著該微電子裝置之厚度、得到之微電子封裝體之厚度及/或該等材料層之厚度改變。該等最小CTE值係與所考慮之溫度有關，因為大部份環氧樹脂材料在它們的玻璃轉移溫度之前之CTE值(以CTE1表示)及在它們的玻璃轉移溫度之後之CTE值(以CTE2表示)會非常不同。如果必須控制之封裝體翹曲之溫度(例如，室溫或迴焊溫度)低於欲設置之材料之玻璃轉移溫度，則該最小CTE值將稱為CTE1之值，且如果高於該玻璃轉移溫度將稱為之CTE2之值。該最小彈性模數一直稱為在所考慮之溫度下之模數。 A layer of structure having a high CTE material layer and a high modulus of elasticity material layer disposed on a microelectronic device should produce a lower package warpage. In an embodiment, the high CTE material layer 182 can be greater than about 25 microns per meter per degree Celsius ("ppm/° C.") and the high modulus of elasticity material layer 184 can be greater than about 5 MPa (GPa"). It should be understood that the minimum necessary CTE and elastic modulus values may vary with the thickness of the microelectronic device, the thickness of the resulting microelectronic package, and/or the thickness of the layers of the materials. The minimum CTE values are The temperature considerations are due to the fact that most of the epoxy materials will have very different CTE values (expressed as CTE 1 ) and their CTE values (expressed as CTE 2 ) after their glass transition temperature. If the temperature at which the package warpage must be controlled (for example, room temperature or reflow temperature) is lower than the glass transition temperature of the material to be set, the minimum CTE value will be referred to as the value of CTE 1 , and if it is higher than the glass The transfer temperature will be referred to as the value of CTE 2. This minimum modulus of elasticity is always referred to as the modulus at the temperature considered.

在本發明之一實施例中，該翹曲控制結構180可薄到足以嵌入在一堆疊封裝體構形(未顯示)中之一頂封裝體(未顯示)與一底封裝體(例如微電子封裝體100)之間的間隙內且因此，如所屬技術領域中具有通常知識者可了解地，不會增加該堆疊封裝體構形(未顯示)之整體z-高度。在另一實施例中，該高CTE材料層182及該高彈性模數材料層184可選擇成使得翹曲可在室溫(大約攝氏25度)及在迴焊溫度(例如，大約攝氏260度)都減少。 In one embodiment of the invention, the warpage control structure 180 can be thin enough to fit into a top package (not shown) and a bottom package (eg, microelectronics) in a stacked package configuration (not shown). Within the gap between the packages 100) and, therefore, as will be appreciated by those of ordinary skill in the art, the overall z-height of the stacked package configuration (not shown) is not increased. In another embodiment, the high CTE material layer 182 and the high modulus of elasticity material layer 184 can be selected such that the warpage can be at room temperature (about 25 degrees Celsius) and at the reflow temperature (eg, about 260 degrees Celsius). ) are reduced.

如第2圖所示，該晶粒背側薄膜(在第1圖中所示之元件172)可本身作為該高CTE材料層。在一實施例中，一翹曲控制結構190可直接設置在該微電子裝置背面108上，其中該翹曲控制結構180可包含設置在該微電子裝置背面108上之高CTE材料層182及一設置在該高CTE材料層182上之高彈性模數材料層184。該高CTE材料層182可包括，但不限於 晶粒背側薄膜或黏著材料，例如由日本910-0381 Fukui Sakai Maruoka Funayose 110-1-1之Nitto Denko取得之Nitto NX2 DBF材料，或由日本東京101-0021 Chiyoda區Sotokanda 4街14-1之日本鋼鐵化學公司取得之NEX系列材料(例如NEX-130CTX，NEX140DBF)。該高彈性模數材料層184可包括，但不限於一金屬層，例如銅、鎳、鋁及其合金。 As shown in Fig. 2, the grain backside film (element 172 shown in Fig. 1) may itself be the high CTE material layer. In one embodiment, a warpage control structure 190 can be disposed directly on the back surface 108 of the microelectronic device, wherein the warpage control structure 180 can include a high CTE material layer 182 and a layer disposed on the back surface 108 of the microelectronic device. A layer of high modulus of elasticity material 184 disposed on the layer of high CTE material 182. The high CTE material layer 182 can include, but is not limited to, The back side film or adhesive material of the grain, such as Nitto NX2 DBF material obtained by Nitto Denko of Japan 910-0381 Fukui Sakai Maruoka Funayose 110-1-1, or 14-1 of Sotokanda 4 Street, Chiyoda District, Tokyo, Japan 101-0021 NEX series materials obtained by Japan Steel Chemical Co., Ltd. (for example, NEX-130CTX, NEX140DBF). The high modulus of elasticity material layer 184 can include, but is not limited to, a metal layer such as copper, nickel, aluminum, and alloys thereof.

第3-13圖顯示形成一凹孔型無凸塊增層式無核心(BBUL-C)微電子封裝體之一製程之一實施例的橫截面圖。如第3圖所示，可提供一載體200。所示之載體200可以是一銅積層基體，且該銅積層基體包含在兩相對銅釋放層(即一第一銅釋放層204與一第二銅釋放層204')之間的一心材206，並且兩相對銅層(即一第一銅層202及一第二銅層202')抵靠它們的各個銅釋放層(即一第一銅釋放層204與一第二銅釋放層204')且抵靠該心材206之一部份，其中該第一銅層202之外表面界定該載體200之一第一表面208且該第二銅層202'之外表面界定該載體200之一第二表面208'。該心材206可以是任何適當材料，包括但不限於一預浸滲複合纖維材料。應了解的是雖然與該心材206積層之該等層係特別指明為銅層(即該等銅層及該等銅釋放層)，本發明不限於此，因為該等層可以由任何適當材料構成。 Figures 3-13 show cross-sectional views of one embodiment of a process for forming a recessed bumpless build-up coreless (BBUL-C) microelectronic package. As shown in Fig. 3, a carrier 200 can be provided. The illustrated carrier 200 can be a copper laminate substrate, and the copper laminate substrate includes a core material 206 between two opposing copper release layers (ie, a first copper release layer 204 and a second copper release layer 204'). And the two opposing copper layers (ie, a first copper layer 202 and a second copper layer 202') abut each of their copper release layers (ie, a first copper release layer 204 and a second copper release layer 204') and Abutting a portion of the core material 206, wherein an outer surface of the first copper layer 202 defines a first surface 208 of the carrier 200 and an outer surface of the second copper layer 202' defines a second surface of the carrier 200 208'. The core material 206 can be any suitable material including, but not limited to, a pre-impregnated composite fiber material. It should be understood that although the layers laminated with the core material 206 are specifically designated as copper layers (i.e., the copper layers and the copper release layers), the invention is not limited thereto, as the layers may be constructed of any suitable material. .

如第4圖所示，一第一微電子裝置附接墊212可形成在該載體第一表面208上且一第二微電子裝置附接墊212'可形成該載體第二表面208'上。如第4圖進一步所示，該第一微 電子裝置附接墊212可以是例如一第一鎳層之一第一保護層214，及例如一第一銅層之一第一高彈性模數材料層216之層結構，且該第一保護層214抵靠該載體第一表面208並且該第一高彈性模數材料層216抵靠該第一保護層214。又，該第二微電子裝置附接墊212'亦可是例如一第二鎳層之一第二保護層214'，及例如一第二銅層之一第二高彈性模數材料層216'之層結構，且該第二保護層214'抵靠該載體第二表面208'並且該第二高彈性模數材料層216'抵靠該第二保護層214'。該第一保護層214及該第二保護層214'可被用來防止氧化物分別形成在該第一高彈性模數材料層216及該第二高彈性模數材料層216'上，且防止在將說明之後續製造程序時蝕刻該第一高彈性模數材料層216及該第二高彈性模數材料層216'。 As shown in FIG. 4, a first microelectronic device attachment pad 212 can be formed on the carrier first surface 208 and a second microelectronic device attachment pad 212' can be formed on the carrier second surface 208'. As further shown in Figure 4, the first micro The electronic device attachment pad 212 may be, for example, a first protective layer 214 of a first nickel layer, and a layer structure of a first high elastic modulus material layer 216 such as a first copper layer, and the first protective layer 214 abuts the first surface 208 of the carrier and the first layer of high modulus of elasticity material 216 abuts the first protective layer 214. Moreover, the second microelectronic device attachment pad 212' can also be, for example, a second protective layer 214' of a second nickel layer, and a second high modulus of elasticity material layer 216', such as a second copper layer. a layer structure, and the second protective layer 214' abuts the carrier second surface 208' and the second high modulus material layer 216' abuts the second protective layer 214'. The first protective layer 214 and the second protective layer 214' can be used to prevent oxides from being formed on the first high elastic modulus material layer 216 and the second high elastic modulus material layer 216', respectively, and prevent The first high modulus of elasticity material layer 216 and the second layer of high modulus of elasticity material 216' are etched during subsequent fabrication steps as will be described.

如第5圖所示，例如一光阻材料之一第一犧牲材料層222可形成在該載體第一表面208上且在該第一微電子裝置附接墊212上；且例如例如一光阻材料之一第二犧牲材料層222'可形成在該載體第二表面208'上且在該第二微電子裝置附接墊212'上。該第一犧牲材料層222及該第二犧牲材料層222'可藉由在所屬技術領域中習知之任何技術形成，包括但不限於旋塗法、乾光膜積層法、及化學蒸氣沈積法。 As shown in FIG. 5, a first sacrificial material layer 222, such as a photoresist material, may be formed on the first surface 208 of the carrier and on the first microelectronic device attachment pad 212; and for example, a photoresist A second sacrificial material layer 222' of material may be formed on the second surface 208' of the carrier and on the second microelectronic device attachment pad 212'. The first sacrificial material layer 222 and the second sacrificial material layer 222' can be formed by any technique known in the art including, but not limited to, spin coating, dry film lamination, and chemical vapor deposition.

如第6圖所示，一開口224可穿過該第一犧牲材料層222而形成以暴露該第一微電子裝置附接墊212及該載體第一表面208之一部份。一開口224'可同時穿過該第二犧牲材料層222'而形成以暴露該第二微電子裝置附接墊212'及該載 體第二表面208'之一部份。該第一犧牲材料層開口224及該第二犧牲材料層開口224'可藉由在所屬技術領域中習知之任何技術形成，包括但不限於光刻法及濕式或乾式蝕刻法。 As shown in FIG. 6, an opening 224 can be formed through the first sacrificial material layer 222 to expose a portion of the first microelectronic device attachment pad 212 and the first surface 208 of the carrier. An opening 224' can be simultaneously formed through the second sacrificial material layer 222' to expose the second microelectronic device attachment pad 212' and the carrier A portion of the second surface 208' of the body. The first sacrificial material layer opening 224 and the second sacrificial material layer opening 224' can be formed by any technique known in the art including, but not limited to, photolithography and wet or dry etching.

如第7圖所示，多數疊合式封裝(PoP)墊可形成在第一犧牲材料層222及該第二犧牲材料層222'上。第7圖顯示一第一疊合式封裝墊228a及一形成在該第一犧牲材料層222上之第二疊合式封裝墊228b，以及一第三疊合式封裝墊228a'及一形成在該第二犧牲材料層222'上之第四疊合式封裝墊228b'。該等疊合式封裝墊(例如，元件228a、228b、228a'、228b')可以是層狀金屬結構，例如一金、鎳及銅層，且該層狀金屬結構可藉由包括但不限於鍍敷之在所屬技術領域中習知之任何技術圖案化。如所屬技術領域中具有通常知識者可了解地，該等疊合式封裝墊可用來在不需要貫穿矽通孔之情形下，以一z方向(請參見第1圖)在微電子裝置封裝體之間形成多數連接部以便堆疊(例如，所謂3D堆疊)。 As shown in FIG. 7, a plurality of stacked package (PoP) pads may be formed on the first sacrificial material layer 222 and the second sacrificial material layer 222'. 7 shows a first stacked package pad 228a and a second stacked package pad 228b formed on the first sacrificial material layer 222, and a third stacked package pad 228a' and a second formed thereon. A fourth stacked package pad 228b' on the sacrificial material layer 222'. The stacked package pads (eg, elements 228a, 228b, 228a', 228b') may be layered metal structures, such as a gold, nickel, and copper layer, and the layered metal structures may be by, but not limited to, plated It is patterned by any technique known in the art. As will be appreciated by those of ordinary skill in the art, the stacked package pads can be used in a z-direction (see Figure 1) in a microelectronic device package without the need to penetrate through the vias. A plurality of connections are formed to be stacked (for example, a so-called 3D stack).

如第8圖所示，一第一微電子裝置242可藉由其一背面250與一高CTE材料層244一起附接在該第一犧牲材料層開口224內之載體第一表面208上。該第一微電子裝置242可在其一主動表面248上具有至少一接觸焊墊(顯示為元件246a與246b)。一第二微電子裝置242'可藉由其一背面250'與一高CTE材料層244'一起附接在該第二犧牲材料層開口224'內之載體第二表面208'上。該第二微電子裝置242'可可在其一主動表面248'上具有至少一接觸焊墊(顯示為元件246a'與246b')。該第一微電子裝置242及該第二微電子裝置242'可 以是任何所需裝置，包括但不限於一微處理器(單核心或多核心)，一記憶體裝置，一晶片組，一繪圖裝置，一特殊應用積體電路等。該等高CTE材料層244與244'可為任何適當材料，包括但不限於晶粒背側薄膜材料。 As shown in FIG. 8, a first microelectronic device 242 can be attached to the carrier first surface 208 within the first sacrificial material layer opening 224 by a back side 250 thereof along with a high CTE material layer 244. The first microelectronic device 242 can have at least one contact pad (shown as elements 246a and 246b) on an active surface 248 thereof. A second microelectronic device 242' can be attached to the carrier second surface 208' within the second sacrificial material layer opening 224' by a back side 250' thereof along with a high CTE material layer 244'. The second microelectronic device 242' may have at least one contact pad (shown as elements 246a' and 246b') on an active surface 248' thereof. The first microelectronic device 242 and the second microelectronic device 242 ′ are Any desired device, including but not limited to a microprocessor (single core or multi-core), a memory device, a chipset, a graphics device, a special application integrated circuit, and the like. The contoured CTE material layers 244 and 244' can be any suitable material including, but not limited to, a grain backside film material.

如第9圖所示，一第一封裝層252可形成在該第一微電子裝置242，該第一犧牲材料層開口224，該第一疊合式封裝墊228a，及該第二疊合式封裝墊228b上。一第二封裝層252'可同時形成在該第二微電子裝置242'，該第二犧牲材料層開口224'，該第三疊合式封裝墊228a'，及該第四疊合式封裝墊228b'上。在一實施例中，該第一封裝層252及該第二封裝層252'可包含填二氧化矽環氧樹脂。 As shown in FIG. 9, a first encapsulation layer 252 can be formed on the first microelectronic device 242, the first sacrificial material layer opening 224, the first stacked package pad 228a, and the second stacked package pad. On 228b. A second encapsulation layer 252 ′ can be simultaneously formed on the second microelectronic device 242 ′, the second sacrificial material layer opening 224 ′, the third stacked package pad 228 a ′, and the fourth stacked package pad 228 b ′ on. In an embodiment, the first encapsulation layer 252 and the second encapsulation layer 252 ′ may comprise a cerium oxide filled epoxy resin.

如第10圖所示，一第一增層262可形成在該第一封裝層252上。該第一增層262可包含多數介電層，且多數導電線路與各介電層相鄰地形成並且多數導電通孔延伸穿過各介電層以連接在不同層上之導電線路。請參閱第10圖，該第一增層262可包含至少一第一層導電線路272，且一第一增建介電層274與該第一層導電線路272及該第一封裝層252相鄰地形成。至少一線路至裝置導電通孔276可延伸穿過該第一增建介電層274以連接至少一第一層導電線路272與至少一微電子裝置接觸焊墊(例如元件246a與246b)。至少一線路至墊導電通孔278可延伸穿過該第一增建介電層274以連接至少一第一層導電線路272與至少一疊合式封裝墊(例如，元件228a與228b)。至少一第二層導電線路282可與該第一增建介電層274相鄰地形成且一第二增建介電層284可 與該第二層導電線路282及該第一增建介電層274相鄰地形成。至少一線路至線路導電通孔286可延伸穿過該第一增建介電層274以連接至少一第一層導電線路272與至少一第二層導電線路282。至少一第三層導電線路292可形成在該第二增建介電層284上且至少一線路至線路導電通孔286可延伸穿過該第二增建介電層284以連接至少一第二層導電線路282與至少一第三層導電線路292。一阻焊材料294可在該第二增建介電層284及該第三層導電線路292上圖案化且具有至少一暴露該第三層導電線路292之至少一部份的開口296。應了解的是例如焊料球之多數互連結構(未顯示)可形成在該(等)第三層導電線路292上穿過該(等)阻焊材料開口296。 As shown in FIG. 10, a first buildup layer 262 can be formed on the first encapsulation layer 252. The first build-up layer 262 can include a plurality of dielectric layers, and a plurality of conductive traces are formed adjacent to the respective dielectric layers and a plurality of conductive vias extend through the respective dielectric layers to connect the conductive traces on the different layers. Referring to FIG. 10 , the first build-up layer 262 can include at least one first conductive trace 272 , and a first build-up dielectric layer 274 is adjacent to the first conductive trace 272 and the first package layer 252 . Ground formation. At least one line-to-device conductive via 276 can extend through the first build-up dielectric layer 274 to connect at least one first conductive trace 272 to at least one microelectronic device contact pad (eg, elements 246a and 246b). At least one line-to-pad conductive via 278 can extend through the first build-up dielectric layer 274 to connect at least a first layer of conductive traces 272 with at least one of the stacked package pads (eg, elements 228a and 228b). At least one second conductive layer 282 can be formed adjacent to the first additional dielectric layer 274 and a second additional dielectric layer 284 can be Formed adjacent to the second layer of conductive traces 282 and the first build-up dielectric layer 274. At least one line-to-line conductive via 286 can extend through the first build-up dielectric layer 274 to connect the at least one first conductive trace 272 to the at least one second conductive trace 282. At least one third layer of conductive traces 292 may be formed on the second build-up dielectric layer 284 and at least one line-to-line conductive via 286 may extend through the second build-up dielectric layer 284 to connect at least a second The layer conductive line 282 and the at least one third layer conductive line 292. A solder resist material 294 can be patterned over the second build-up dielectric layer 284 and the third layer of conductive traces 292 and has at least one opening 296 that exposes at least a portion of the third layer of conductive traces 292. It will be appreciated that a plurality of interconnect structures (not shown), such as solder balls, may be formed over the (etc.) third layer of conductive traces 292 through the (and other) solder resist openings 296.

如第10圖進一步所示，一第二增層262'可形成在該第二封裝層252'上。該第二增層262'可包含多數介電層，且多數導電線路與各介電層相鄰地形成並且多數導電通孔延伸穿過各介電層以連接在不同層上之導電線路。請參閱第10圖，該第二增層262'可包含至少一第一層導電線路272'，且一第一增建介電層274'與該第一層導電線路272'及該第二封裝層252'相鄰地形成。至少一線路至裝置導電通孔276'可延伸穿過該第一增建介電層274'以連接至少一第一層導電線路272'與至少一微電子裝置接觸焊墊(例如元件246a'與246b')。至少一線路至墊導電通孔278'可延伸穿過該第一增建介電層274'以連接至少一第一層導電線路272'與至少一疊合式封裝墊(例如，元件228a'與228b')。至少一第二層導 電線路282'可與該第一增建介電層274'相鄰地形成且一第二增建介電層284'可與該第二層導電線路282'及該第一增建介電層274'相鄰地形成。至少一線路至線路導電通孔286'可延伸穿過該第一增建介電層274'以連接至少一第一層導電線路272'與至少一第二層導電線路282'。至少一第三層導電線路292'可形成在該第二增建介電層284'上且至少一線路至線路導電通孔286'可延伸穿過該第二增建介電層284'以連接至少一第二層導電線路282'與至少一第三層導電線路292'。一阻焊材料294'可在該第二增建介電層284'及該第三層導電線路292'上圖案化且具有至少一暴露該第三層導電線路292'之至少一部份的開口296'。應了解的是例如焊料球之多數互連結構(未顯示)可形成在該(等)第三層導電線路292'上穿過該(等)阻焊材料開口296'。 As further shown in FIG. 10, a second buildup layer 262' can be formed on the second encapsulation layer 252'. The second build-up layer 262' can comprise a plurality of dielectric layers, and a plurality of conductive traces are formed adjacent to the respective dielectric layers and a plurality of conductive vias extend through the respective dielectric layers to connect the conductive traces on the different layers. Referring to FIG. 10, the second build-up layer 262' may include at least one first conductive layer 272', and a first additional dielectric layer 274' and the first conductive trace 272' and the second package. Layer 252' is formed adjacently. At least one line-to-device conductive via 276' may extend through the first build-up dielectric layer 274' to connect at least one first conductive trace 272' to at least one microelectronic device contact pad (eg, component 246a') 246b'). At least one line-to-pad conductive via 278' may extend through the first build-up dielectric layer 274' to connect at least one first conductive trace 272' with at least one stacked package pad (eg, elements 228a' and 228b) '). At least one second layer guide An electrical line 282 ′ can be formed adjacent to the first additional dielectric layer 274 ′ and a second additional dielectric layer 284 ′ can be coupled to the second conductive line 282 ′ and the first additional dielectric layer 274' is formed adjacently. At least one line-to-line conductive via 286' may extend through the first build-up dielectric layer 274' to connect at least one first conductive trace 272' and at least one second conductive trace 282'. At least one third layer of conductive traces 292' may be formed on the second build-up dielectric layer 284' and at least one trace-to-line conductive via 286' may extend through the second build-up dielectric layer 284' to connect At least one second conductive line 282' and at least one third conductive line 292'. A solder resist material 294' may be patterned on the second build-up dielectric layer 284' and the third layer conductive trace 292' and have at least one opening exposing at least a portion of the third layer conductive trace 292' 296'. It will be appreciated that a plurality of interconnect structures (not shown), such as solder balls, may be formed over the (etc.) third layer of conductive traces 292' through the (and the like) solder resist opening 296'.

該等線路(例如元件272、272'、282、282'、292及292')可以是包括但不限於銅、鋁、銀、金及其合金之任何適當導電材料，且可由包括但不限於光刻法及鍍敷法之在所屬技術領域中習知之任何技術製成。該等導電通孔(例如元件276、276'、278、278'、286及286')可以是包括但不限於銅、鋁、銀、金及其合金之任何適當導電材料，且可由包括但不限於雷射鑽孔法、離子鑽孔、光刻法、鍍敷法及沈積法之在所屬技術領域中習知之任何技術製成。 The lines (eg, elements 272, 272', 282, 282', 292, and 292') may be any suitable electrically conductive material including, but not limited to, copper, aluminum, silver, gold, and alloys thereof, and may include, but are not limited to, light. Engraving and plating are made by any technique known in the art. The conductive vias (eg, elements 276, 276', 278, 278', 286, and 286') may be any suitable conductive material including, but not limited to, copper, aluminum, silver, gold, and alloys thereof, and may include but not Laser drilling, ion drilling, photolithography, plating, and deposition are limited to any technique known in the art.

應了解的是可增建另外之介電層、導電通孔及導電線路以形成所需數目之增層。 It will be appreciated that additional dielectric layers, conductive vias, and conductive traces can be added to form the desired number of buildup layers.

如此形成在該載體第一表面208上及在該載體第二表 面208'上之結構可以如在所屬技術領域中習知地利用一分板程序互相分開。第11圖顯示在分板後形成在該載體第一表面208上之結構。如第12圖所示，可例如，藉由蝕刻程序由該載體200移除在分板後留下之銅層202。如第13圖所示，如所屬技術領域中具有通常知識者可了解地，可例如，藉由電漿拋光、噴砂或溶劑脫離移除該第一犧牲材料層222以形成一微電子裝置封裝體290。因此，第3-13圖之製程形成一包含至少該高CTE材料層244及該第一高彈性模數材料層216之翹曲控制結構295。 So formed on the first surface 208 of the carrier and in the second table of the carrier The structures on face 208' can be separated from each other using a splitter procedure as is known in the art. Figure 11 shows the structure formed on the first surface 208 of the carrier after the sub-board. As shown in FIG. 12, the copper layer 202 remaining after the sub-board can be removed from the carrier 200 by, for example, an etching process. As shown in FIG. 13, the first sacrificial material layer 222 can be removed, for example, by plasma polishing, sand blasting, or solvent detachment to form a microelectronic device package, as will be appreciated by those of ordinary skill in the art. 290. Thus, the process of Figures 3-13 forms a warp control structure 295 comprising at least the high CTE material layer 244 and the first high modulus of elasticity material layer 216.

如所屬技術領域中具有通常知識者可了解地，可進行另外之加工步驟，包括但不限於分割、堆疊及封裝。 Additional processing steps may be performed, including but not limited to segmentation, stacking, and packaging, as will be appreciated by those of ordinary skill in the art.

第14-25圖顯示形成一埋入型無凸塊增層式無核心(BBUL-C)微電子封裝體之一製程之另一實施例的橫截面圖。如第14圖所示，可提供一載體，例如第3圖之載體200，且可在該載體上形成至少一支座。如圖所示，一第一微電子裝置附接墊312可形成在該載體第一表面208上且一第二微電子裝置附接墊312'可形成該載體第二表面208'上。如第14圖進一步所示，該第一微電子裝置附接墊312可以是例如一鎳層之一第一保護層314，及例如一銅層之一第一高彈性模數材料層316之層結構，且該第一保護層314抵靠該載體第一表面208並且該第一高彈性模數材料層316抵靠該第一保護層314。又，該第二微電子裝置附接墊312'亦可是例如一鎳層之一第二保護層314'，及例如一銅層之一第二高彈性模數材料層316'之層結構，且該第二保護層314'抵靠該載體 第二表面208'並且該第二高彈性模數材料層316'抵靠該第二保護層314'。 Figures 14-25 show cross-sectional views of another embodiment of a process for forming a buried bumpless build-up coreless (BBUL-C) microelectronic package. As shown in Fig. 14, a carrier, such as carrier 200 of Fig. 3, may be provided and at least one seat may be formed on the carrier. As shown, a first microelectronic device attachment pad 312 can be formed on the carrier first surface 208 and a second microelectronic device attachment pad 312' can be formed on the carrier second surface 208'. As further shown in FIG. 14, the first microelectronic device attachment pad 312 can be, for example, a first protective layer 314 of a nickel layer, and a layer of a first high modulus of elasticity material layer 316, such as a copper layer. Structure, and the first protective layer 314 abuts the carrier first surface 208 and the first high modulus of elasticity material layer 316 abuts the first protective layer 314. Moreover, the second microelectronic device attachment pad 312' may also be, for example, a second protective layer 314' of a nickel layer, and a layer structure of a second high modulus of elasticity material layer 316', such as a copper layer, and The second protective layer 314' abuts the carrier The second surface 208' and the second high modulus of elasticity material layer 316' abut the second protective layer 314'.

如第15圖所示，多數疊合式封裝(PoP)墊可形成在該載體第一表面208上及在該載體第二表面208'上。第15圖顯示一第一疊合式封裝墊328a及一形成在該載體第一表面208上之第二疊合式封裝墊328b，以及一第三疊合式封裝墊328a'及一形成在該載體第二表面208'上之第四疊合式封裝墊328b'。該等疊合式封裝墊(例如，元件328a、328b、328a'、328b')可以是層狀金屬結構，例如一金、鎳及銅層，且該層狀金屬結構可藉由包括但不限於鍍敷之在所屬技術領域中習知之任何技術圖案化。 As shown in FIG. 15, a plurality of stacked package (PoP) pads may be formed on the first surface 208 of the carrier and on the second surface 208' of the carrier. 15 shows a first stacked package pad 328a and a second stacked package pad 328b formed on the first surface 208 of the carrier, and a third stacked package pad 328a' and a second formed on the carrier. A fourth stacked package pad 328b' on surface 208'. The stacked package pads (eg, elements 328a, 328b, 328a', 328b') may be layered metal structures, such as a gold, nickel, and copper layer, and the layered metal structures may be by, but not limited to, plated It is patterned by any technique known in the art.

如第16圖所示，一第一微電子裝置342可藉由其一背面350與一高CTE材料344一起附接在該第一微電子裝置附接墊312上。該第一微電子裝置342可在其一主動表面348上具有至少一接觸焊墊(顯示為元件346a與346b)。一第二微電子裝置342'可藉由其一背面350'與一高CTE材料344'一起附接在該第二微電子裝置附接墊312'上。該第二微電子裝置342'可在其一主動表面348'上具有至少一接觸焊墊(顯示為元件346a'與346b')。該第一微電子裝置342及該第二微電子裝置342'可以是任何所需裝置，包括但不限於一微處理器(單核心或多核心)，一記憶體裝置，一晶片組，一繪圖裝置，一特殊應用積體電路等。該等高CTE材料344與244'可為任何適當材料，包括但不限於晶粒背側薄膜材料。 As shown in FIG. 16, a first microelectronic device 342 can be attached to the first microelectronic device attachment pad 312 by a back side 350 thereof along with a high CTE material 344. The first microelectronic device 342 can have at least one contact pad (shown as elements 346a and 346b) on an active surface 348 thereof. A second microelectronic device 342' can be attached to the second microelectronic device attachment pad 312' by a back side 350' thereof along with a high CTE material 344'. The second microelectronic device 342' can have at least one contact pad (shown as elements 346a' and 346b') on an active surface 348' thereof. The first microelectronic device 342 and the second microelectronic device 342' may be any required devices, including but not limited to a microprocessor (single core or multi-core), a memory device, a chip set, a drawing Device, a special application integrated circuit, etc. The high CTE materials 344 and 244' can be any suitable material including, but not limited to, a grain backside film material.

如第17圖所示，一第一封裝層352可形成在該第一微電 子裝置342，該載體第一表面208，該第一疊合式封裝墊328a，及該第二疊合式封裝墊328b上。一第二封裝層352'可同時形成在該第二微電子裝置342'，該第三疊合式封裝墊328a'，及該第四疊合式封裝墊328b'上。在一實施例中，該第一封裝層352及該第二封裝層352'可包含填二氧化矽環氧樹脂。 As shown in FIG. 17, a first encapsulation layer 352 can be formed on the first micro-electric The sub-device 342, the carrier first surface 208, the first stacked package pad 328a, and the second stacked package pad 328b. A second encapsulation layer 352' can be simultaneously formed on the second microelectronic device 342', the third stacked package pad 328a', and the fourth stacked package pad 328b'. In an embodiment, the first encapsulation layer 352 and the second encapsulation layer 352' may comprise a cerium oxide epoxy resin.

如第18圖所示，一第一增層362可形成在該第一封裝層352上。該第一增層362可包含多數介電層，且多數導電線路與各介電層相鄰地形成並且多數導電通孔延伸穿過各介電層以連接在不同層上之導電線路。請參閱第18圖，該第一增層362可包含至少一第一層導電線路372，且一第一增建介電層374與該第一層導電線路372及該第一封裝層352相鄰地形成。至少一線路至裝置導電通孔376可延伸穿過該第一增建介電層374以連接至少一第一層導電線路372與至少一微電子裝置接觸焊墊(例如元件346a與346b)。至少一線路至墊導電通孔378可延伸穿過該第一增建介電層374以連接至少一第一層導電線路372與至少一疊合式封裝墊(例如，元件328a與328b)。至少一第二層導電線路382可與該第一增建介電層374相鄰地形成且一第二增建介電層384可與該第二層導電線路382及該第一增建介電層374相鄰地形成。至少一線路至線路導電通孔386可延伸穿過該第一增建介電層374以連接至少一第一層導電線路372與至少一第二層導電線路382。至少一第三層導電線路392可形成在該第二增建介電層384上且至少一線路至線路導電通孔386可延 伸穿過該第二增建介電層384以連接至少一第二層導電線路382與至少一第三層導電線路392。一阻焊材料394可在該第二增建介電層384及該第三層導電線路392上圖案化且具有至少一暴露該第三層導電線路392之至少一部份的開口396。應了解的是例如焊料球之多數互連結構(未顯示)可形成在該(等)第三層導電線路392上穿過該(等)阻焊材料開口396。 As shown in FIG. 18, a first buildup layer 362 can be formed on the first encapsulation layer 352. The first build-up layer 362 can include a plurality of dielectric layers, and a plurality of conductive traces are formed adjacent to the respective dielectric layers and a plurality of conductive vias extend through the respective dielectric layers to connect the conductive traces on the different layers. Referring to FIG. 18 , the first build-up layer 362 can include at least one first conductive layer 372 , and a first additional dielectric layer 374 is adjacent to the first conductive layer 372 and the first package layer 352 . Ground formation. At least one line-to-device conductive via 376 can extend through the first build-up dielectric layer 374 to connect at least one first conductive trace 372 to at least one microelectronic device contact pad (eg, elements 346a and 346b). At least one line-to-pad conductive via 378 can extend through the first build-up dielectric layer 374 to connect at least one first conductive trace 372 with at least one stacked package pad (eg, elements 328a and 328b). At least one second conductive layer 382 can be formed adjacent to the first additional dielectric layer 374 and a second additional dielectric layer 384 can be associated with the second conductive layer 382 and the first additional dielectric Layers 374 are formed adjacent to each other. At least one line-to-line conductive via 386 can extend through the first build-up dielectric layer 374 to connect at least one first conductive trace 372 to at least one second conductive trace 382. At least one third layer of conductive traces 392 may be formed on the second build-up dielectric layer 384 and at least one of the trace-to-line conductive vias 386 may be extended The second build-up dielectric layer 384 extends through the second build-up dielectric layer 382 to connect at least a second conductive trace 382 to the at least one third conductive trace 392. A solder resist material 394 can be patterned over the second build-up dielectric layer 384 and the third layer of conductive traces 392 and has at least one opening 396 that exposes at least a portion of the third layer of conductive traces 392. It will be appreciated that a plurality of interconnect structures (not shown), such as solder balls, may be formed over the (etc.) third layer of conductive traces 392 through the (and other) solder resist openings 396.

如第18圖進一步所示，一第二增層362'可形成在該第二封裝層352'上。該第二增層362'可包含多數介電層，且多數導電線路與各介電層相鄰地形成並且多數導電通孔延伸穿過各介電層以連接在不同層上之導電線路。請參閱第18圖，該第二增層362'可包含至少一第一層導電線路372'，且一第一增建介電層374'與該第一層導電線路372'及該第二封裝層352'相鄰地形成。至少一線路至裝置導電通孔376'可延伸穿過該第一增建介電層374'以連接至少一第一層導電線路372'與至少一微電子裝置接觸焊墊(例如元件346a'與346b')。至少一線路至墊導電通孔378'可延伸穿過該第一增建介電層374'以連接至少一第一層導電線路372'與至少一疊合式封裝墊(例如，元件328a'與328b')。至少一第二層導電線路382'可與該第一增建介電層374'相鄰地形成且一第二增建介電層384'可與該第二層導電線路382'及該第一增建介電層374'相鄰地形成。至少一線路至線路導電通孔386'可延伸穿過該第一增建介電層374'以連接至少一第一層導電線路372'與至少一第二層導電線路382'。至少一第三層導 電線路392'可形成在該第二增建介電層384'上且至少一線路至線路導電通孔386'可延伸穿過該第二增建介電層384'以連接至少一第二層導電線路382'與至少一第三層導電線路392'。一阻焊材料394'可在該第二增建介電層384'及該第三層導電線路392'上圖案化且具有至少一暴露該第三層導電線路392'之至少一部份的開口396'。應了解的是例如焊料球之多數互連結構(未顯示)可形成在該(等)第三層導電線路392'上穿過該(等)阻焊材料開口396'。 As further shown in FIG. 18, a second buildup layer 362' can be formed on the second encapsulation layer 352'. The second build-up layer 362' can comprise a plurality of dielectric layers, and a plurality of conductive traces are formed adjacent to the respective dielectric layers and a plurality of conductive vias extend through the respective dielectric layers to connect the conductive traces on the different layers. Referring to FIG. 18, the second build-up layer 362' may include at least one first conductive layer 372', and a first additional dielectric layer 374' and the first conductive trace 372' and the second package. Layer 352' is formed adjacently. At least one line-to-device conductive via 376' may extend through the first build-up dielectric layer 374' to connect at least one first conductive trace 372' to at least one microelectronic device contact pad (eg, component 346a') 346b'). At least one line-to-pad conductive via 378' can extend through the first build-up dielectric layer 374' to connect at least one first conductive trace 372' with at least one stacked package pad (eg, elements 328a' and 328b) '). At least one second conductive layer 382 ′ can be formed adjacent to the first additional dielectric layer 374 ′ and a second additional dielectric layer 384 ′ can be coupled to the second conductive layer 382 ′ and the first An additional dielectric layer 374' is formed adjacently. At least one line-to-line conductive via 386' may extend through the first build-up dielectric layer 374' to connect at least one first conductive trace 372' and at least one second conductive trace 382'. At least one third layer guide Electrical lines 392' may be formed on the second additional dielectric layer 384' and at least one line-to-line conductive via 386' may extend through the second additional dielectric layer 384' to connect at least a second layer Conductive line 382' and at least a third layer of conductive line 392'. A solder resist material 394' may be patterned on the second build dielectric layer 384' and the third layer conductive trace 392' and have at least one opening exposing at least a portion of the third layer conductive trace 392' 396'. It will be appreciated that a plurality of interconnect structures (not shown), such as solder balls, may be formed over the (etc.) third layer of conductive traces 392' through the (and the like) solder resist opening 396'.

該等線路(例如元件372、372'、382、382'、392及3°92')可以是包括但不限於銅、鋁、銀、金及其合金之任何適當導電材料，且可由包括但不限於光刻法及鍍敷法之在所屬技術領域中習知之任何技術製成。該等導電通孔(例如元件376、376'、378、378'、386及386')可以是包括但不限於銅、鋁、銀、金及其合金之任何適當導電材料，且可由包括但不限於雷射鑽孔法、離子鑽孔、光刻法、鍍敷法及沈積法之在所屬技術領域中習知之任何技術製成。 The lines (eg, elements 372, 372', 382, 382', 392, and 3° 92') may be any suitable conductive material including, but not limited to, copper, aluminum, silver, gold, and alloys thereof, and may include but not It is limited to any technique known in the art for photolithography and plating. The conductive vias (eg, elements 376, 376', 378, 378', 386, and 386') may be any suitable conductive material including, but not limited to, copper, aluminum, silver, gold, and alloys thereof, and may include but not Laser drilling, ion drilling, photolithography, plating, and deposition are limited to any technique known in the art.

應了解的是可增建另外之介電層、導電通孔及導電線路以形成所需數目之增層。 It will be appreciated that additional dielectric layers, conductive vias, and conductive traces can be added to form the desired number of buildup layers.

如此形成在該載體第一表面208上及在該載體第二表面208'上之結構可以如在所屬技術領域中習知地利用一分板程序互相分開。第19圖顯示在分板後形成在該載體第一表面208上之結構。如第20圖所示，可例如，藉由蝕刻程序由該載體200移除在分板後留下之銅層202，以形成一微電子裝置封裝體390。因此，第14-20圖之製程形成一包含至 少該高CTE材料層344及該高彈性模數材料層316之翹曲控制結構395。 The structures thus formed on the first surface 208 of the carrier and on the second surface 208' of the carrier can be separated from one another by a splitter procedure as is conventional in the art. Figure 19 shows the structure formed on the first surface 208 of the carrier after the sub-board. As shown in FIG. 20, the copper layer 202 remaining after the sub-board can be removed from the carrier 200 by an etching process, for example, to form a microelectronic device package 390. Therefore, the processes of Figures 14-20 form an inclusion to The high CTE material layer 344 and the warpage control structure 395 of the high elastic modulus material layer 316 are less.

如所屬技術領域中具有通常知識者可了解地，可進行另外之加工步驟，包括但不限於分割、堆疊及封裝。 Additional processing steps may be performed, including but not limited to segmentation, stacking, and packaging, as will be appreciated by those of ordinary skill in the art.

在此應了解的是本發明之標的物不一定限定於第1-20圖所示之特定應用。該標的物可應用於包括會與翹曲有關之其他無核心及薄核心封裝體的其他微電子裝置封裝應用。此外，包括但不限於玻璃布積層、模製等在所屬技術領域中習知之其他翹曲減少技術可與本發明之標的物組合。另外，如所屬技術領域中具有通常知識者可了解地，本發明之標的物可以是一更大之無凸塊增層式封裝體之一部份，它可包括多數堆疊微電子晶粒，它可以一晶圓級，或任何次數之適當變化形成。又，該標的物亦可被使用在該微電子裝置製造領域以外之任何適當應用中。 It should be understood that the subject matter of the present invention is not necessarily limited to the particular application shown in Figures 1-20. The subject matter can be applied to other microelectronic device packaging applications including other coreless and thin core packages that are associated with warpage. In addition, other warpage reduction techniques known in the art including, but not limited to, glass cloth laminates, molding, etc., can be combined with the subject matter of the present invention. In addition, as will be appreciated by those of ordinary skill in the art, the subject matter of the present invention can be part of a larger bumpless build-up package that can include a plurality of stacked microelectronic dies. It can be formed at a wafer level, or any number of times. Moreover, the subject matter can also be used in any suitable application outside of the field of microelectronic device fabrication.

已如此詳細說明了本發明之實施例，應了解的是由於在不偏離本發明之精神或範疇之情形下可有許多其顯而易見之變化，因此由附加申請專利範圍界定之發明不受限於在在以上說明中提出之特定細節。 The embodiments of the present invention have been described in detail, and it is understood that the invention defined by the scope of the appended claims is not limited Specific details are set forth in the above description.

100‧‧‧微電子封裝體 100‧‧‧Microelectronics package

102‧‧‧微電子裝置 102‧‧‧Microelectronics

104‧‧‧主動表面 104‧‧‧Active surface

106‧‧‧接觸焊墊 106‧‧‧Contact pads

108‧‧‧背面 108‧‧‧Back

110‧‧‧側 110‧‧‧ side

112‧‧‧封裝材料 112‧‧‧Packaging materials

114‧‧‧第一表面 114‧‧‧ first surface

116‧‧‧第二表面 116‧‧‧ second surface

122‧‧‧增層 122‧‧‧Additional

132‧‧‧第一層導電線路 132‧‧‧First layer of conductive lines

134‧‧‧第一增建介電層 134‧‧‧First added dielectric layer

136‧‧‧線路至裝置導電通孔 136‧‧‧Line to device conductive through hole

142‧‧‧第二層導電線路 142‧‧‧Second layer conductive line

144‧‧‧第二增建介電層 144‧‧‧Second additional dielectric layer

146‧‧‧線路至線路導電通孔 146‧‧‧Line-to-line conductive vias

152‧‧‧第三層導電線路 152‧‧‧The third layer of conductive lines

154‧‧‧阻焊材料 154‧‧‧Soldering material

156‧‧‧開口 156‧‧‧ openings

162‧‧‧疊合式封裝(PoP)墊 162‧‧‧Positive Package (PoP) Pad

172‧‧‧晶粒背側薄膜 172‧‧‧ grain back film

180‧‧‧翹曲控制結構 180‧‧‧ warpage control structure

182‧‧‧高熱膨脹係數(CTE)材料層 182‧‧‧High thermal expansion coefficient (CTE) material layer

184‧‧‧高彈性模數材料層 184‧‧‧High elastic modulus material layer

190‧‧‧翹曲控制結構 190‧‧‧ warpage control structure

200‧‧‧載體 200‧‧‧ Carrier

202‧‧‧第一銅層 202‧‧‧First copper layer

202'‧‧‧第二銅層 202'‧‧‧Second copper layer

204‧‧‧第一銅釋放層 204‧‧‧First copper release layer

204'‧‧‧第二銅釋放層 204'‧‧‧Second copper release layer

206‧‧‧心材 206‧‧‧heartwood

208‧‧‧第一表面 208‧‧‧ first surface

208'‧‧‧第二表面 208'‧‧‧ second surface

212‧‧‧第一微電子裝置附接墊 212‧‧‧First microelectronic device attachment pad

212'‧‧‧第二微電子裝置附接墊 212'‧‧‧Second microelectronic device attachment pad

214‧‧‧第一保護層 214‧‧‧First protective layer

214'‧‧‧第二保護層 214'‧‧‧Second protective layer

216‧‧‧第一高彈性模數材料層 216‧‧‧First high modulus of elasticity material layer

216'‧‧‧第二高彈性模數材料層 216'‧‧‧Second high modulus of elasticity material layer

222‧‧‧第一犧牲材料層 222‧‧‧First sacrificial material layer

222'‧‧‧第二犧牲材料層 222'‧‧‧Second sacrificial material layer

224,224'‧‧‧開口 224,224'‧‧‧ openings

228a‧‧‧第一疊合式封裝墊 228a‧‧‧First laminated pad

228b‧‧‧第二疊合式封裝墊 228b‧‧‧Second stacking pad

228a'‧‧‧第三疊合式封裝墊 228a'‧‧‧ Third laminated package pad

228b'‧‧‧第四疊合式封裝墊 228b'‧‧‧fourth stacking pad

242‧‧‧第一微電子裝置 242‧‧‧First microelectronic device

242'‧‧‧第二微電子裝置 242'‧‧‧Second microelectronic device

244,244'‧‧‧高CTE材料層 244,244'‧‧‧High CTE material layer

246a,246b‧‧‧接觸焊墊 246a, 246b‧‧‧Contact pads

246a',246b'‧‧‧接觸焊墊 246a', 246b'‧‧‧ contact pads

248,248'‧‧‧主動表面 248,248'‧‧‧ active surface

250,250'‧‧‧背面 250,250'‧‧‧ back

252‧‧‧第一封裝層 252‧‧‧First encapsulation layer

252'‧‧‧第二封裝層 252'‧‧‧Second encapsulation layer

262‧‧‧第一增層 262‧‧‧First buildup

262'‧‧‧第二增層 262'‧‧‧Second layer

272,272'‧‧‧第一層導電線路 272,272'‧‧‧First conductive line

274,274'‧‧‧第一增建介電層 274, 274'‧‧‧First added dielectric layer

276,276'‧‧‧線路至裝置導電通孔 276,276'‧‧‧Line to device conductive through hole

278,278'‧‧‧線路至墊導電通孔 278,278'‧‧‧Line to pad conductive via

282,282'‧‧‧第二層導電線路 282,282'‧‧‧Second layer conductive line

284,284'‧‧‧第二增建介電層 284,284'‧‧‧Second additional dielectric layer

286,286'‧‧‧線路至線路導電通孔 286, 286'‧‧‧Line-to-line conductive vias

290‧‧‧微電子裝置封裝體 290‧‧‧Microelectronic device package

292,292'‧‧‧第三層導電線路 292,292'‧‧‧third layer conductive line

294,294'‧‧‧阻焊材料 294,294'‧‧‧ soldering material

295‧‧‧翹曲控制結構 295‧‧‧ warpage control structure

296,296'‧‧‧開口 296,296'‧‧‧ openings

312‧‧‧第一微電子裝置附接墊 312‧‧‧First microelectronic device attachment pad

312'‧‧‧第二微電子裝置附接墊 312'‧‧‧Second microelectronic device attachment pad

314‧‧‧第一保護層 314‧‧‧First protective layer

314'‧‧‧第二保護層 314'‧‧‧Second protective layer

316‧‧‧第一高彈性模數材料層 316‧‧‧First high elastic modulus material layer

316'‧‧‧第二高彈性模數材料層 316'‧‧‧Second high modulus of elasticity material layer

328a‧‧‧第一疊合式封裝墊 328a‧‧‧First laminated pad

328b‧‧‧第二疊合式封裝墊 328b‧‧‧Second stacking pad

328a'‧‧‧第三疊合式封裝墊 328a'‧‧‧Third-stacked packing mat

328b'‧‧‧第四疊合式封裝墊 328b'‧‧‧fourth stacking pad

342‧‧‧第一微電子裝置 342‧‧‧First microelectronic device

342'‧‧‧第二微電子裝置 342'‧‧‧Second microelectronic device

344,344'‧‧‧高CTE材料 344,344'‧‧‧High CTE material

346a,346b‧‧‧接觸焊墊 346a, 346b‧‧‧Contact pads

346a',346b'‧‧‧接觸焊墊 346a',346b'‧‧‧Contact pads

348,348'‧‧‧主動表面 348,348'‧‧‧ Active surface

350,350'‧‧‧背面 350,350'‧‧‧ back

352‧‧‧第一封裝層 352‧‧‧First encapsulation layer

352'‧‧‧第二封裝層 352'‧‧‧Second encapsulation layer

362‧‧‧第一增層 362‧‧‧First buildup

362'‧‧‧第二增層 362'‧‧‧Second layer

372,372'‧‧‧第一層導電線路 372,372'‧‧‧First conductive line

374,374'‧‧‧第一增建介電層 374,374'‧‧‧First added dielectric layer

376,376'‧‧‧線路至裝置導電通孔 376,376'‧‧‧Line to device conductive through hole

378,378'‧‧‧線路至墊導電通孔 378,378'‧‧‧Line to pad conductive via

382,382'‧‧‧第二層導電線路 382,382'‧‧‧Second layer conductive line

384,384'‧‧‧第二增建介電層 384,384'‧‧‧Second additional dielectric layer

386,386'‧‧‧線路至線路導電通孔 386,386'‧‧‧Line to line conductive vias

390‧‧‧微電子裝置封裝體 390‧‧‧Microelectronic device package

392,392'‧‧‧第三層導電線路 392,392'‧‧‧3rd conductive line

394,394'‧‧‧阻焊材料 394,394'‧‧‧Soldering material

395‧‧‧翹曲控制結構 395‧‧‧ warpage control structure

396,396'‧‧‧開口 396,396'‧‧‧ openings

第1圖顯示依據本發明一實施例之一無凸塊增層式無核心微電子封裝體的側橫截面圖。 1 shows a side cross-sectional view of a bumpless build-up coreless microelectronic package in accordance with an embodiment of the present invention.

第2圖顯示依據本發明另一實施例之一無凸塊增層式無核心微電子封裝體的側橫截面圖。 2 is a side cross-sectional view showing a bumpless build-up coreless microelectronic package in accordance with another embodiment of the present invention.

第3-13圖顯示依據本發明一實施例之形成一凹孔型無 凸塊增層式無核心微電子封裝體之一製程的橫截面圖。 Figures 3-13 show the formation of a recessed hole type according to an embodiment of the invention. A cross-sectional view of one of the processes of a bump build-up coreless microelectronic package.

第14-20圖顯示依據本發明一實施例之形成一埋入型無凸塊增層式無核心微電子封裝體之一製程的橫截面圖。 14-20 illustrate cross-sectional views of a process for forming a buried bumpless build-up coreless microelectronic package in accordance with an embodiment of the present invention.

100‧‧‧微電子封裝體 100‧‧‧Microelectronics package

102‧‧‧微電子裝置 102‧‧‧Microelectronics

104‧‧‧主動表面 104‧‧‧Active surface

106‧‧‧接觸焊墊 106‧‧‧Contact pads

108‧‧‧背面 108‧‧‧Back

110‧‧‧側 110‧‧‧ side

112‧‧‧封裝材料 112‧‧‧Packaging materials

114‧‧‧第一表面 114‧‧‧ first surface

116‧‧‧第二表面 116‧‧‧ second surface

122‧‧‧增層 122‧‧‧Additional

132‧‧‧第一層導電線路 132‧‧‧First layer of conductive lines

134‧‧‧第一增建介電層 134‧‧‧First added dielectric layer

136‧‧‧線路至裝置導電通孔 136‧‧‧Line to device conductive through hole

142‧‧‧第二層導電線路 142‧‧‧Second layer conductive line

144‧‧‧第二增建介電層 144‧‧‧Second additional dielectric layer

142‧‧‧第二層導電線路 142‧‧‧Second layer conductive line

144‧‧‧第二增建介電層 144‧‧‧Second additional dielectric layer

146‧‧‧線路至線路導電通孔 146‧‧‧Line-to-line conductive vias

152‧‧‧第三層導電線路 152‧‧‧The third layer of conductive lines

154‧‧‧阻焊材料 154‧‧‧Soldering material

156‧‧‧開口 156‧‧‧ openings

162‧‧‧疊合式封裝(PoP)墊 162‧‧‧Positive Package (PoP) Pad

172‧‧‧晶粒背側薄膜 172‧‧‧ grain back film

180‧‧‧翹曲控制結構 180‧‧‧ warpage control structure

182‧‧‧高熱膨脹係數(CTE)材料層 182‧‧‧High thermal expansion coefficient (CTE) material layer

184‧‧‧高彈性模數材料層 184‧‧‧High elastic modulus material layer

Claims (20)

一種微電子封裝體，包含：一微電子裝置，其具有一主動表面、一相對的背面、及至少一側；及一翹曲控制結構，其與該微電子裝置背面相鄰，其中該翹曲控制結構包括一高熱膨脹係數材料層及一高彈性模數材料層。 A microelectronic package comprising: a microelectronic device having an active surface, an opposite back surface, and at least one side; and a warpage control structure adjacent to a back surface of the microelectronic device, wherein the warpage The control structure includes a layer of high coefficient of thermal expansion material and a layer of high modulus of elasticity material. 如申請專利範圍第1項之微電子封裝體，其中該高熱膨脹係數材料層包含一材料，且該材料具有一大於約25ppm/℃之熱膨脹係數。 The microelectronic package of claim 1, wherein the high coefficient of thermal expansion material layer comprises a material having a coefficient of thermal expansion greater than about 25 ppm/°C. 如申請專利範圍第1項之微電子封裝體，其中該高熱膨脹係數材料層包含一填充環氧樹脂材料層。 The microelectronic package of claim 1, wherein the high coefficient of thermal expansion material layer comprises a layer of filled epoxy material. 如申請專利範圍第1項之微電子封裝體，其中該高彈性模數材料層包含一材料層，且該材料層具有一大於約50GPa之模數。 The microelectronic package of claim 1, wherein the high modulus of elasticity material layer comprises a layer of material and the layer of material has a modulus greater than about 50 GPa. 如申請專利範圍第1項之微電子封裝體，其中高彈性模數材料層包含一金屬層。 The microelectronic package of claim 1, wherein the high elastic modulus material layer comprises a metal layer. 如申請專利範圍第1項之微電子封裝體，更包括一封裝材料，且該封裝材料係相鄰該微電子裝置主動表面之至少一部份及至少一微電子裝置側之至少一部份而設置。 The microelectronic package of claim 1, further comprising a package material, wherein the package material is adjacent to at least a portion of the active surface of the microelectronic device and at least a portion of the at least one microelectronic device side. Settings. 如申請專利範圍第6項之微電子封裝體，更包括一增層，且該增層係形成在靠近該微電子裝置主動表面之該封裝材料之一第一表面上。 The microelectronic package of claim 6, further comprising a buildup layer formed on a first surface of the encapsulation material adjacent to the active surface of the microelectronic device. 一種製造一微電子封裝體之方法，其包含下列步驟： 形成一微電子裝置，且該微電子裝置具有一主動表面、一相對的背面、及至少一側；及形成一與該微電子裝置背面相鄰之翹曲控制結構，其包含形成與一高彈性模數材料層相鄰之一高熱膨脹係數材料層。 A method of fabricating a microelectronic package comprising the steps of: Forming a microelectronic device having an active surface, an opposite back surface, and at least one side; and forming a warp control structure adjacent to the back surface of the microelectronic device, the formation comprising a high elasticity A layer of high coefficient of thermal expansion material adjacent to the layer of modulus material. 如申請專利範圍第8項之方法，其中形成該高熱膨脹係數材料層之步驟包含在該微電子裝置背面上形成該高熱膨脹係數材料層。 The method of claim 8, wherein the step of forming the layer of high coefficient of thermal expansion material comprises forming the layer of high coefficient of thermal expansion material on the back side of the microelectronic device. 如申請專利範圍第8項之方法，其中形成該高熱膨脹係數材料層之步驟包含形成具有一大於約25ppm/℃之熱膨脹係數之一材料層。 The method of claim 8, wherein the step of forming the layer of high coefficient of thermal expansion material comprises forming a layer of material having a coefficient of thermal expansion greater than about 25 ppm/°C. 如申請專利範圍第8項之方法，其中形成該高熱膨脹係數材料層之步驟包含形成一填充環氧樹脂材料層。 The method of claim 8, wherein the step of forming the layer of high coefficient of thermal expansion material comprises forming a layer of filled epoxy material. 如申請專利範圍第8項之方法，其中形成該高彈性模數材料層之步驟包含形成具有一大於約50GPa之模數之一材料層。 The method of claim 8, wherein the step of forming the layer of high modulus of elasticity material comprises forming a layer of material having a modulus greater than about 50 GPa. 如申請專利範圍第8項之方法，更包括相鄰該微電子裝置主動表面之至少一部份及至少一微電子裝置側之至少一部份設置一封裝材料。 The method of claim 8, further comprising providing a package material to at least a portion of the active surface adjacent to the microelectronic device and at least a portion of the at least one microelectronic device side. 如申請專利範圍第8項之方法，更包括在靠近該微電子裝置主動表面之該封裝材料之一第一表面上形成一增層。 The method of claim 8, further comprising forming a buildup layer on a first surface of the encapsulating material adjacent to the active surface of the microelectronic device. 一種製造一微電子封裝體之方法，其包含下列步驟：提供一載體； 在該載體上形成一微電子裝置附接墊，其中該微電子裝置附接墊包括一高彈性模數材料層；附接具有一主動表面、一相對的背面、及至少一側之一微電子裝置在該微電子裝置附接墊上，其中附接該微電子裝置之步驟包括將一高熱膨脹係數材料層設置在該微電子裝置背面與該微電子裝置附接墊之間；相鄰該微電子裝置主動表面之至少一部份及至少一微電子裝置側之至少一部份相鄰設置一封裝材料；及移除該載體。 A method of fabricating a microelectronic package, comprising the steps of: providing a carrier; Forming a microelectronic device attachment pad on the carrier, wherein the microelectronic device attachment pad comprises a layer of high elastic modulus material; the attachment has an active surface, an opposite back surface, and at least one of the microelectronics The device is mounted on the microelectronic device attachment pad, wherein the step of attaching the microelectronic device comprises placing a layer of high coefficient of thermal expansion material between the back surface of the microelectronic device and the microelectronic device attachment pad; adjacent to the microelectronic device At least a portion of the active surface of the device and at least a portion of the at least one microelectronic device side are disposed adjacent to an encapsulation material; and the carrier is removed. 如申請專利範圍第15項之方法，其中將一高熱膨脹係數材料層設置在該微電子裝置背面與該微電子裝置附接墊之間的步驟包含將具有一大於約25ppm/℃之熱膨脹係數之一材料層設置在該微電子裝置背面與該微電子裝置附接墊之間。 The method of claim 15, wherein the step of disposing a layer of high coefficient of thermal expansion material between the back side of the microelectronic device and the microelectronic device attachment pad comprises having a coefficient of thermal expansion greater than about 25 ppm/°C. A layer of material is disposed between the back side of the microelectronic device and the microelectronic device attachment pad. 如申請專利範圍第15項之方法，其中將一高熱膨脹係數材料層設置在該微電子裝置背面與該微電子裝置附接墊之間的步驟包含將一填充環氧樹脂材料層設置在該微電子裝置背面與該微電子裝置附接墊之間。 The method of claim 15, wherein the step of disposing a layer of high coefficient of thermal expansion material between the back surface of the microelectronic device and the attachment pad of the microelectronic device comprises disposing a layer of a filled epoxy material in the micro Between the back of the electronic device and the microelectronic device attachment pad. 如申請專利範圍第15項之方法，其中在該載體上形成一微電子裝置附接墊之步驟包含在該載體上形成一微電子裝置附接墊，其中該微電子裝置附接墊包括具有一大於約50GPa之模數之一高彈性模數材料層。 The method of claim 15, wherein the step of forming a microelectronic device attachment pad on the carrier comprises forming a microelectronic device attachment pad on the carrier, wherein the microelectronic device attachment pad comprises one A layer of high modulus of elasticity material greater than one of the modulus of about 50 GPa. 如申請專利範圍第15項之方法，其中設置該封裝材料之步驟包含相鄰該微電子裝置主動表面之至少一部份及 至少一微電子裝置側之至少一部份設置一填充環氧樹脂材料。 The method of claim 15, wherein the step of disposing the encapsulating material comprises adjacent at least a portion of an active surface of the microelectronic device and At least a portion of the at least one microelectronic device side is provided with a filled epoxy material. 如申請專利範圍第15項之方法，更包括在靠近該微電子裝置主動表面之該封裝材料之一第一表面上形成一增層。 The method of claim 15, further comprising forming a buildup layer on a first surface of the encapsulating material adjacent to the active surface of the microelectronic device.
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KR101579823B1 (en) 2015-12-24
US20140363929A1 (en) 2014-12-11
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TWI578469B (en) 2017-04-11
CN103635996A (en) 2014-03-12

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