CN202394963U - Multi-chip wafer-level semiconductor packaging structure - Google Patents
Multi-chip wafer-level semiconductor packaging structure Download PDFInfo
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- CN202394963U CN202394963U CN2011205609003U CN201120560900U CN202394963U CN 202394963 U CN202394963 U CN 202394963U CN 2011205609003 U CN2011205609003 U CN 2011205609003U CN 201120560900 U CN201120560900 U CN 201120560900U CN 202394963 U CN202394963 U CN 202394963U
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- circuit layer
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- adhesive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
The utility model discloses a multi-chip wafer-level semiconductor packaging structure, and provides a miniaturized system packaging module. The multi-chip wafer-level semiconductor packaging structure comprises a re-wiring circuit layer, at least one first chip, a first packaging rubber material, at least one second chip, a second packaging rubber material and a plurality of externally connected protruding blocks, wherein a first surface of the re-wiring circuit layer is provided with a plurality of first connection gaskets; a second surface of the re-wiring circuit layer is provided with a plurality of second connection gaskets; the at least one first chip is positioned on the first surface of the re-wiring circuit layer; the first packaging rubber material is positioned on the first surface of the re-wiring circuit layer, and covers the first chip; the at least one second chip is positioned on the second surface of the re-wiring circuit layer; the second packaging rubber material is positioned on the second surface of the re-wiring circuit layer, covers the second chip, and is provided with a plurality of openings; and the plurality of externally connected protruding blocks are respectively positioned in the openings, and are electrically connected to the second connection gaskets of the re-wiring circuit layer.
Description
Technical field
The utility model relates to a kind of multicore wafer level semiconductor packaging structure, particularly relevant for a kind of wafer level semiconductor packaging structure that the micro mation system package module of a plurality of chips of tool can be provided.
Background technology
Now; The semiconductor packages industry is in order to satisfy the demand of various high-density packages; Develop the packaging structure that various different types gradually, and wherein various system in package (system in package, SIP) design concept is usually used in framework high-density packages structure; The said system encapsulation can be further divided into multi-chip module (multi chip module again; MCM), stacked package body on the packaging body (package on package, stacked package body POP) and in the packaging body (package in package, PIP) etc.In addition; The design concept that produces in order to dwindle the packaging structure volume is also arranged; Wafer-grade packaging structure (wafer level package for example; WLP), chip size packages structure (chip scale package, CSP) and encapsulation constitution without external pin (quad-flat no-lead package, QFN) etc.
For instance; Please with reference to shown in Figure 1; It discloses a kind of by stacked package body (POP) structure on the packaging body of existing wafer-grade packaging structure (WLP) formation; It comprises one first wafer-grade packaging structure 100 and one second wafer-grade packaging structure 200, wherein said first wafer-grade packaging structure 100 comprise one first chip 11, one first packaging adhesive material 12, one first reroute layer (re-distributed layer, RDL) 13, several first projections 14 and several wear glue via (through molding via; TMV) 15; The said glue via 15 of wearing runs through said first packaging adhesive material 12, and its bottom electrically connects said first projection 14 through said first layer 13 that reroutes, and the top electrically connects several switching pads 16 of said first packaging adhesive material, 12 upper surfaces; Simultaneously, said second wafer-grade packaging structure 200 comprises one second chip 21, one second packaging adhesive material 22, one second reroute layer 23 and several second projections 24.When assembling, said second wafer-grade packaging structure 200 is stacked on said first packaging adhesive material 12 of said first wafer-grade packaging structure 100, and said second projection 24 electrically connects said switching pad 16.Therefore; Said second chip 21 can through said second reroute layer 23, second projection 24, switching pad 16, wear glue via 15, first layer 13 and first projection 14 that reroute and form the electrical connection path of an I/O, with the power supply that transmits said second wafer-grade packaging structure 200, signal or as the ground connection purposes.
Yet; The problem of stacked package body structure is on the packaging body that above-mentioned existing wafer-grade packaging structure constitutes: become a kind of micro mation system encapsulation (SIP) structure though can two or above wafer-grade packaging structure 100,200 be stacked; But because said first wafer-grade packaging structure 100 must be provided with glue via 15 connects said second wafer-grade packaging structure 200 for correspondence second projection 24 of wearing of sufficient amount in said first packaging adhesive material 12; Therefore said first packaging adhesive material 12 must possess enough volumes; This causes the whole volume of said first wafer-grade packaging structure 100 further to be dwindled, and is unfavorable for the microminiaturization of system packaging construct.Otherwise; If will control only tool one limited bulk of said first packaging adhesive material 12; Then said first packaging adhesive material 12 can't be provided with the too many glue via 15 of wearing; So second projection, 24 quantity of said second wafer-grade packaging structure 200 will be restricted, and then influence the chip computing capability that system packaging construct can provide.Moreover, being subject to the said technical merit of wearing glue via 15 of present making, the yield of its making is also still low relatively.As a result, encapsulation industry at present is difficult in limited encapsulated space, further design the micro mation system package design that has higher circuit layout density than the POP framework of existing wafer-grade packaging structure.
So, be necessary to provide a kind of multicore wafer level semiconductor packaging structure, to solve the existing in prior technology problem.
The utility model content
In view of this, the utility model provides a kind of multicore wafer level semiconductor packaging structure, to solve the existing technical problem that can't take into account high circuit layout density and pile up volume microminiaturization of existing wafer-level packaging technology.
The main purpose of the utility model is to provide a kind of multicore wafer level semiconductor packaging structure; It is to be to make the circuit layer that reroutes earlier during manufacture; Combine at least one chip respectively in the both sides of the circuit layer that reroutes again; And after sealing, external projection is set as input/output terminal in circuit layer one side that reroutes, and plate heat radiating metallic layer at the outer surface of packaging adhesive material, so can under the situation of not using the POP framework, accomplish modularization encapsulation for the first time; And direct wafer-level packaging of construction (wafer level package; WLP) therefore the micro mation system package module of grade helps increasing the circuit layout density of single packaging structure itself, the radiating efficiency of lifting packaging structure, and and then makes the volume energy of wafer-grade packaging structure realize compactization smoothly.
The secondary objective of the utility model is to provide a kind of multicore wafer level semiconductor packaging structure; It is to utilize above-mentioned micro mation system package module further to carry out the modularization encapsulation second time again; Just combine micro mation system package module and at least one chip respectively in the both sides of another circuit layer that reroutes; Therefore help really increasing single packaging structure itself circuit layout density, promote packaging structure radiating efficiency, improve the feasibility of piling up of stacked package body (PIP) framework in the packaging body of wafer-grade packaging structure, and and then the volume energy that makes wafer-grade packaging structure and PIP framework thereof compactization of realization smoothly.
For reaching the aforementioned purpose of the utility model, the utility model provides a kind of multicore wafer level semiconductor packaging structure, and wherein said multicore wafer level semiconductor packaging structure is a micro mation system package module, and said micro mation system package module comprises:
One circuit layer that reroutes has a first surface and a second surface, and said first surface is provided with several first connection pads, and said second surface is provided with several second connection pads;
At least one first chip is positioned on the first surface of the said circuit layer that reroutes, and is provided with several first weld pads, and said first weld pad is electrically connected on first connection pad of the said circuit layer that reroutes;
One first packaging adhesive material is positioned on the first surface of the said circuit layer that reroutes, and coats said first chip;
At least one second chip is positioned on the second surface of the said circuit layer that reroutes, and is provided with several second weld pads, and said second weld pad is electrically connected on second connection pad of the said circuit layer that reroutes;
One second packaging adhesive material is positioned on the second surface of the said circuit layer that reroutes, and coats said second chip, and has several openings; And
Several first external projections lay respectively in the said opening, and are electrically connected on second connection pad of the said circuit layer that reroutes.
In an embodiment of the utility model; Comprise several second external projections in the opening of said second packaging adhesive material in addition; The said second external projection piles up respectively and is combined on the said first external projection, and the said second external projection is partly to protrude into outside the opening of said second packaging adhesive material.
In an embodiment of the utility model, an outer surface of said first packaging adhesive material has a heat radiating metallic layer.
In an embodiment of the utility model, an outer surface of said second packaging adhesive material has a heat radiating metallic layer.
In an embodiment of the utility model, said first packaging adhesive material is photoresist (photo-resist), epoxy resin (epoxy), pressing sheet (prepreg) or laser activation material (laser activated material).
In an embodiment of the utility model, said second packaging adhesive material is photoresist, epoxy resin, pressing sheet or laser activation material.
In an embodiment of the utility model, first weld pad of said first chip is electrically connected on first connection pad of the said circuit layer that reroutes through several first projections.
In an embodiment of the utility model, said first projection can be selected from tin projection, golden projection, copper post projection (Cu pillar bumps) or nickel post projection.
In an embodiment of the utility model, second weld pad of said second chip is electrically connected on second connection pad of the said circuit layer that reroutes through several second projections.
In an embodiment of the utility model, said second projection can be selected from tin projection, golden projection, copper post projection or nickel post projection.
Moreover the utility model provides another kind of multicore wafer level semiconductor packaging structure, and wherein said multicore wafer level semiconductor packaging structure comprises:
One as stated micro mation system package module comprises: one first reroute circuit layer, at least one first chip, one first packaging adhesive material, a heat radiating metallic layer, at least one second chip, second packaging adhesive material and several first external projections;
One second circuit layer that reroutes; Have one first loading end and one second load-bearing surface; Said first loading end is provided with several first switching pads; Reach said second loading end and be provided with several second switching pads, wherein said micro mation system package module is positioned on said first loading end, and the said first external projection is electrically connected at the said first switching pad;
One the 3rd packaging adhesive material is positioned at said second and reroutes on first loading end of circuit layer, and coats said micro mation system package module;
At least one the 3rd chip is positioned at said second and reroutes on second loading end of circuit layer, and is provided with several the 3rd weld pads, and said the 3rd weld pad is electrically connected to said second and reroutes on the second switching pad of circuit layer;
One the 4th packaging adhesive material is positioned at said second and reroutes on second loading end of circuit layer, and coat said the 3rd chip, and has several switching openings; And
Several the 3rd external projections lay respectively in the said switching opening, and are electrically connected to said second and reroute on the second switching pad of circuit layer.
In an embodiment of the utility model; Comprise several in the opening of said the 4th packaging adhesive material in addition and connect projection all round; Said the connects projection all round piles up respectively and is combined on the said the 3rd external projection, and said the to connect projection all round be partly to protrude into outside the opening of said the 4th packaging adhesive material.
In an embodiment of the utility model, an outer surface of said the 3rd packaging adhesive material has a heat radiating metallic layer.
In an embodiment of the utility model, an outer surface of said the 4th packaging adhesive material has a heat radiating metallic layer.
Description of drawings
Fig. 1 is a kind of sketch map by stacked package body (POP) structure on the packaging body of existing wafer-grade packaging structure (WLP) formation.
Fig. 2 A, 2B, 2C and 2D are the schematic flow sheets of the utility model first each step of embodiment multicore wafer level semiconductor packaging structure manufacturing approach.
Fig. 2 E is the sketch map of the utility model second embodiment multicore wafer level semiconductor packaging structure.
Embodiment
For making the utility model above-mentioned purpose, characteristic and advantage more obviously understandable, hereinafter is special lifts the utility model preferred embodiment, and conjunction with figs., elaborates as follows.Moreover, the direction term that the utility model is mentioned, for example " on ", D score, " preceding ", " back ", " left side ", " right side ", " interior ", " outward ", " side " etc., only be direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the utility model, but not in order to restriction the utility model.
Please with reference to shown in Fig. 2 A to 2D; The schematic flow sheet of each step of manufacturing approach of the multicore wafer level semiconductor packaging structure of its announcement the utility model first embodiment; The utility model will utilize Fig. 2 A to 2D to specify the detailed processed process of first each step of embodiment one by one in hereinafter, and detail structure, assembled relation and the operation principles thereof of each element.
Please with reference to shown in Fig. 2 A; The manufacturing approach of the multicore wafer level semiconductor packaging structure of the utility model first embodiment at first is: prepare a provisional support plate 30, and on an adhesion coating 301 of said provisional support plate 30, make the circuit layer 31 that reroutes according to increasing layer process (build-up process); Then, pile up and with at least one first chip 32 and to be combined on the said circuit layer 31 that reroutes.In this step, said provisional support plate 30 can be metallic plate (like corrosion resistant plate or copper coin etc.), glass plate or the plastic plate etc. with enough hardness.Said adhesion coating 301 is copper seed layer (Cu seed layer) or ultraviolet light adhesive plaster (UV tape) preferably.The said circuit layer 31 that reroutes is meant by a plurality of insulating barriers and circuit layer alternated arranges the composite stack layer that forms, and the insulating barrier that wherein comprises and the number of plies of circuit layer are that the demand that accordings to product redistribution bond pad locations and spacing designs.Completing behind the said circuit layer 31 that reroutes according to increasing layer process; This moment, the said circuit layer 31 that reroutes had a first surface (being upper surface) and a second surface (being lower surface); Said first surface is exposed to have several first connection pads 311, and said second surface is exposed that several second connection pads 312 are arranged.
Moreover; Said at least one first chip 32 is positioned on the first surface of the said circuit layer 31 that reroutes; And has down a back side up, active surface and; Said active surface is provided with several first weld pads 321, and said first weld pad 321 is attached on first connection pad 311 of the said circuit layer 31 that reroutes through several first projections 322.Said first projection 322 can be selected from tin projection, golden projection, copper post projection (Cu pillar bumps) or nickel post projection, but is not limited to this.
Please with reference to shown in Fig. 2 B; The manufacturing approach of the multicore wafer level semiconductor packaging structure of the utility model first embodiment then is: make one first packaging adhesive material 33, be positioned on the first surface of the said circuit layer 31 that reroutes and coat said first chip 32 of protection; Subsequently, on an outer surface of said first packaging adhesive material 33, plate a heat radiating metallic layer 34.In this step; Said first packaging adhesive material 33 can be selected from photoresist (photo-resist), epoxy resin (epoxy), pressing sheet (prepreg) or laser activation material (laser activated material); For example said first packaging adhesive material 33 can be selected from the pressing sheet; Said pressing sheet is meant the semi-solid preparation preimpregnation material that is composited by epoxy resin and glass fiber, and it can suitable distortion after pressing is stacked on the first surface of the said circuit layer 31 that reroutes, and fills up said space of rerouting between the circuit layer 31 and first chip 32; Then heating is solidified the pressing sheet again, to form said first packaging adhesive material 33.In case of necessity, before making said first packaging adhesive material 33, also can insert underfill (underfill) in said space of rerouting between the circuit layer 31 and first chip 32 in advance.
Moreover; Said heat radiating metallic layer 34 is coating or its composite deposite of copper, silver, gold, nickel, palladium preferably, and it can be plated on the outer surface (like upper surface) of said first packaging adhesive material 33 through sputter (sputtering), vapor deposition (evaporation), plating (electroplating) or electroless plating technologies such as (electroless plating).In case of necessity; Can when making said first packaging adhesive material 33, directly expose said first chip 32 back side up; Or after making said first packaging adhesive material 33, grind again up to exposed said first chip 32 back side up; So that the back side of said first chip 32 can directly be linked together, with said heat radiating metallic layer 34 further to promote the efficient that said first chip 32 is dispelled the heat.
Please with reference to shown in Fig. 2 C; The manufacturing approach of the multicore wafer level semiconductor packaging structure of the utility model first embodiment then is: remove said provisional support plate 30 and adhesion coating 301, and on the assembly of the said circuit layer 31 of rerouting, first chip 32, first packaging adhesive material 33 and heat radiating metallic layer 34 second connection pad 312 below, combine at least one second chip 35 and several first external projections 36.In this step; When said adhesion coating 301 is copper seed layer; At first divest said provisional support plate 30 with external force, then said adhesion coating 301 is removed in etching again, and second connection pad 312 of the second surface that subsequently the said circuit layer 31 that reroutes is exposed carries out surface treatment; Plated with nickel/gold layer or nickel/palladium/gold layer for example is for use in said at least one second chip 35 of combination and several first external projections 36.Said second chip 35 is positioned on the second surface (being lower surface) of the said circuit layer 31 that reroutes; And being provided with several second weld pads 351, said second weld pad 351 is electrically connected on second connection pad 312 of the said circuit layer 31 that reroutes through several second projections 352.Said second projection 352 can be selected from tin projection, golden projection, copper post projection or nickel post projection, but is not limited to this.
Moreover, the said first external projection 36 can be equidistantly or not equidistance arrangement and be combined on other second connection pads 312 of periphery of said second chip 35.The height of the said first external projection 36 can greater than, be equal to or less than the total height on the second surface that said second chip 35, second weld pad 351 and second projection 352 be combined in the said circuit layer 31 that reroutes.The said first external projection 36 also can be selected from tin projection, golden projection, copper post projection or nickel post projection, but is not limited to this.
In addition; In another execution mode of this step; Said provisional support plate 30 can be selected from glass plate and said adhesion coating 301 can be selected from the ultraviolet light adhesive plaster; Can make it lose stickiness this moment through the said adhesion coating 301 of UV-irradiation; And the assembly of the said circuit layer 31 of rerouting, first chip 32, first packaging adhesive material 33 and heat radiating metallic layer 34 is separated from each other with said provisional support plate 30 and adhesion coating 301 smoothly, and then can carry out the surface treatment of said second connection pad 312 equally, and combine said second chip 35 and the first external projection 36.
Please with reference to shown in Fig. 2 D; The manufacturing approach of the multicore wafer level semiconductor packaging structure of the utility model first embodiment then is: make one second packaging adhesive material 37, be positioned on the second surface of the said circuit layer 31 that reroutes and coat said second chip 35 of protection at least; Subsequently, on each said first external projection 36, pile up combination one second external projection 38.In this step; Said second packaging adhesive material 37 can be selected from photoresist, epoxy resin, pressing sheet or laser activation material; For example said second packaging adhesive material 37 can be selected from the pressing sheet; Said pressing sheet is meant the semi-solid preparation preimpregnation material that is composited by epoxy resin and glass fiber, and it can suitable distortion after pressing is stacked on the second surface of the said circuit layer 31 that reroutes, and fills up said space of rerouting between the circuit layer 31 and second chip 35; Then heating is solidified the pressing sheet again, to form said second packaging adhesive material 37.In case of necessity, before making said second packaging adhesive material 37, also can insert underfill in said space of rerouting between the circuit layer 31 and second chip 35 in advance.
Moreover; After making said second packaging adhesive material 37; Said second packaging adhesive material 37 coats said second chip 35 and the first external projection 36, and can further carry out perforate to said second packaging adhesive material 37 this moment, to form the exposed respectively said first external projection 36 of several openings 371.Perhaps; If said second packaging adhesive material 37 is to be selected from the epoxy resin base material that is doped with solid filling; And be the words of utilizing transfer casting (transfer molding) technology to make; Then also can be through the die cavity shape of its mould of design, and make it when said second packaging adhesive material 37 of molded formation, directly form said opening 371.The purpose of said opening 371 is: on each said first external projection 36, further pile up combination one second external projection 38; The total height of said first and second external projection 38 is the thickness greater than said second packaging adhesive material 37, thereby the said second external projection 38 can partly protrude into outside the opening of said second packaging adhesive material 37.The said second external projection 38 can be selected from tin projection, golden projection, copper post projection or nickel post projection, but is not limited to this.
In addition, also can optionally plate a heat radiating metallic layer (not illustrating) on the outer surface (like lower surface) of said second packaging adhesive material 37.Said heat radiating metallic layer preferably also is coating or its composite deposite of copper, silver, gold, nickel, palladium, and it can be plated on the outer surface of said second packaging adhesive material 37 through technologies such as sputter, vapor deposition, plating or electroless platings equally.In case of necessity; Also can when making said second packaging adhesive material 37, directly expose said second chip 35 back side down; Or after making said second packaging adhesive material 37, grind again up to exposed said second chip 35 back side down; So that the back side of said second chip 35 can directly be linked together with said heat radiating metallic layer, further to promote the efficient that said second chip 35 is dispelled the heat.
Last in this step; Can cut the above-mentioned circuit layer 31 of rerouting, first packaging adhesive material 33, heat radiating metallic layer 34 and second packaging adhesive material 37; To separate into several micro mation system package modules (miniaturized SIP module) 300, wherein each said micro mation system package module 300 roughly comprises: reroute circuit layer 31, at least one first chip 32, one first packaging adhesive material 33, a heat radiating metallic layer 34, at least one second chip 35, second packaging adhesive material 37, several first external projections 36 and several second external projections 38.The said circuit layer 31 that reroutes has a first surface (being upper surface) and a second surface (being lower surface), and said first surface is provided with several first connection pads 311, and said second surface is provided with several second connection pads 312.Said at least one first chip 32 is positioned on the first surface of the said circuit layer 31 that reroutes, and is provided with several first weld pads 321, and said first weld pad 321 is electrically connected on first connection pad 311 of the said circuit layer 31 that reroutes.Said first packaging adhesive material 33 is positioned on the first surface of the said circuit layer 31 that reroutes, and coats said first chip 32.Said heat radiating metallic layer 34 is coated on the outer surface (like upper surface) of said first packaging adhesive material 33.
Moreover said at least one second chip 35 is positioned on the second surface of the said circuit layer 31 that reroutes, and is provided with several second weld pads 351, and said second weld pad 351 is electrically connected on second connection pad 312 of the said circuit layer 31 that reroutes.Said second packaging adhesive material 37 is positioned on the second surface of the said circuit layer 31 that reroutes, and coats said second chip 35, and has several openings 371.Several first external projections 36 lay respectively in the said opening 371, and are electrically connected on other second connection pads 312 of the said circuit layer 31 that reroutes.The said second external projection 38 piles up respectively and is combined on the said first external projection 36; And the said second external projection 38 is partly to protrude into outside the opening 371 of said second packaging adhesive material 37; With as input/output terminal, with transmission power supply, signal or as the ground connection purposes.
Please with reference to shown in Fig. 2 E; The multicore wafer level semiconductor packaging structure of the utility model second embodiment is similar in appearance to the utility model first embodiment; And roughly continue to use similar elements title and figure number; But the difference characteristic of second embodiment is: the multicore wafer level semiconductor packaging structure 400 of said second embodiment is to use the micro mation system package module 300 of above-mentioned first embodiment further to carry out the flow process of modularization encapsulation for the second time again; The step of the said modularization encapsulation second time is similar in appearance to Fig. 2 A to 2D; It only is to replace first chip 32 among Fig. 2 A to 2D with said micro mation system package module 300, and replaces second chip 35 among Fig. 2 A to 2D with at least one the 3rd chip 44 in addition, and remaining step process principle is similar basically.After the flow process of accomplishing modularization encapsulation for the second time, the multicore wafer level semiconductor packaging structure 400 of said second embodiment comprises: a micro mation system package module 300, one second circuit layer 41, one the 3rd packaging adhesive material 42, a heat radiating metallic layer 43, at least one the 3rd chip 44, one the 4th packaging adhesive material 46, several the 3rd external projections 45 and several that reroute connect projection 47 all round.
In a second embodiment; Said micro mation system package module 300 comprises each assembly structure of aforesaid first embodiment, i.e. one (the first) reroute circuit layer 31, at least one first chip 32, one first packaging adhesive material 33, a heat radiating metallic layer 34, at least one second chip 35, second packaging adhesive material 37, several first external projections 36 and several second external projections 38.Said second circuit layer 41 that reroutes has one first loading end (being upper surface) and one second load-bearing surface (being lower surface); Said first loading end is provided with several first switching pads 411; And said second loading end is provided with several second switching pads 412; Wherein said micro mation system package module 300 is positioned on said first loading end, and said first and second external projection 36,38 is electrically connected at the said first switching pad 411.Said the 3rd packaging adhesive material 42 is positioned at said second and reroutes on first loading end of circuit layer 41, and coats said micro mation system package module 300.Said heat radiating metallic layer 43 is coated on the outer surface (like upper surface) of said the 3rd packaging adhesive material 42.
Moreover; Said at least one the 3rd chip 44 is positioned at said second and reroutes on second loading end of circuit layer 41; And being provided with several the 3rd weld pads 441, said the 3rd weld pad 441 is electrically connected to said second through several the 3rd projections 442 and reroutes on the second switching pad 412 of circuit layer 41.Said the 4th packaging adhesive material 46 is positioned at said second and reroutes on second loading end of circuit layer 41, and coats said the 3rd chip 44, and has several switching openings 461.Said several the 3rd external projections 45 lay respectively in the said switching opening 461, and are electrically connected to said second and reroute on other second switching pads 412 of circuit layer 41.Said the 4th projection 38 piles up respectively and is combined on the said the 3rd external projection 45; And the said second external projection 38 is partly to protrude into outside the opening 461 of said the 4th packaging adhesive material 46; With as input/output terminal, with transmission power supply, signal or as the ground connection purposes.
In case of necessity, before making said the 3rd packaging adhesive material 42, also can be in advance insert underfill in said second space of rerouting between circuit layer 41 and the said micro mation system package module 300.Before making said the 4th packaging adhesive material 46, also can be in advance insert underfill in said second space of rerouting between circuit layer 41 and the 3rd chip 44.In addition, also can optionally plate a heat radiating metallic layer (not illustrating) on the outer surface (like lower surface) of said the 4th packaging adhesive material 46.In case of necessity; Also can when making said the 3rd (or 4th) packaging adhesive material 42 (or 46), directly expose said micro mation system package module 300 heat radiating metallic layer 34 (or said the 3rd chip 44 back side down) up; Or after making said the 3rd (or 4th) packaging adhesive material 42 (or 46), grind again up to exposed said micro mation system package module 300 heat radiating metallic layer 34 (or said the 3rd chip 44 back side down) up; So that the heat radiating metallic layer 34 (or back side of said the 3rd chip 44) of said micro mation system package module 300 can directly be linked together with outer heat radiating metallic layer 43 or said the 4th packaging adhesive material 46 outer heat radiating metallic layers (not illustrating) of said the 3rd packaging adhesive material 42, further to promote the efficient that said micro mation system package module 300 or the 3rd chip 44 are dispelled the heat.
As stated; Compared to the existing technical problem that can't take into account high circuit layout density and pile up volume microminiaturization of existing wafer-level packaging technology; The utility model of Fig. 2 A to 2D is to be to make the said circuit layer 31 that reroutes earlier during manufacture; Combine said at least one first chip 32 and said at least one second chip 35 more respectively in the both sides of the said circuit layer 31 that reroutes; And after sealing, said first and second external projection 36,38 is set as input/output terminal in said circuit layer 31 1 sides (like downside) that reroute; And the outer surface that can be chosen in said first and second packaging adhesive material 33,37 plates heat radiating metallic layer 34; So can under the situation of not using the POP framework, directly accomplish modularization encapsulation for the first time, and direct wafer-level packaging of construction (wafer level package, WLP) the micro mation system package module 300 of grade; Therefore help increasing the circuit layout density of single packaging structure itself, the radiating efficiency of lifting packaging structure, and and then make the volume energy of wafer-grade packaging structure realize compactization smoothly.
Moreover; The utility model of Fig. 2 E utilizes above-mentioned micro mation system package module 300 further to carry out modularization encapsulation second time flow process more especially; Just combine micro mation system package module 300 and at least one the 3rd chip 44 respectively in the both sides of another circuit layer 41 that reroutes; Therefore help really increasing single packaging structure itself circuit layout density, promote packaging structure radiating efficiency, improve the feasibility of piling up of stacked package body (PIP) framework in the packaging body of wafer-grade packaging structure, and and then the volume energy that makes wafer-grade packaging structure and PIP framework thereof compactization of realization smoothly.
The utility model is described by above-mentioned related embodiment, yet the foregoing description is merely the example of implementing the utility model.Must be pointed out that disclosed embodiment does not limit the scope of the utility model.On the contrary, being contained in the spirit of claims and the modification and impartial setting of scope includes in the scope of the utility model.
Claims (10)
1. multicore wafer level semiconductor packaging structure, it is characterized in that: said multicore wafer level semiconductor packaging structure is a micro mation system package module, and said micro mation system package module comprises:
One circuit layer that reroutes has a first surface and a second surface, and said first surface is provided with several first connection pads, and said second surface is provided with several second connection pads;
At least one first chip is positioned on the first surface of the said circuit layer that reroutes, and is provided with several first weld pads, and said first weld pad is electrically connected on first connection pad of the said circuit layer that reroutes;
One first packaging adhesive material is positioned on the first surface of the said circuit layer that reroutes, and coats said first chip;
At least one second chip is positioned on the second surface of the said circuit layer that reroutes, and is provided with several second weld pads, and said second weld pad is electrically connected on second connection pad of the said circuit layer that reroutes;
One second packaging adhesive material is positioned on the second surface of the said circuit layer that reroutes, and coats said second chip, and has several openings; And
Several first external projections lay respectively in the said opening, and are electrically connected on second connection pad of the said circuit layer that reroutes.
2. multicore wafer level semiconductor packaging structure as claimed in claim 1 is characterized in that: comprise several second external projections in the opening of said second packaging adhesive material in addition, the said second external projection piles up respectively and is combined on the said first external projection.
3. multicore wafer level semiconductor packaging structure as claimed in claim 2 is characterized in that: the said second external projection is partly to protrude into outside the opening of said second packaging adhesive material.
4. multicore wafer level semiconductor packaging structure as claimed in claim 1, it is characterized in that: an outer surface of said first packaging adhesive material has a heat radiating metallic layer.
5. multicore wafer level semiconductor packaging structure as claimed in claim 1, it is characterized in that: an outer surface of said second packaging adhesive material has a heat radiating metallic layer.
6. multicore wafer level semiconductor packaging structure as claimed in claim 1 is characterized in that: first weld pad of said first chip is electrically connected on first connection pad of the said circuit layer that reroutes through several first projections; And second weld pad of said second chip is electrically connected on second connection pad of the said circuit layer that reroutes through several second projections.
7. multicore wafer level semiconductor packaging structure, it is characterized in that: said multicore wafer level semiconductor packaging structure comprises:
One micro mation system package module as claimed in claim 1 comprises one first reroute circuit layer, at least one first chip, one first packaging adhesive material, a heat radiating metallic layer, at least one second chip, second packaging adhesive material and several first external projections;
One second circuit layer that reroutes; Have one first loading end and one second load-bearing surface; Said first loading end is provided with several first switching pads; Reach said second loading end and be provided with several second switching pads, wherein said micro mation system package module is positioned on said first loading end, and the said first external projection is electrically connected at the said first switching pad;
One the 3rd packaging adhesive material is positioned at said second and reroutes on first loading end of circuit layer, and coats said micro mation system package module;
At least one the 3rd chip is positioned at said second and reroutes on second loading end of circuit layer, and is provided with several the 3rd weld pads, and said the 3rd weld pad is electrically connected to said second and reroutes on the second switching pad of circuit layer;
One the 4th packaging adhesive material is positioned at said second and reroutes on second loading end of circuit layer, and coat said the 3rd chip, and has several switching openings; And
Several the 3rd external projections lay respectively in the said switching opening, and are electrically connected to said second and reroute on the second switching pad of circuit layer.
8. multicore wafer level semiconductor packaging structure as claimed in claim 7; It is characterized in that: comprise several in the opening of said the 4th packaging adhesive material in addition and connect projection all round; Said the connects projection all round piles up respectively and is combined on the said the 3rd external projection, and said the to connect projection all round be partly to protrude into outside the opening of said the 4th packaging adhesive material.
9. multicore wafer level semiconductor packaging structure as claimed in claim 7, it is characterized in that: an outer surface of said the 3rd packaging adhesive material has a heat radiating metallic layer.
10. multicore wafer level semiconductor packaging structure as claimed in claim 7, it is characterized in that: an outer surface of said the 4th packaging adhesive material has a heat radiating metallic layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205609003U CN202394963U (en) | 2011-12-28 | 2011-12-28 | Multi-chip wafer-level semiconductor packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205609003U CN202394963U (en) | 2011-12-28 | 2011-12-28 | Multi-chip wafer-level semiconductor packaging structure |
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| Publication Number | Publication Date |
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| CN202394963U true CN202394963U (en) | 2012-08-22 |
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| CN2011205609003U Expired - Lifetime CN202394963U (en) | 2011-12-28 | 2011-12-28 | Multi-chip wafer-level semiconductor packaging structure |
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