TWI275150B - Embedded chip package structure - Google Patents

Embedded chip package structure Download PDF

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Publication number
TWI275150B
TWI275150B TW094115339A TW94115339A TWI275150B TW I275150 B TWI275150 B TW I275150B TW 094115339 A TW094115339 A TW 094115339A TW 94115339 A TW94115339 A TW 94115339A TW I275150 B TWI275150 B TW I275150B
Authority
TW
Taiwan
Prior art keywords
wafer
layer
semiconductor
embedded
carrier plate
Prior art date
Application number
TW094115339A
Other languages
Chinese (zh)
Other versions
TW200639955A (en
Inventor
Shih-Ping Hsu
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW094115339A priority Critical patent/TWI275150B/en
Publication of TW200639955A publication Critical patent/TW200639955A/en
Application granted granted Critical
Publication of TWI275150B publication Critical patent/TWI275150B/en
Priority to US11/798,139 priority patent/US7973398B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An embedded chip package structure is proposed. The embedded chip package structure includes a supporting board with at least one of the protruding section, a semiconductor chip formed on the protruding section of the supporting board, a resist layer formed on the supporting board and the semiconductor chip, and a circuit layer formed on the resist layer. The circuit layer is electrically connected to the electrode pads of semiconductor chip via a plurality of conducting structures, and thus the semiconductor chip can electrically extend outside. By varying the thickness of the protruding section, the resist layer and the supporting board, the warp of the package structure because of temperature change is controlled during the fabricated process.

Description

1275150 九、發明說明： 【發明所屬之技術領域】 ^:係㈣於—種晶片嵌埋式料結構，尤指一種 並使其直接向外作電性延伸之封裝結構。 L先珂技術】 隨著半導體封裝技術的演進，半導體裝置 丰導:ndUCtQr心心）已開發出不同的封裝型態，傳統 ί I Γ 要係在—㈣基板（PaGkage s—trate)或 ^木上先裝置—例如積體電路之半導體元件，再將半導 體：：電性連接在該封裝基板或導線架上，接著以膠體進 I 、:其中球柵陣列式(BaU grid阶町，BGA)為一種 導體封裝技術，其特點在於採用—縣基板來安 導體70件，並利用自動對位（Self-alignment)技術以 於遠封裝基板背面植置多數個成栅狀陣列排列之錫球 (S^der ball)，使相同單位面積之半導體元件承載件上可 以=納更多輸入/輸出連接端（I/O connection)以符合高 度集積化（Integration)之半導體晶片所需，以藉由此些1 錫 球將整個封裝單元焊結並電性連接至外部裝置。 惟傳統半導體封裝結構是將半導體元件一個接一個的 黏貼於基板頂面，進行打線接合（wire bonding)或覆晶接 合（Flip chip)封裝，再於基板之背面植以錫球以進行電性 連接，如此，雖可達到高腳數的目的，但由於半導體元件 之面積及體積限制使得基板表面佈線難度增加，以及由於 玄二半‘ m元件係全部分佈於基板表面，因而不利於半導 18475 5 1275150 -體元件封裝結構尺寸之縮小及性能的提高。 ,、此外’-般半導體元件之製程，首先係由晶 製造業者生產適用於該半導體元件 ;導線架，之後，再將該些晶體::: 者進订置晶、模壓、以及植球等製程，最後，方可完成客 ‘ 2端所需之電子功能之半導體元件。其間涉 •者（即包含有晶片承載件製造業者與半導體封裂苹旬= 馨此於貫際製造過程中不僅步驟須項且界面整合不易，況 2，若客戶端欲進行變更功能設計時，其牽 敕入 層面更是複雜，亦不符合需求變更彈性與經濟效/。、正5 :者，隨著電子產業的蓬勃發展，電子產品 高性能的研發方向。為滿足半導體 广求丰ν㈣片於運作時所產生之熱量將_ 加，如不及時將半導體晶片產生之熱量有效逸散& ⑩縮短半導體晶片之性能及壽命。 、厭重 • /此，遂有業界提出將半導體元件埋人基板之作法。 ‘ 圖所I ’係為習知的半導體元件埋入基板之封裝* t之剖面示意圖。如圖所示，該封裳結構係包括-散i: 2’且讀熱板12中形成有一開口 12〇; 一半導俨 係接置於該散熱板12上並收納於該散熱板開;日且 該半導體晶片上係具有多數電極墊咖絕緣層14係妒成 ::1亥„12及該半導體晶片13上；以及線路層…係 巴緣層14上’且該線路層15得以透過形成於該 18475 1275150 * 絕緣層1 4中之墓带亡？丨1 C： λ τ* a ¥兒目孔15 0而電性連接至該半導體晶片 ， 13之電極墊130。 該晶片埋入基板之封裝結構雖可解決上述習知技術之 缺失，然而，由於散熱板12、絕緣層14之熱膨脹係數 (Coefflclent of The〇]al Εχρ_〇η，αΕ)差異大，此 -種基板結構於製程中之溫度變化下（如基板烘烤 • (Baki^)、後續熱循環（Thermal Cycle)作業等環境下，各 參組成部件上分別產生不同之熱應力（Thermaistress))， ㈣生_(WaFp㈣現象’嚴重者可能造成結構 a曰產生脫層，甚或擠壓至半導體晶片’造成晶片破裂。 惟增加散熱板厚度以平衡溫度變化時基板所受的熱應力 (Thermal Stress)方能有效改善基板麵曲現象，但增設散 熱板厚度會明顯增加封裝結構成品的體積與厚度會導 致製程成本之增加。 ，外’上述之封裝結構中所埋人的半導體晶片大多數 形式且尺寸相同，尚未形成多功能之模組架構，而 I付現今電子產品發展趨勢。此外若於該封I結構中埋入 m尺寸不同之半導體元件以達成多功能之模組架 :之=於所埋入的該些元件之尺寸不同，使得該些元 件之琶性連接表面不處於同一平面，導致埋訝 之封裝基板表面之絕緣層表面不平整 ^一 ’、 層上進行後續細線路製程之製造甚而^於該絕緣 α此如何提出—種晶片嵌埋式封裝結構，以 知半導體封裝結構製程令結構發生趣曲、封ι结搆厚度、 18475 1275150 重里及成本i曰加、製私表面不平整、線路製程 升、界面整合不易、無法有 界亟待攻克之難題。有效月丈…寻問遣貫以成爲目前業 [發明内容] 本發明之主要目的即在於 藉以避免於半導體裝置熱 鑒於上述習知技術之缺失 提供一種晶片嵌埋式封裝結構 製程中造成結構翹曲現象。 本，另一目的即在於提供一種晶片嵌埋式封裝社 減小半導體裝置厚度、重量及製程成本。… 树明之再一目的即在於提供一種晶片 構，猎以維持嵌埋其中 了表、··口 致性，淮而担4: 動面之平整性與- 進而鍉升後績細線路製程之製程能力。 处爐本f明之又再一目的即在於提供—種晶片嵌埋式封裝 :。，可整合複數半導體晶片’提升電子裝置之電性‘ 本發^之又再一目的即在於提供—種晶片嵌埋式封裝 、。以有效逸散半導體晶片運作過程中產生的熱量。 為達上述及其他目的，本一 封裝結構，俘句括·曰 種日日片耿埋式 繁u l括·—具至少—凸料之承載板；至少_ 曰 妾置於忒承载板之凸起部上，且該半 板::第墊;一絕緣層，係形成於該承载 绫 ）、版日日片上，以及一線路層，係形成於該絕 、、’曰，丨該線路層得以透過形成於該絕緣層中之導^士 構而電性連接至該第—半導體晶片之電極墊，其中：：;； 18475 1275150 羞結構復可包括至少一第二導 ' 载板上凸起邻以冰Γ- ，日日片，八係接置於該承 叙 起°卩以外之區域，且該第二半導I#曰η μ目士夕 數電極墊，而# 且日日片上八有夕 結構電性連接 …亥、、·邑、味層中之導電 俨曰y 玄弟—+導體晶片之電極塾。該第二丰導 且日日片之厚度係可與 -整凸起部之厚度以使該第一不同’並可透過調 .線路層：::右Γ應實際電性設計需求，亦可於該 % 上^成有線路增層結構。 该承载板及形成於其上之凸起部材質可 5 ’且該承载板與凸起部亦係 ;^ 載板及凸起部之材質係可 / 成型之結構，該承 .之一者所製成。 旬尤及南散熱材料其中 相較於習知技術，本發明之晶 要係將半導f日 乃甘人埋式封裝結構，主 肘牛蛤肢阳月接置於承載板之凸 承裁板凸起部以調整凸起部間之絕緣声材料U精由該 材料及承载板之厚度，以 :广緣層 熱板厚度來改善製程溫度變化中增加散 狀況所引起的封裝結構厚度、重量及“：：產生的輕曲 又，本發里及裊耘成本之增加。 佶鬥严Λ ° “虞貫際設計需要調整凸起部之厚戶以 使不同厚度尺寸之半導體晶 I之各度以 導體晶片之電性連接表面維持=載板後’該等半 半導體晶片之承載板上…2一千面，以維持收納有 進而提升後續於絕緣声上千正性與-致性， 衆層上形成線路製程之可靠度。此外， 9 18475 1275150 於本發明中’該承載板中可收納多數处 。亦Γ分相同）、尺寸不同(或部分 Β曰片，進而可形成整合有多晶片之模 ^之+V體 合現今電子產品多功能需求。 衣、，構，以符 再者，於本發明之晶片嵌埋 路層上’復可進行線路增層製程，二，絕緣層及線 晶片之承载板上形成高密度及細㈣里有半導體 時可在線路結構外表面植設複數導電元件^路結構，同 權中之半導體晶片得以直接電::至^ 此，本發明亦可整合半導體晶月及卜^置，因 裝過程，提供客戶端較 S 7載件之製造與封 程與介面協調問題。 ㈣以及簡化半導體業者製 ’置於其上之半導體晶…時 散至外界’延長半導體晶 封逸 【實施方式】 7卩㈣裝結構之可靠性。 熟悉Llf由特定的具體實施例說明本發明之實施方式， 本發明之：t人士可由本έ兄明書所揭示之内容輕易地瞭解 〜：他優點及功效。本發明亦可藉由其他不同的具 :Γ 同：行或應用，本說明書中的各項細節亦可基 ㈣m。 在不^本發明之精神下進行各種 18475 10 1275150 上具有本 及説明，本垂㈣^ 肢晶片之凸起部，為簡化圖示 為例進僅以承裁板上具有二個凸起部 上&子兄月，但亚非用之限制本發明。 裝心::::二::詳細説明本發明之晶片嵌埋式封 構紅土 示意圖。如圖所示，該封裝处 = =::一，該承載板2〇上形成有凸㈣ ，半導體晶片21a、21b，係分別接置於該承 Γ 2之0 ^部2〇1、2〇2上’一絕緣層22，係形成於該承載 板20及该些半導體晶片…、⑽上；以及—線路層μ 係形成於該絕緣層22上，且令該線路層23電性連^至該 半導體晶片21a、21b。 另外，5玄封裝結構2復可包括有至少一半導體晶片 21 c’係接置於該承載板20上凸起部2〇1、2〇2以外""之33區域， 且該線路層23復可電性連接至該半導體晶片2]k。 一 該承載板20之材質可與該凸起部2〇1、2〇2之材質相 同或不同，係可由金屬、陶瓷及高散熱材料其中之一者所 製成。上述该半導體晶片21 a、21 b係接置於該凸起部2 〇 1、 202上，而該半導體晶片21c係直接接置於該承載板2〇上。 另外’该承載板2 0與凸起部2 01、2 0 2亦可為例如金 屬、陶瓷或高散熱材料之一體成型之結構。 該半導體晶片21 a、21 b係形成有一具多數電極墊 210a、210b之主動面211a、211b，及與該主動面相對之非 主動面212 a、212b’且該半導體晶片21a、21b係以其非 18475 11 1275150 主動面21 2a、212b透過一黏著層（未圖示）接置於該凸起 部20卜2()2上；半導體晶片2lG，係直接接置於該承載板 20上，遠半‘體晶片21c係形成有一具多數電極塾2i〇c 之主動面211c及與該主動面相對之非主動面212c，且該 半導體晶片21c係以其非主動面212c透過一黏著層（未圖 示）而直接接置於該承載板20上。上述該些半導體晶片 21a、21b、21c係可為主動式或被動式晶片之任意組合。 另该些半導體晶片21a、21b、21c之厚度係可不同；且形 成於该承載板上之凸起部201、202高度係可因應該些半導 脰日日片21a、21b、21c之不同厚度而加變化，以使該些半 導體晶片21a、21b、21c之主動面211a、211b、211c得以 維持在同一平面，俾利於在該晶片上進行後續電性延伸之 細線路製程。 该絕緣層22，係形成於該承載板2〇及該些半導體晶 片21a、21b、21c上，且令該絕緣層22完全填充於相鄰凸 起邛間之間隙中。該絕緣層22係可例如有機薄膜介電材或 液態有機樹脂材料；上述材質係可選自ABF(Ajin〇m〇t〇1275150 IX. Description of the invention: [Technical field to which the invention pertains] ^: (4) In-wafer embedded material structure, especially a package structure which is electrically extended directly outward. L-first technology] With the evolution of semiconductor packaging technology, semiconductor devices: ndUCtQr heart) have developed different package types, the traditional ί I Γ on the (four) substrate (PaGkage s-trate) or ^ wood First, a semiconductor device such as an integrated circuit, and then electrically connected to the package substrate or the lead frame, and then a colloid into the I, wherein: a ball grid array type (BaU grid order, BGA) is a kind The conductor encapsulation technology is characterized in that 70 pieces of conductors are used in the county substrate, and a plurality of solder balls arranged in a grid array are mounted on the back surface of the far package substrate by using a self-alignment technique (S^der). Ball), so that more I/O connections can be made on the semiconductor component carrier of the same unit area to meet the requirements of a highly integrated semiconductor wafer, thereby using 1 tin The ball welds and electrically connects the entire package unit to an external device. However, the conventional semiconductor package structure is to adhere the semiconductor components one by one to the top surface of the substrate, and to perform wire bonding or Flip chip packaging, and then solder balls on the back surface of the substrate for electrical connection. Therefore, although the purpose of the high number of pins can be achieved, the difficulty of the surface wiring of the substrate is increased due to the limitation of the area and volume of the semiconductor element, and the semi-conducting 18475 5 is disadvantageous because the two semi-m component lines are all distributed on the surface of the substrate. 1275150 - Reduction in size and performance of body component package structures. In addition, the process of 'general semiconductor components' is firstly produced by the crystal manufacturer for the semiconductor component; the lead frame, and then the crystals are::: the crystal is set, molded, and the ball is processed. Finally, the semiconductor components required for the electronic functions required at the '2' end can be completed. In the meantime, it involves the manufacturer of the wafer carrier and the semiconductor chipping. In this way, not only the steps and interface integration are difficult, but also if the client wants to change the function design. The level of involvement is more complicated, and it does not meet the elasticity of change in demand and economic efficiency. Positive 5: With the vigorous development of the electronics industry, the research and development direction of high-performance electronic products. To satisfy the semiconductor wide-ranging (four) film The heat generated during operation will be _, if the heat generated by the semiconductor wafer is not effectively dissipated & 10, the performance and life of the semiconductor wafer are shortened. The method of the substrate is shown in the schematic view of the package of the conventional semiconductor device embedded in the substrate. As shown in the figure, the package structure includes - scatter i: 2' and is read in the hot plate 12 An opening 12〇 is formed; a semi-conductor is attached to the heat dissipating plate 12 and is received in the heat dissipating plate; and the semiconductor wafer has a plurality of electrode pad insulation layers 14 on the semiconductor wafer: 1:1 And the half On the body wafer 13; and the circuit layer is on the edge layer 14' and the circuit layer 15 is transparent to the tomb that is formed in the 18475 1275150* insulating layer 14? 丨1 C: λ τ* a The hole 150 is electrically connected to the electrode pad 130 of the semiconductor wafer, 13. The package structure of the chip embedded in the substrate can solve the above-mentioned lack of the prior art, however, due to the thermal expansion coefficient of the heat dissipation plate 12 and the insulating layer 14 ( Coefflclent of The〇]al Εχρ_〇η, αΕ) has a large difference, and the substrate structure is under the temperature change in the process (such as substrate baking • (Baki^), subsequent thermal cycle (Thermal Cycle) operation, etc. Different thermal stresses (Thermaistress) are generated on each of the components of the ginseng. (4) The wa wa (WaFp (four) phenomenon may cause delamination of the structure a ,, or even extrusion to the semiconductor wafer', causing the wafer to rupture. The thickness of the substrate can effectively improve the surface curvature of the substrate by adjusting the thermal stress of the substrate when the temperature is changed. However, the thickness of the heat sink can significantly increase the volume and thickness of the finished package, which will lead to process cost. In addition, the semiconductor chips buried in the above package structure are mostly in the form and the same size, and have not yet formed a multi-functional module structure, and I pay attention to the current development trend of electronic products. In addition, if buried in the I structure Into the m-different semiconductor components to achieve a multi-functional module frame: the size of the components embedded in the different components, so that the elastic connection surfaces of the components are not in the same plane, resulting in a buried package substrate The surface of the insulating layer on the surface is not flat, the subsequent thin-line process is performed on the layer, and the insulating layer is thus proposed. The wafer-embedded package structure is known to have a structure in the semiconductor package structure. The thickness of the sealing structure, 18475 1275150 and the cost, the irregular surface of the system, the rise of the line process, the difficulty of interface integration, and the inability to overcome the problem. OBJECT OF THE INVENTION The present invention aims to avoid structural warpage caused by a wafer embedded package structure process in view of the above-mentioned conventional techniques. phenomenon. Another object of the present invention is to provide a wafer embedded package company which reduces the thickness, weight and process cost of the semiconductor device. ... Another purpose of Shuming is to provide a wafer structure, hunting to maintain the embedded table, · oral, Huai and 4: the smoothness of the moving surface and - and then the process of the fine line process ability. Another purpose of the furnace is to provide a wafer embedded package: It is possible to integrate a plurality of semiconductor wafers to enhance the electrical properties of electronic devices. A further object of the present invention is to provide a chip embedded package. To effectively dissipate the heat generated during the operation of the semiconductor wafer. In order to achieve the above and other purposes, the present package structure, the captive sentence, the 曰 曰 日 日 日 耿 · · 具 具 具 具 具 具 具 具 具 具 具 具 具 具 具 具 具 具 具 具 具 具 具 具 具 具 具 具 承载And the half board: a first pad; an insulating layer formed on the carrier 绫), a stencil, and a circuit layer formed on the singular, 曰, 丨, the circuit layer is transparent The electrode pad formed in the insulating layer is electrically connected to the electrode pad of the first semiconductor wafer, wherein: 18475 1275150 the shame structure may include at least one second guide' Hail -, the Japanese film, the eight series are placed in the area other than the 卩 起 , , and the second semi-conducting I # 曰 μ μ 目 夕 夕 夕 electrode pads, and #日日片上八夕Electrical connection of the structure...Electrical 俨曰 y in the hai, 邑 邑, 味 layer 玄 玄 — — + + + + + + + + + + + The thickness of the second and the daily film can be the same as the thickness of the entire convex portion to make the first difference and can be transmitted through the wiring layer::: the right side should be the actual electrical design requirement, or The % is formed into a line build-up structure. The carrier plate and the protrusion formed thereon may be made of material 5' and the carrier plate and the protrusion portion are also; ^ The material of the carrier plate and the protrusion portion is a structure that can be formed/formed, one of the supports production. Compared with the prior art, the crystal system of the present invention is a semi-conducting f-day gan-buried package structure, and the main elbow sirloin is placed on the convex panel of the carrier plate. The raised portion adjusts the thickness of the material and the carrier plate by adjusting the insulating sound material U between the protrusions, and improves the thickness and weight of the package structure caused by the increased dispersion condition in the process temperature change by the thickness of the wide-layer layer hot plate. ":: The resulting soft music, the cost of this hair and the increase of the 。 Λ Λ Λ ° ° "虞 虞 设计 设计 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞 虞The electrical connection surface of the conductor wafer is maintained = after the carrier board, the carrier board of the semi-semiconductor wafer ... 2 thousand faces to maintain the storage and further enhance the subsequent positive and negative properties of the insulation sound, on the layer Form the reliability of the line process. Further, in the present invention, 9 18475 1275150 'the carrier plate can accommodate a plurality of places. It is also divided into the same), the size is different (or part of the cymbal, which can form a multi-chip integrated +V body to meet the multi-functional needs of today's electronic products. Clothing, construction, to Fu, in the present invention On the buried circuit layer of the wafer, the circuit can be added to the circuit, and the high-density and fine (4) semiconductors on the carrier layer of the insulating layer and the wire wafer can be implanted with a plurality of conductive elements on the outer surface of the circuit structure. The structure, the semiconductor wafer in the same right can be directly charged:: To this, the invention can also integrate the semiconductor crystal moon and the device, and provide the manufacturing and sealing and interface coordination of the client than the S 7 carrier due to the loading process. (4) and simplifying the semiconductor industry's 'semiconductor crystals placed on it...spreading to the outside world' to extend the semiconductor crystal encapsulation [embodiment] 7卩(4) mounting structure reliability. Familiar with Llf by a specific embodiment Embodiments of the invention, the present invention: can be easily understood by the content disclosed by the book of the brothers of the book: his advantages and effects. The invention can also be made by other different means: Γ same: line or application, this Say The details in the book can also be based on (4) m. In the spirit of the present invention, various 18475 10 1275150 have the convex portions of the present and the description, and the projections of the vertical (four) limb wafers are The cutting board has two raised portions on the & sub-brothers, but the Asian and African restrictions on the present invention. Center::::2:: Detailed description of the wafer embedded embedding red earth of the present invention. As shown in the figure, the package is ==:: one, the carrier plate 2 is formed with a convex (four), and the semiconductor wafers 21a, 21b are respectively placed at the 0 ^ portion 2〇1, 2〇2 of the bearing 2 An 'insulating layer 22 is formed on the carrier 20 and the semiconductor wafers..., (10); and a circuit layer μ is formed on the insulating layer 22, and the circuit layer 23 is electrically connected to the The semiconductor package 21a, 21b. In addition, the 5th package structure 2 may include at least one semiconductor wafer 21c' attached to the carrier plate 20 on the other side of the protrusions 2〇1, 2〇2"" a region, and the circuit layer 23 is electrically connected to the semiconductor wafer 2] k. The material of the carrier 20 can be combined with the protrusions 2〇1, 2〇2 The materials are the same or different, and may be made of one of a metal, a ceramic, and a high heat dissipation material. The semiconductor wafer 21 a, 21 b is attached to the protrusions 2 〇 1, 202, and the semiconductor wafer The 21c is directly attached to the carrier plate 2. The carrier plate 20 and the protrusions 20, 2 2 can also be a structure formed by, for example, metal, ceramic or high heat dissipation material. 21 a, 21 b are formed with active faces 211a, 211b of a plurality of electrode pads 210a, 210b, and non-active faces 212 a, 212b' opposite the active faces and the semiconductor wafers 21a, 21b are not 18475 11 1275150 The active surface 21 2a, 212b is placed on the convex portion 20 2 (2) through an adhesive layer (not shown); the semiconductor wafer 2lG is directly attached to the carrier plate 20, and the distal half body The wafer 21c is formed with an active surface 211c having a plurality of electrodes 〇2i 〇c and an inactive surface 212c opposite to the active surface, and the semiconductor wafer 21c is passed through an adhesive layer (not shown) by the non-active surface 212c. Directly placed on the carrier plate 20. The semiconductor wafers 21a, 21b, 21c described above may be any combination of active or passive wafers. The thickness of the semiconductor wafers 21a, 21b, 21c may be different; and the height of the protrusions 201, 202 formed on the carrier plate may be different depending on the thickness of the semi-conductive solar panels 21a, 21b, 21c. The change is added to maintain the active faces 211a, 211b, and 211c of the semiconductor wafers 21a, 21b, and 21c in the same plane, thereby facilitating the subsequent fine electrical wiring process on the wafer. The insulating layer 22 is formed on the carrier plate 2 and the semiconductor wafers 21a, 21b, 21c, and the insulating layer 22 is completely filled in the gap between the adjacent protrusions. The insulating layer 22 may be, for example, an organic thin film dielectric material or a liquid organic resin material; the above material may be selected from ABF (Ajin〇m〇t〇).

Build-up Film )、BCB(Benzocyclo-buthene)、LCP(LiquidBuild-up Film ), BCB (Benzocyclo-buthene), LCP (Liquid

Crystal Polymer) > PI (p〇ly-imide) > PPE(P〇ly(phenylene ether))、PTFE(Poly(tetra-fluoroethylene))、FR4、FR5、 BT(Bismaleimide Triazine)、芳香尼龍（Aramide)等感光 或非感光有機樹脂，或亦可混合環氧樹脂與玻璃纖維等材 質所構成。 該線路層23係形成於該絕緣層22上，並可藉由形成 18475 12 1275150 於該絕緣層22中之多數導電結構222(例如為導電盲孔或 導電凸塊等）而電性導接至該些半導體晶片21a、2仙、2卜 上之电極墊210a、210b、210c，並可藉由線路層23電性 =接半導體晶片21a、2lbOlc，另在該線路層23之部 /刀外表面上則形成有多數電性連接I 234，且於該線路層 23上係被覆有一防焊層25,該防焊層託係具有多數開口 以外露出該電性連接塾234,用以提供植置有多數之導電 :件26 ’而該些半導體晶片進而可形成整合有多晶片模組 尺之：導體晶片封裝結構。該線路層23之形成方式係為業 "所習知之製程技術，故在此不再為文贅述。 八 相較於習知技術，本發明之晶片嵌埋式封裝結構，主 =係將半導體晶片接置於該承餘之凸起部上，從而可藉 忒承載板所具有之凸起部以調整凸起部間絕緣層 溫度變化過程中’平衡封裝結構所受到的 規、：二從而可避免封裝結構於製程溫度 1現象的產生。且透過該凸起部可提供接置其上之中= 之支可避免封裝結構趣曲而造成晶片:;損 此本發明係將半導體晶片接置於凸起部上，從而 可避免白知全面增加承裁板之厚度， 二 構成品之重量，且本發明可彳 ^ 17 ’ y、遠封裝結 之厚度以使不同厚度之半導體晶::置二 等半導體晶㈣性連接表面維持在同一：載= 性，以方便㈣進行線路製程，料提 18475 13 27s15〇 私成線路製程之可靠度。 後續於本發明之封裴結構中，亦 %緣；s & 依據声' ^而要於該 冬層22及線路層23上進行線路增芦 電性設計之線路連接。 θ ^構成所需Crystal Polymer) > PI (p〇ly-imide) > PPE (P〇ly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), Aromatic Nylon (Aramide) A photosensitive or non-photosensitive organic resin, or a mixture of an epoxy resin and a glass fiber. The circuit layer 23 is formed on the insulating layer 22, and can be electrically connected to the plurality of conductive structures 222 (for example, conductive blind vias or conductive bumps) in the insulating layer 22 by forming 18475 12 1275150. The electrode pads 210a, 210b, 210c of the semiconductor wafers 21a, 2, 2, and 2 can be electrically connected to the semiconductor wafers 21a, 2lbOlc by the wiring layer 23, and further outside the circuit layer 23 A plurality of electrical connections I 234 are formed on the surface, and a solder resist layer 25 is coated on the circuit layer 23, and the solder resist layer has a plurality of openings to expose the electrical connection ports 234 for providing the implants. There is a majority of the conductive: 26' and the semiconductor wafers can in turn form a multi-chip module scale: a conductor chip package structure. The formation of the circuit layer 23 is a well-known process technology, and therefore will not be described herein. Compared with the prior art, the wafer embedded package structure of the present invention mainly connects the semiconductor wafer to the convex portion of the bearing, so that the convex portion of the carrier plate can be adjusted. During the temperature change of the insulating layer between the protrusions, the balance of the package structure is: 2, so that the phenomenon of the package structure at the process temperature 1 can be avoided. And through the raised portion, the support can be provided to prevent the package structure from being disturbed to cause the wafer: the invention is to attach the semiconductor wafer to the convex portion, thereby avoiding comprehensive The thickness of the cutting board is increased, and the weight of the two components is increased, and the thickness of the package can be made to be such that the semiconductor crystals of different thicknesses are maintained at the same level: Load = sex, to facilitate (4) to carry out the line process, and to estimate the reliability of the 18475 13 27s15 〇 private line process. Subsequent to the sealing structure of the present invention, the edge is also connected to the circuit layer 23 and the circuit layer 23 according to the sound. θ ^ constitutes the required

請參閱第2Β圖，俜a於笛9 A 略声23 圖所示之絕緣層22及線 曰23上進仃線路增層製程所形成之 一 意圖。其結構與第Μ圖所示 、、、、’口 面不 層22及綠敗— 構大致相同，惟於該絕緣 • "上復形成有一線路增層結構24。 該線路增層結構24係包括有 緣屉94Π l > μ a 承尽Z4U、《置於該絕 曰 上之、、泉路層242、以及穿過哕頌缝js 9/ln 242a。 承曰r万綠路層23之導電盲孔 有多===層結構24之外表面之線路層上則形成 -防焊芦25卞244 ’且於該最外層線路層上係被覆有 :坏層25’该防焊層25係具有 =2;4,提供植置有多數之軸 二Τ、導電柱或焊柱，俾供一 …元二: 層23、該線路增層結構24以及 意二SI:而電性導接至外部電子裂置。此外⑽ 實際需求増二層結構㈣圖示之層數為限’而可因應 裝結發明之晶片嵌埋式封 到土貫施例之剖面示意圖，與前-實施例不 14 18475 1275150 上凸起部係—體成形於承載板上。如圖所示，該 上以電物刻的方式形成有 使兮此〇b上付为別接置半導體晶片21a、21b， 性延伸之細線路=程。千面’俾利於在該晶片上進行後續電 j此’本發明之晶片嵌埋式封裝結 體晶片放置於承载板 再王要知將+¥ ，有之凸起部以調並可藉由該承載板所具 料及承载板之〜。Bi之㈣層材料、增層絕緣層材 戰板之尽度，以便於平 封裝結構所受到的熱應力&程中晶片 ，封裝結構龜曲現象之產生變化過程 散熱板厚度以改善製程溫产微^了避免習知技術中增加 曲狀況所引起的封I结構裝::產生_ 同厚度之半導俨日H拉$ 凋正凸起。卩之厚度以使不 之^t 於該承载板後，該等半導η 之面維持在同一平面，以二= 片之承载板表面之絕緣層表 有牛^曰 升後續於絕緣層上形成線路製程之；靠；―:：，進而提 明中，該承載板中可收纳夕*w J罪度。此外，於本發 戋邻八4门、 、、、内夕數個功能不相同（或相同，亦 。刀相同）之半導體晶片“ （飞相门亦 化之半導體晶片封裝έ士構，以#a y成正5有多晶片模組 求。 合現今電子產品多功能需 絕緣層及線 再者，於本發明之晶片嵌埋式封裝結構之 18475 15 1275150 路層上，復可進行線路增 晶片之承載板上形成高密度及'田線7在該嵌埋有半導體 時可在線路結構外表面 之：層線路結構，同 承載板中之半導铲曰v电兀件，藉以供嵌埋於 此，本發明亦可二ί = ί接電性連接至外部裝置，因 程’提供客戶端較大需求彈性以及，件之‘造與封裝過 介面協調問題。 間匕半導體業者製程與 玉此外纟發明之晶片嵌埋式封裝 散熱之金屬材料、陶究 & 、、、、°冓之承載板係由高 程，因而可藉由今承1 鳴材料其中之-者所製 之彻曰作爲散熱路徑將直接接置於心 界，延長半導體晶片之妄人及的散逸至外 上述實施例僅為之可靠性。 而非用於㈣本發明。任何孰f H及其功效， 違背本發明之精神及範蜂下，對上、才 =蟄之人士均可在不 此本發明之權㈣護㈣，應如後進㈣改。因 【圖式簡單説明】 申明專利砣圍所列。 第1圖係為習知之整合半導體晶片 —第^圖係為本發明之晶片嵌埋式封裝結^構， 貫施悲樣之剖面示意圖； 1、。 k佳 弟2B圖係為本發明之晶月故埋式封裂 實施態樣進行線路增層製程之封音^較佳 圖係為本發明之晶片歲埋式封裝結構;：較; 知恶樣之剖面示意圖。 ^土貝 18475 16 1275150Referring to Figure 2, 俜a is intended to be formed on the insulating layer 22 and the winding line 23 on the insulating layer 22 and the winding line 23 shown in Figure 9A. The structure is substantially the same as that shown in the figure, and is not the same as the layer 22 and the green failure structure, except that the insulation layer is formed with a line buildup structure 24. The line build-up structure 24 includes a rim drawer 94 Π l > μ a bearing Z4U, "placed on the rim, spring road layer 242, and through quilting js 9/ln 242a. There are many conductive blind holes in the 万 万 绿 green road layer 23 === layer structure 24 is formed on the outer layer of the circuit layer - solder resist 25 244 ' and is covered on the outermost circuit layer: bad The layer 25' of the solder resist layer 25 has = 2; 4, providing a plurality of shafts, conductive pillars or soldering posts, and a layer 2, a layer 23, a layer build-up structure 24, and a second layer SI: Electrically conductive to external electronic cracking. In addition, (10) the actual demand, the two-layer structure (4) is limited to the number of layers, and can be embedded in the cross-sectional view of the embedded embedding method of the invention, and the pre-embodiment is not 14 18475 1275150 The department is formed on the carrier plate. As shown in the figure, the upper portion of the semiconductor wafers 21a and 21b is formed by means of electrical etching to form a thin line of the semiconductor wafers 21a and 21b. "Thousands of faces" facilitate the subsequent powering on the wafer. The 'wafer embedded packaged wafer of the present invention is placed on the carrier plate, and the king must know +¥, and the convex portion can be adjusted by the The material of the carrier board and the carrier board are ~. Bi (four) layer material, the thickness of the insulating layer of the insulating layer, in order to facilitate the thermal stress of the flat package structure, the wafer in the process, the tortuosity of the package structure changes, the thickness of the heat sink to improve the process temperature Micro-enclosures to avoid the increase in the condition of the prior art caused by the structure of the package I:: _ _ the same thickness of the semi-conducting day H pull $ with positive bulge. The thickness of the crucible is such that after the carrier plate, the faces of the semiconducting η are maintained in the same plane, and the insulating layer on the surface of the carrier plate of the two = sheet is formed on the insulating layer. The line process; rely on; ―::, and then in the description, the carrier board can accommodate the sin*w J crime. In addition, there are several semiconductor wafers with different functions (or the same, also the same knife) in the eight-door, four-door, and the inner eve of this issue. Ay Chengzheng 5 has more than one chip module. Nowadays, the electronic product needs multi-layer insulation layer and wire. On the 18475 15 1275150 road layer of the wafer embedded package structure of the present invention, the line can be loaded with the wafer. Forming a high density on the board and the 'field line 7' may be on the outer surface of the line structure when the semiconductor is embedded: a layer line structure, and a semi-conducting shovel v electric part in the carrier board, for embedding therein, The invention can also be electrically connected to an external device, because the process provides a large demand elasticity of the client and the problem of the coordination between the device and the package interface. The carrier material of the embedded material of the embedded heat-dissipating package is made of high-grade, so that it can be directly used as a heat-dissipating path by the one of the materials Connected to the heart, extended The above embodiments of the semiconductor wafer are only reliable, and are not used for (4) the present invention. Any 孰f H and its effects are contrary to the spirit of the present invention, and the above is the only one. Anyone who can not use this invention (4) protects (4), should be changed as follows (4). Because [simplified description of the schema] is declared as a patent. The first figure is a conventional integrated semiconductor wafer - the first figure The present invention is a schematic diagram of a cross-sectional structure of a buried embedded package structure according to the present invention; 1. k Jiadi 2B is a circuit layer build-up process of the crystal moon buried buried cracking embodiment of the present invention. The sound-blocking ^ is a wafer-in-the-earth package structure of the present invention;: a cross-sectional view of a known evil sample. ^Tubei 18475 16 1275150

【元件符號簡單説明】 1、2 封裝結構 12 散熱板 120 開口 13 半導體晶片 130 電極塾 14 絕緣層 15 線路層 150 導電結構 20 承載板 201 、 202 、 20a 、 20b 凸起部 21a 、 21b 、 21c 半導體晶片 210a 、 210b 、 210c 電極塾 211a 、 211b 、 211c 電路面 212a 、 212b 、 212c 非電路面 23 絕緣層 222 導電結構 24 線路層 25 線路增層結構 240 絕緣層 242 線路層 242a 導電盲孔 244 電性連接墊 25 防焊層 26 導電元件 17 18475[Description of Component Symbols] 1, 2 Package Structure 12 Heat Sink 120 Opening 13 Semiconductor Wafer 130 Electrode 塾 14 Insulation Layer 15 Circuit Layer 150 Conductive Structure 20 Carrier Plates 201, 202, 20a, 20b Projections 21a, 21b, 21c Semiconductor Wafers 210a, 210b, 210c Electrodes 塾211a, 211b, 211c Circuit faces 212a, 212b, 212c Non-circuit surface 23 Insulation layer 222 Conductive structure 24 Circuit layer 25 Line build-up structure 240 Insulation layer 242 Circuit layer 242a Conductive blind hole 244 Electrical Connection pad 25 solder mask 26 conductive element 17 18475

Claims (1)

1275150 十、申請專利範圍·· 1 · 一種晶片嵌埋式封裝結構，係包括： -承載板，且該承載板上係形成至 至少一第一半導體晶片，係凸U， 該第一半導體曰# ^凸起部上，且 千ν月且日日片上具有多數電極墊； 一絕緣層，係形成於該承载板 上；以及 /乐 +導體晶片 I 一線路層，係形成於該絕緣層上，且 透過形成於該絕緣層中之導電結構性5連ς路層^以 一半導體晶片之電極墊。 随連接至该第 2. 如申請專利範圍第！項之晶片嵌 該線路層上復形成一線路增層 ^ [、吉構，其中， 係可電性導接至該線路層。 以線路增層結構 3. 如申請專利範圍第2項之晶片嵌埋 該線路增層結構係包括有絕緣居、:告構，其中， 線路層、以及穿過兮 、置於該絕緣層上之 汉牙過δ亥絕緣層以供該線 緣層下方線路層之導電盲孔。 s书性連接至絕 4. 如申請專利範圍第2項之晶 該線路增層結構外表面係植設有多二結構，其中， 該半導紐連接至外 俾可供 5. 如申請專利範圍第丨項之晶月嵌埋= 該承載板係由全J & 工、羞、、、吉構，其中， 成。 心“散熱材料其中之—者所t 6. 如申請專利範圍 貝之日日片甘欠埋式封裝結構，其中， 18475 1275150 =凸起部係由金屬、陶纽高散熱 成。 /、〒之一者所製 •如申π專利乾圍第！項之晶片嵌埋式 該承載板之材料可與該 ’一構，其中， δ.如申請專利範圍第1項之晶片 該承載板之材料可與該 #結構’其中， 该凸起部係為額外接置於該承载板上構，其中， 1〇.如申請專利範圍第！項之晶片t封卜構 该承載板與凸起部係為-體成型之構、告其中， 11·如申請專利範圍第丨項之晶片爭 = 哕篦主谨遍 人里式封裝結構，苴中， 導體晶片係為主動式晶片及被動式晶片其中 12. 如申請專利範圍第丨項之u嵌 該承載板之凸起部以外之μ>忒、·。構，其中， 且該第二半導體晶片上具有多數電極塾， 心泉路層係透過形成於該絕緣層中之該導電結構帝 ’生連接至該第二半導體晶片之電極墊。 电 13. 如申請專㈣圍第丨2項之晶片嵌埋式封i结構，其 :’該第二半導體晶片係為主動式晶片及被 中之一者。 … 14. 如申請專利範圍第12項之晶片嵌埋式封裝結構，其 中，該第一及第二半導體晶片之厚度係不同，且形成於 。亥承載板上之凸起部高度係可因應該第一及第二半導 18475 19 1275150 體晶片之不同厚度而加變化，以使該些半導體晶片之電 性連接表面得以維持在同一平面。 20 184751275150 X. Patent Application Scope 1 · A wafer embedded package structure includes: - a carrier plate, and the carrier plate is formed to at least one first semiconductor wafer, the protrusion U, the first semiconductor 曰# ^ on the raised portion, and a plurality of electrode pads on the wafer and the solar array; an insulating layer is formed on the carrier plate; and /Le + conductor wafer I a circuit layer is formed on the insulating layer, And passing through the conductive structural 5 connecting circuit layer formed in the insulating layer to form an electrode pad of a semiconductor wafer. With the connection to the second 2. As claimed in the patent scope! The wafer of the item is embedded on the circuit layer to form a line-increasing layer ^, and the structure is electrically connected to the circuit layer. In the case of a circuit-added structure, the wafer-embedded structure of the second aspect of the patent application includes an insulating structure, wherein the circuit layer and the through-layer are placed on the insulating layer. The Han tooth passes through the δ hai insulation layer for the conductive blind holes of the circuit layer below the line edge layer. s book connection to the fourth 4. For example, the outer surface of the line-added structure of the patent application scope has a plurality of structures, wherein the semi-conductor is connected to the outer casing. 5. The crystal moon embedding of the third item = the carrier plate is composed of all J & work, shame, and ji, in which. The heart "heat-dissipating material among them" is as follows: 6. If the patent application scope is on the day of the film, the piece is immersed in the buried package structure, in which 18475 1275150 = the convex part is made of metal and ceramic high heat. /, 〒之之The material of the carrier plate can be embedded with the material of the carrier plate, such as the material of the wafer of the first embodiment of the invention. And the structure of the structure, wherein the raised portion is additionally attached to the carrier plate, wherein, the wafer is sealed according to the scope of the patent application; - The formation of the body, tells it, 11 · The wafer contention of the scope of the patent application = = 哕篦 哕篦 哕篦 人 人 人 人 人 人 人 人 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体The second aspect of the patent application scope is embedded in the outer surface of the carrier plate, wherein the second semiconductor wafer has a plurality of electrode electrodes, and the core spring layer is formed through the insulation. The conductive structure in the layer is connected to The electrode pad of the second semiconductor wafer. 13. The application of the embedded semiconductor package structure of the second (4), the second semiconductor wafer is an active wafer and one of the ... 14. The wafer embedded package structure of claim 12, wherein the thicknesses of the first and second semiconductor wafers are different, and the height of the protrusions formed on the board on the board is suitable for the first The thicknesses of the first and second semiconductors 18475 19 1275150 are varied to maintain the electrical connection surfaces of the semiconductor wafers in the same plane.
TW094115339A 2005-05-12 2005-05-12 Embedded chip package structure TWI275150B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI426588B (en) * 2010-10-12 2014-02-11 Advanced Semiconductor Eng Package structure and package process
US11399438B2 (en) 2019-01-07 2022-07-26 Delta Electronics (Shanghai) Co., Ltd. Power module, chip-embedded package module and manufacturing method of chip-embedded package module

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI474417B (en) * 2014-06-16 2015-02-21 Phoenix Pioneer Technology Co Ltd Package method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI426588B (en) * 2010-10-12 2014-02-11 Advanced Semiconductor Eng Package structure and package process
US11399438B2 (en) 2019-01-07 2022-07-26 Delta Electronics (Shanghai) Co., Ltd. Power module, chip-embedded package module and manufacturing method of chip-embedded package module

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