JPH08330471A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH08330471A JPH08330471A JP13821495A JP13821495A JPH08330471A JP H08330471 A JPH08330471 A JP H08330471A JP 13821495 A JP13821495 A JP 13821495A JP 13821495 A JP13821495 A JP 13821495A JP H08330471 A JPH08330471 A JP H08330471A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- heat dissipation
- package
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＢＧＡ（Ball Grid Ar
ray)パッケージの半導体装置に関する。近年、電子機器
に搭載される半導体装置は高機能かつ低コストのものが
求められており、ＢＧＡパッケージの利用が拡大してき
ている。このＢＧＡパッケージの半導体装置では、ボー
ル電極形成の簡略化が望まれていると共に、品質向上の
ための低熱抵抗化が望まれている。The present invention relates to a BGA (Ball Grid Ar).
ray) package semiconductor device. In recent years, semiconductor devices mounted on electronic devices are required to have high functionality and low cost, and the use of BGA packages is expanding. In the semiconductor device of the BGA package, simplification of ball electrode formation is desired and low thermal resistance for quality improvement is desired.
【０００２】[0002]
【従来の技術】図７に、従来のＢＧＡパッケージの半導
体装置の構成図を示す。図７に示す半導体装置１１は、
底面（ボール電極側）を上方にした斜視図であり、図７
（Ａ）は斜視図、図７（Ｂ）は縦側断面図である。図７
（Ａ），（Ｂ）の半導体装置１１において、ガラスエポ
キシ樹脂等で形成された基板１２の中央部分が開口され
てアルミニウム及び銅等で形成された放熱板１３が設け
られており、この放熱板１３上に接着剤１４により半導
体チップ１５が搭載される。2. Description of the Related Art FIG. 7 is a block diagram of a conventional BGA package semiconductor device. The semiconductor device 11 shown in FIG.
7 is a perspective view with the bottom surface (ball electrode side) facing upward, and FIG.
7A is a perspective view, and FIG. 7B is a vertical cross-sectional view. Figure 7
In the semiconductor device 11 of (A) and (B), a heat radiating plate 13 made of aluminum, copper or the like is provided by opening a central portion of a substrate 12 made of glass epoxy resin or the like. A semiconductor chip 15 is mounted on 13 by an adhesive 14.
【０００３】そして、半導体チップ１５と基板１２との
間でワイヤ１６により電気的接続が行われてモールド樹
脂１７によりパッケージングされ、基板１２の表出面の
パッド上に対応してはんだ等のボール電極１８が所定数
形成される。すなわち、半導体装置１１の底面における
ボール電極１８の形成領域以外の中央部分に放熱板１３
が設けられて半導体チップ１５の発熱を外部に放散す
る。Then, the semiconductor chip 15 and the substrate 12 are electrically connected by the wires 16 and packaged by the molding resin 17, and ball electrodes such as solder corresponding to the pads on the exposed surface of the substrate 12 are formed. A predetermined number of 18 are formed. That is, the heat radiating plate 13 is formed on the central portion of the bottom surface of the semiconductor device 11 other than the formation region of the ball electrode 18.
Is provided to dissipate the heat generated by the semiconductor chip 15 to the outside.
【０００４】そこで、図８に、図７のボール電極形成の
製造工程図を示す。図８において、図８（Ａ）はボール
電極１８が形成される直前の状態を示しており、この構
造は上述の通りである。そして、図８（Ｂ）に示すよう
に、金属板にボール電極に対応する位置に、該ボール電
極の直径よりやや大の孔１９ａが形成されたマスク１９
が位置される。Therefore, FIG. 8 shows a manufacturing process diagram for forming the ball electrode shown in FIG. In FIG. 8, FIG. 8A shows a state immediately before the ball electrode 18 is formed, and this structure is as described above. Then, as shown in FIG. 8B, a mask 19 in which a hole 19a having a diameter slightly larger than the diameter of the ball electrode is formed in the metal plate at a position corresponding to the ball electrode.
Is located.
【０００５】続いて、図８（Ｃ）に示すようにマスク１
９の孔１９ａ内に例えばはんだで形成されたボール１８
ａがそれぞれ挿入される。ボール１８ａの挿入後に加熱
することで該ボール１８ａを溶融させ、図８（Ｄ）に示
すように基板１２上に固着させることによりボール電極
１８が形成される。そして、図８（Ｅ）に示すように、
マスク１９を取り除くことにより、図７に示す半導体装
置１１となるものである。Subsequently, as shown in FIG. 8C, the mask 1
Balls 18 made of, for example, solder in the holes 19a
a is inserted respectively. The ball electrode 18 is formed by melting the ball 18a by heating after the ball 18a is inserted and fixing the ball 18a on the substrate 12 as shown in FIG. 8 (D). Then, as shown in FIG.
By removing the mask 19, the semiconductor device 11 shown in FIG. 7 is obtained.
【０００６】なお、半導体チップ１５の高機能化に伴っ
てボール電極１８の個数が増大する場合には、基板１２
を多層基板で形成して対処することが行われている。When the number of ball electrodes 18 increases as the semiconductor chip 15 becomes more sophisticated, the substrate 12
Has been dealt with by forming a multi-layer substrate.
【０００７】[0007]
【発明が解決しようとする課題】しかし、放熱板１３を
半導体装置１１の底面の中央部分に設けただけでは、半
導体チップ１５が大容量化すると十分に放熱を行うこと
ができず、熱抵抗を低下させることができないという問
題がある。However, if the heat dissipation plate 13 is provided only in the central portion of the bottom surface of the semiconductor device 11, sufficient heat cannot be dissipated when the semiconductor chip 15 has a large capacity, and thermal resistance is reduced. There is a problem that it cannot be lowered.
【０００８】また、ボール電極１８の形成にあたって、
マスク１９を使用することから、形成後に該マスク１９
を取り除く工程等を必要として工程削減による簡略化す
ることができないという問題がある。そこで、本発明は
上記課題に鑑みなされたもので、低熱抵抗化、製造工程
の簡略化を図り、品質の向上及び歩留りの向上を図る半
導体装置を提供することを目的とする。In forming the ball electrode 18,
Since the mask 19 is used, the mask 19 is not formed after formation.
However, there is a problem that it is not possible to simplify the process by reducing the number of processes and the like. Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device in which the thermal resistance is reduced, the manufacturing process is simplified, and the quality and yield are improved.
【０００９】[0009]
【課題を解決するための手段】上記課題を解決するため
に、請求項１では、基板上に半導体チップを搭載し、該
基板の一方面を表出させて樹脂封止されたパッケージ部
と、該パッケージ部の表出された該基板の一方面に所定
数設けられる実装のための突起電極と、該突起電極に対
応する位置に貫通穴が所定数形成され、当該突起電極の
一部を所定量突出させて該基板の一方面に設けられる放
熱部と、を有する半導体装置が構成される。In order to solve the above-mentioned problems, in a first aspect of the present invention, a semiconductor chip is mounted on a substrate, and one side of the substrate is exposed, and a resin-sealed package portion is provided. A predetermined number of mounting projection electrodes are provided on one surface of the substrate exposed on the package portion, and a predetermined number of through holes are formed at positions corresponding to the projection electrodes, and a part of the projection electrodes is provided. A semiconductor device having a heat radiating portion that is provided on one surface of the substrate by protruding a certain amount is configured.
【００１０】請求項２では、請求項１において、前記放
熱部の表面上に絶縁部材が形成されてなる。請求項３で
は、請求項１又は２の何れか一項において、前記放熱部
は、前記パッケージ部の取り付け平面より大にして設け
られる。According to a second aspect, in the first aspect, an insulating member is formed on the surface of the heat dissipation portion. According to a third aspect of the present invention, in any one of the first or second aspects, the heat dissipation portion is provided so as to be larger than a mounting plane of the package portion.
【００１１】請求項４では、請求項３記載の放熱部の所
定部分に、実装時の位置決めを行うための位置決め部が
形成されてなる。請求項５では、半導体チップを搭載
し、実装のための所定数の突起電極を有するパッケージ
における半導体装置の製造方法において、所定基板上に
半導体チップを搭載して所定の電気的接続の後に該基板
の一方面を表出させてパッケージングを行う工程と、表
出された該基板の一方面に、所定数の貫通穴が形成され
た放熱部を取り付ける工程と、該放熱部をマスクとして
該貫通穴内の前記基板上に所定大の電極部材をそれぞれ
位置させる工程と、それぞれの該電極部材を溶融させて
該基板上に固着し、該放熱部の貫通穴より一部突出させ
て突起電極を形成する工程と、を含んで半導体装置の製
造方法が構成される。According to a fourth aspect of the present invention, a positioning portion for performing positioning at the time of mounting is formed on a predetermined portion of the heat radiating portion according to the third aspect. According to a fifth aspect of the present invention, in a method of manufacturing a semiconductor device in a package having a semiconductor chip mounted thereon and having a predetermined number of protruding electrodes for mounting, the semiconductor chip is mounted on a predetermined substrate, and after the predetermined electrical connection, the substrate is mounted. The step of exposing one surface of the substrate for packaging, the step of attaching a heat dissipation part having a predetermined number of through holes formed on the one surface of the exposed board, and the step of using the heat dissipation part as a mask Positioning electrode members of a predetermined size in the holes on the substrate, and melting each of the electrode members and fixing them on the substrate to form a protruding electrode by partially protruding from the through hole of the heat dissipation portion. The method of manufacturing a semiconductor device is configured to include the steps of:
【００１２】[0012]
【作用】上述のように請求項１又は５の発明では、単層
又は多層の基板に半導体チップを搭載したパッケージ部
に貫通穴が所定数形成された放熱部が設けられて、該放
熱部をマスクとして貫通穴内の基板上に突起電極を所定
数形成させる。これにより、放熱部領域の拡大による低
熱抵抗化で品質の向上が図られ、突起電極の製造時にマ
スクとして放熱部を使用して行うことで製造工程の簡略
化による歩留りの向上を図ることが可能となる。As described above, in the invention of claim 1 or 5, the heat dissipation portion having a predetermined number of through holes is provided in the package portion having the semiconductor chip mounted on the single-layer or multi-layer substrate, and the heat dissipation portion is provided. As a mask, a predetermined number of protruding electrodes are formed on the substrate in the through holes. This improves the quality by lowering the thermal resistance by expanding the heat dissipation area, and by using the heat dissipation section as a mask when manufacturing the protruding electrodes, it is possible to improve the yield by simplifying the manufacturing process. Becomes
【００１３】請求項２の発明では、放熱部の表面上に絶
縁部材を形成する。これにより、突起電極の放熱部への
短絡を確実に防止することが可能となる。請求項３の発
明では、放熱部をパッケージ部より大にして該パッケー
ジ上に設ける。これにより、放熱効果がより向上して低
熱抵抗化を図ることが可能となる。According to the second aspect of the invention, the insulating member is formed on the surface of the heat radiating portion. This makes it possible to reliably prevent a short circuit of the protruding electrode to the heat dissipation portion. According to the third aspect of the invention, the heat radiating portion is made larger than the package portion and provided on the package. As a result, it is possible to further improve the heat dissipation effect and reduce the thermal resistance.
【００１４】請求項４の発明では、パッケージ部より大
の放熱部の所定部分に位置決め部を形成する。これによ
り、実装時の位置決めを容易に行うことが可能となる。According to the fourth aspect of the present invention, the positioning portion is formed at a predetermined portion of the heat radiation portion which is larger than the package portion. This makes it possible to easily perform positioning during mounting.
【００１５】[0015]
【実施例】図１に、本発明の一実施例の全体斜視図を示
す。また、図２に図１の底面図及び縦側断面図を示すと
共に、図３に図１の放熱板の斜視図を示す。図１に示す
半導体装置２１は、ＢＧＡパッケージで底面を上方にし
たもので、後述する半導体チップを搭載したパッケージ
部２２に放熱部である放熱板２３が接着剤等により取り
付けられて設けられる。この放熱板２３は、図３に示す
ように、例えばアルミニウム及び銅等の熱伝導性の良好
な金属板上に、後述するボール電極（ボール電極が設け
られる基板のパッド）に対応する貫通穴２３ａが所定数
形成される。すなわち、放熱板２３は、パッケージ部２
２への取り付け平面の大きさを同等にして、中央の所定
領域以外の部分に貫通穴２３ａが形成されたものであ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an overall perspective view of an embodiment of the present invention. 2 shows a bottom view and a vertical sectional view of FIG. 1, and FIG. 3 shows a perspective view of the heat sink of FIG. A semiconductor device 21 shown in FIG. 1 is a BGA package with a bottom surface facing upward, and is provided with a heat radiating plate 23, which is a heat radiating portion, attached to a package portion 22 on which a semiconductor chip described later is mounted by an adhesive or the like. As shown in FIG. 3, the heat dissipation plate 23 is formed on a metal plate having good thermal conductivity, such as aluminum and copper, and a through hole 23a corresponding to a ball electrode (a substrate pad on which the ball electrode is provided) described later. Are formed in a predetermined number. That is, the heat dissipation plate 23 has the package portion 2
The through holes 23a are formed in a portion other than a predetermined central region by making the sizes of the mounting planes of the two to be equal.
【００１６】図１に戻り、パッケージ部２２に取り付け
られた放熱板２３の各貫通穴２３ａより一部を突出され
て突起電極であるボール電極２４が設けられている。こ
のボール電極２４は、後述する基板の一方面のパッドに
固着されるもので、図２（Ａ）の底面図に示すように放
熱板１２３の貫通穴２３ａとは非接触状態で絶縁されて
いる。Returning to FIG. 1, a ball electrode 24, which is a protruding electrode, is provided by partially protruding from each through hole 23a of the heat dissipation plate 23 attached to the package portion 22. The ball electrode 24 is fixed to a pad on one surface of the substrate, which will be described later, and is insulated from the through hole 23a of the heat dissipation plate 123 in a non-contact state as shown in the bottom view of FIG. .
【００１７】一方、パッケージ部２２は、図２（Ｂ）に
示すように、例えばガラスエポキシ樹脂等で形成された
基板２５上の略中央部分に銀ペースト等の接着剤２６に
より半導体チップ２７が搭載され、基板２５上の対応す
るパターン（パッド）とワイヤ２８により電気的接続が
行われる。この場合、基板２５の半導体チップ搭載面の
反対面（一方面）には、半導体チップ２７の入出力のた
めのパッド（図に表われず）が形成され、このパッドに
上記ボール電極２４が固着される。そして、基板１５の
上記一方面を表出させて、モールド樹脂２９によりパッ
ケージングがされたものである。On the other hand, in the package portion 22, as shown in FIG. 2B, a semiconductor chip 27 is mounted on the substrate 25 made of, for example, glass epoxy resin or the like in an approximately central portion by an adhesive 26 such as silver paste. Then, the corresponding pattern (pad) on the substrate 25 is electrically connected to the wire 28. In this case, a pad (not shown) for inputting / outputting the semiconductor chip 27 is formed on the surface (one surface) opposite to the semiconductor chip mounting surface of the substrate 25, and the ball electrode 24 is fixed to this pad. To be done. Then, the one surface of the substrate 15 is exposed and packaged with the mold resin 29.
【００１８】このような半導体装置２１は、パッケージ
部２２の一方面の全面に、ボール電極２４を回避する貫
通穴２３ａが形成された放熱板２３A をサイズ拡大して
設けることができることから、半導体チップ２７の発熱
に対して熱抵抗を低減させることができ、品質の向上を
図ることができる。In the semiconductor device 21 as described above, since the heat dissipation plate 23 A having the through hole 23 a for avoiding the ball electrode 24 can be provided on the entire one surface of the package part 22 in an enlarged size, the semiconductor device 21 can be provided. It is possible to reduce the thermal resistance against the heat generated by the chip 27 and improve the quality.
【００１９】また、上記ＢＧＡパッケージの半導体装置
２１を実装する際にはパッケージ重量によりボール電極
２４はつぶれを生じるが、該ボール電極２４は放熱板２
３Aの貫通穴２３ａより一部を所定量突出している状態
であり、当該放熱板２３A の厚さがギャップを保つこと
となり、該厚さを限度としてボール電極２４の過度のつ
ぶれを防止することができるもので、実装の簡略化を図
ることができる。Further, when the semiconductor device 21 of the BGA package is mounted, the ball electrode 24 is crushed due to the package weight.
A part of the through hole 23a of 3 A is projected by a predetermined amount, and the thickness of the heat dissipation plate 23 A keeps a gap, and the ball electrode 24 is prevented from being excessively crushed with the thickness limited. Therefore, the implementation can be simplified.
【００２０】さらに、ボール電極２４を放熱板２３の貫
通穴２３ａより所定量突出させることから、該放熱板２
３の平面を基準として当該ボール電極２４の高さ検査を
容易とすることができる。次に、図４に、図１のボール
電極形成の構成図を示す。図４（Ａ）は、パッケージ部
２２を示したもので、基板２５上に半導体チップ２７が
搭載されて、モールド樹脂２９によりパッケージングさ
れた状態である。続いて、図４（Ｂ）に示すように、パ
ッケージ部２２における基板２５の表出された一方面上
に、ボール電極２４に対応する貫通穴２３ａが形成され
た放熱板２３A が接着剤等により取り付けられる。Further, since the ball electrode 24 is protruded from the through hole 23a of the heat dissipation plate 23 by a predetermined amount, the heat dissipation plate 2
The height of the ball electrode 24 can be easily inspected with reference to the plane of FIG. Next, FIG. 4 shows a configuration diagram of the ball electrode formation of FIG. FIG. 4A shows the package portion 22, in which the semiconductor chip 27 is mounted on the substrate 25 and packaged with the molding resin 29. Subsequently, as shown in FIG. 4B, a heat dissipation plate 23 A having a through hole 23 a corresponding to the ball electrode 24 is formed on one exposed surface of the substrate 25 in the package portion 22 with an adhesive or the like. It is attached by.
【００２１】そこで、図４（Ｃ）に示すように、放熱板
２３A の貫通穴２３ａ内にであって、基板２５のパッド
上に例えばはんだで形成された電極部材２４ａをそれぞ
れ位置させる。このとき、放熱板２３A がボール電極形
成時のマスクの役割をなす。そして、図４（Ｄ）に示す
ように、例えばリフロー加熱（レーザ光加熱でもよい）
を行って電極部材２４ａを溶融させ、基板２５のパッド
上に固着させることにより、ボール電極２４が形成され
る。この場合、放熱板２３A の貫通穴２３ａは基板２５
のパッドより若干広く形成させておくことにより、ボー
ル電極２４の放熱板２３A への接触（短絡）を防止して
いる。[0021] Therefore, as shown in FIG. 4 (C), there is the heat sink 23 A through hole 23a, thereby the electrode member 24a formed on the pad of the substrate 25. For example, solder located respectively. At this time, the heat dissipation plate 23 A serves as a mask when forming the ball electrode. Then, as shown in FIG. 4D, for example, reflow heating (or laser light heating may be used).
Then, the electrode member 24a is melted and fixed on the pad of the substrate 25, whereby the ball electrode 24 is formed. In this case, the through hole 23a of the heat radiating plate 23 A substrate 25
By forming the pad slightly wider than the pad, the contact (short circuit) of the ball electrode 24 with the heat dissipation plate 23 A is prevented.
【００２２】このように、ボール電極２４を形成するに
際して、放熱板２３A にマスクの役割をさせることか
ら、従来のようにマスクの形成や取り付け、取り外しを
行う必要がなく、製造工程を簡略化することができ、歩
留りの向上を図ることができるものである。また、放熱
板２３A をパッケージ部２２の全面に取り付けることか
ら、例えばリフロー時等の該パッケージ部２３の反りが
減小されて歩留りを向上させることができるものであ
る。As described above, when the ball electrode 24 is formed, the heat dissipation plate 23 A plays a role of a mask, so that it is not necessary to form, attach and detach the mask as in the conventional case, and the manufacturing process is simplified. Therefore, the yield can be improved. Further, since the heat dissipation plate 23 A is attached to the entire surface of the package portion 22, the warp of the package portion 23 at the time of reflow, for example, can be reduced and the yield can be improved.
【００２３】次に、図５及び図６に、本発明の他の実施
例の斜視図を示す。図５に示す半導体装置２１は、放熱
板２３B の表面に絶縁材料の絶縁膜３０をコーティング
したもので、他の構成は図１と同様である。これによれ
ば、ボール電極２４の形成時や形成後の外れに対して該
ボール電極２４の短絡をさらに確実に防止することがが
でき、歩留りの向上、品質の向上を図ることができるも
のである。Next, FIGS. 5 and 6 are perspective views showing another embodiment of the present invention. A semiconductor device 21 shown in FIG. 5 has a surface of a heat sink 23 B coated with an insulating film 30 made of an insulating material, and other configurations are similar to those of FIG. According to this, it is possible to more reliably prevent the short circuit of the ball electrode 24 during the formation of the ball electrode 24 and the detachment after the formation, and it is possible to improve the yield and the quality. is there.
【００２４】また、図６に示す半導体装置２１は、パッ
ケージ２２上に設けられる放熱板２３C を、該パッケー
ジ２２の取り付け平面より大に形成し、放熱板２３C の
拡大した領域の所定部分に所定高さの位置決め部として
の突起部３１を形成したもので、他の構成は図１と同様
である。なお、図５と同様に、放熱板２３C の表面上に
絶縁膜をコーティングしてもよい。Further, the semiconductor device 21 shown in FIG. 6, the heat radiating plate 23 C provided on the package 22, formed in the larger than the mounting plane of the package 22, a predetermined portion of the enlarged area of the heat sink 23 C The protrusion 31 is formed as a positioning portion having a predetermined height, and other configurations are the same as those in FIG. Note that, as in FIG. 5, an insulating film may be coated on the surface of the heat dissipation plate 23 C.
【００２５】これによれば、当該半導体装置２１をプリ
ント基板等に実装する際に、突起部３１を位置決めの基
準とすることにより、容易に位置決めを行うことができ
る。また、実装時に当該半導体装置２１をプリント基板
に所定圧力で押圧したときに、突起部３１の高さでボー
ル電極２４の過度のつぶれを防止することができ、歩留
りの向上を図ることができる。さらに、放熱板２３C を
拡大することで放熱特性が向上されて、さらに低熱抵抗
化を図ることができ、品質の向上を図ることができるも
のである。According to this, when the semiconductor device 21 is mounted on a printed circuit board or the like, positioning can be easily performed by using the projection 31 as a positioning reference. Further, when the semiconductor device 21 is pressed against the printed circuit board with a predetermined pressure during mounting, the height of the protrusion 31 can prevent the ball electrode 24 from being excessively crushed, and the yield can be improved. Further, by enlarging the heat dissipation plate 23 C , the heat dissipation characteristics are improved, the thermal resistance can be further reduced, and the quality can be improved.
【００２６】なお、上記実施例では、突起電極としてボ
ール電極２４の場合を示したが、柱状等の電極（広い意
味でのＢＧＡパッケージ）でもよい。また、上記実施例
では単層の基板２５を用いたが、多層のものでもよい。
さらに、上記実施例ではプラスチックパッケージの場合
を示したが、ベアチップパッケージ又はセラミックパッ
ケージについても適用することができるものである。In the above embodiment, the ball electrode 24 is used as the protruding electrode, but a columnar electrode (BGA package in a broad sense) may be used. Further, although the single-layer substrate 25 is used in the above embodiment, a multi-layer substrate may be used.
Further, although the above-mentioned embodiment shows the case of the plastic package, it can be applied to a bare chip package or a ceramic package.
【００２７】[0027]
【発明の効果】以上のように上述のように請求項１又は
５の発明によれは、単層又は多層の基板に半導体チップ
を搭載したパッケージ部に貫通穴が所定数形成された放
熱部が設けられて、該放熱部をマスクとして貫通穴内の
基板上に突起電極を所定数形成させることにより、放熱
部領域の拡大による低熱抵抗化で品質の向上が図られ、
突起電極の製造時にマスクとして放熱部を使用して行う
ことで製造工程の簡略化による歩留りの向上を図ること
ができる。As described above, according to the invention of claim 1 or 5, as described above, there is provided a heat radiating portion having a predetermined number of through holes formed in a package portion in which a semiconductor chip is mounted on a single-layer or multi-layer substrate. By providing a predetermined number of projecting electrodes on the substrate in the through hole using the heat dissipation portion as a mask, it is possible to improve the quality by lowering the thermal resistance by expanding the heat dissipation portion area,
By using the heat radiating portion as a mask when manufacturing the protruding electrodes, it is possible to improve the yield by simplifying the manufacturing process.
【００２８】請求項２の発明によれば、放熱部の表面上
に絶縁部材を形成することにより、突起電極の放熱部へ
の短絡を確実に防止することができる。請求項３の発明
によれば、放熱部をパッケージ部より大にして該パッケ
ージ上に設けることにより、放熱効果がより向上して低
熱抵抗化を図ることができる。According to the second aspect of the present invention, by forming the insulating member on the surface of the heat radiating portion, it is possible to reliably prevent the short circuit of the protruding electrode to the heat radiating portion. According to the third aspect of the present invention, by disposing the heat dissipating portion larger than the package portion on the package, the heat dissipating effect is further improved and the low thermal resistance can be achieved.
【００２９】請求項４の発明によれば、パッケージ部よ
り大の放熱部の所定部分に位置決め部を形成することに
より、実装時の位置決めを容易に行うことができる。According to the invention of claim 4, the positioning portion is formed at a predetermined portion of the heat radiation portion larger than the package portion, so that the positioning at the time of mounting can be easily performed.
【図１】本発明の一実施例の全体斜視図である。FIG. 1 is an overall perspective view of an embodiment of the present invention.
【図２】図１の底面図及び縦側断面図である。FIG. 2 is a bottom view and a vertical cross-sectional view of FIG.
【図３】図１の放熱板の斜視図である。FIG. 3 is a perspective view of the heat dissipation plate of FIG.
【図４】図１のボール電極形成の製造工程である。FIG. 4 is a manufacturing process of forming the ball electrode of FIG.
【図５】本発明の他の実施例の斜視図（１）である。FIG. 5 is a perspective view (1) of another embodiment of the present invention.
【図６】本発明の他の実施例の斜視図（２）である。FIG. 6 is a perspective view (2) of another embodiment of the present invention.
【図７】従来のＢＧＡパッケージの半導体装置の構成図
である。FIG. 7 is a configuration diagram of a semiconductor device of a conventional BGA package.
【図８】図７のボール電極形成の製造工程図である。FIG. 8 is a manufacturing process diagram of forming the ball electrode of FIG. 7;
２１ 半導体装置 ２２ パッケージ部 ２３A 〜２３C 放熱板 ２４ ボール電極 ２５ 基板 ２７ 半導体チップ ２９ モールド樹脂 ３０ 絶縁膜 ３１ 突起部21 Semiconductor Device 22 Package Part 23 A to 23 C Heat Sink Plate 24 Ball Electrode 25 Substrate 27 Semiconductor Chip 29 Mold Resin 30 Insulating Film 31 Protrusion
フロントページの続き (72)発明者 米竹 一浩 宮城県柴田郡村田町大字村田字西ケ丘１番 地の１ 株式会社富士通宮城エレクトロニ クス内Front Page Continuation (72) Inventor Kazuhiro Yonetake 1st Nishigaoka, Murata, Murata-cho, Shibata-gun, Miyagi Prefecture 1 In Fujitsu Miyagi Electronics Co., Ltd.
Claims (5)
の一方面を表出させて樹脂封止されたパッケージ部と、 該パッケージ部の表出された該基板の一方面に所定数設
けられる実装のための突起電極と、 該突起電極に対応する位置に貫通穴が所定数形成され、
当該突起電極の一部を所定量突出させて該基板の一方面
に設けられる放熱部と、 を有することを特徴とする半導体装置。1. A package part in which a semiconductor chip is mounted on a substrate, and one surface of the substrate is exposed and resin-sealed, and a predetermined number is provided on the exposed one surface of the substrate of the package part. A protruding electrode for mounting, and a predetermined number of through holes are formed at positions corresponding to the protruding electrode,
A semiconductor device, comprising: a heat radiating portion which is provided on one surface of the substrate by protruding a part of the protruding electrode by a predetermined amount.
に絶縁部材が形成されてなることを特徴とする半導体装
置。2. The semiconductor device according to claim 1, wherein an insulating member is formed on the surface of the heat dissipation portion.
前記放熱部は、前記パッケージ部の取り付け平面より大
にして設けられることを特徴とする半導体装置。3. The method according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the heat dissipation portion is provided so as to be larger than a mounting plane of the package portion.
装時の位置決めを行うための位置決め部が形成されてな
ることを特徴とする半導体装置。4. A semiconductor device according to claim 3, wherein a predetermined portion of the heat dissipation portion is formed with a positioning portion for performing positioning during mounting.
定数の突起電極を有するパッケージにおける半導体装置
の製造方法において、 所定基板上に半導体チップを搭載して所定の電気的接続
の後に該基板の一方面を表出させてパッケージングを行
う工程と、 表出された該基板の一方面に、所定数の貫通穴が形成さ
れた放熱部を取り付ける工程と、 該放熱部をマスクとして該貫通穴内の前記基板上に所定
大の電極部材をそれぞれ位置させる工程と、 それぞれの該電極部材を溶融させて該基板上に固着し、
該放熱部の貫通穴より一部突出させて突起電極を形成す
る工程と、 を含むことを特徴とする半導体装置の製造方法。5. A method for manufacturing a semiconductor device in a package having a semiconductor chip mounted thereon and having a predetermined number of projecting electrodes for mounting, the semiconductor chip being mounted on a predetermined substrate, and after the predetermined electrical connection, the substrate. The step of exposing one surface of the substrate for packaging, the step of attaching a heat dissipation portion having a predetermined number of through holes formed on the one surface of the exposed substrate, and the through hole using the heat dissipation portion as a mask. Positioning each electrode member of a predetermined size on the substrate in the hole, and melting each of the electrode members and fixing them on the substrate,
And a step of forming a protruding electrode by partially protruding from the through hole of the heat radiating portion, the method of manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13821495A JPH08330471A (en) | 1995-06-05 | 1995-06-05 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13821495A JPH08330471A (en) | 1995-06-05 | 1995-06-05 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08330471A true JPH08330471A (en) | 1996-12-13 |
Family
ID=15216757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13821495A Withdrawn JPH08330471A (en) | 1995-06-05 | 1995-06-05 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08330471A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09153565A (en) * | 1995-11-25 | 1997-06-10 | Samsung Electron Co Ltd | Ball grid array package with heat sink |
| KR19990012706A (en) * | 1997-07-30 | 1999-02-25 | 이대원 | Semiconductor package and manufacturing method |
| CN112071821A (en) * | 2019-06-10 | 2020-12-11 | 恒劲科技股份有限公司 | Semiconductor package substrate, manufacturing method thereof and electronic package |
-
1995
- 1995-06-05 JP JP13821495A patent/JPH08330471A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09153565A (en) * | 1995-11-25 | 1997-06-10 | Samsung Electron Co Ltd | Ball grid array package with heat sink |
| KR19990012706A (en) * | 1997-07-30 | 1999-02-25 | 이대원 | Semiconductor package and manufacturing method |
| CN112071821A (en) * | 2019-06-10 | 2020-12-11 | 恒劲科技股份有限公司 | Semiconductor package substrate, manufacturing method thereof and electronic package |
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