KR100836657B1 - Electronic package and manufacturing method thereof - Google Patents

Electronic package and manufacturing method thereof Download PDF

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Publication number
KR100836657B1
KR100836657B1 KR1020070018221A KR20070018221A KR100836657B1 KR 100836657 B1 KR100836657 B1 KR 100836657B1 KR 1020070018221 A KR1020070018221 A KR 1020070018221A KR 20070018221 A KR20070018221 A KR 20070018221A KR 100836657 B1 KR100836657 B1 KR 100836657B1
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South Korea
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chip
build
layer
insulating material
electrical contact
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KR1020070018221A
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Korean (ko)
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백종환
이성
도재천
박승욱
강준석
김선경
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삼성전기주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

An electronic package and a manufacturing method thereof are provided to realize an SIP(system in package) by configuring a COC package and applying a build-up technology to the COC package to realize electrical connection. An other side plane of a first chip including an electric contact point at the one side plane is attached to a heat spreader(100). The other side plane of the second chip having the electric contact point at the one side plane is attached with the one side plane of the first chip, thus the second chip is stacked on the first chip(110). The first and the second chips are encapsulated by coating the heat spreader with an insulating member(120). A first via which is connected with the electric contact points is processed by punching the insulating member(130).

Description

전자 패키지 및 그 제조방법{Electronic package and manufacturing method thereof}Electronic package and manufacturing method thereof

도 1은 종래기술에 따른 빌드업 기술이 적용된 전자 패키지를 나타낸 단면도.1 is a cross-sectional view showing an electronic package to which the build-up technique according to the prior art is applied.

도 2는 종래기술에 따른 빌드업 기술이 적용된 전자 패키지를 나타낸 개념도.2 is a conceptual diagram illustrating an electronic package to which a buildup technique according to the related art is applied.

도 3은 본 발명의 바람직한 일 실시예에 따른 전자 패키지 제조방법을 나타낸 순서도.3 is a flow chart showing a method of manufacturing an electronic package according to an embodiment of the present invention.

도 4는 본 발명의 바람직한 일 실시예에 따른 전자 패키지 제조공정을 나타낸 흐름도.4 is a flowchart illustrating a process of manufacturing an electronic package according to an embodiment of the present invention.

도 5는 본 발명의 바람직한 일 실시예에 따른 전자 패키지를 나타낸 단면도.5 is a cross-sectional view showing an electronic package according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

10 : 방열판 11 : 접착제10: heat sink 11: adhesive

12 : 제1 칩 13a, 13b : 전기접점12: first chip 13a, 13b: electrical contact

14 : 제2 칩 15 : 제1 비아14 second chip 15 first via

15a : 제1 비아홀 15b : 제1 관통부15a: first via hole 15b: first through part

15c : 제1 랜드부 16 : 제2 비아15c: first land portion 16: second via

16a : 제2 비아홀 16b : 제2 관통부16a: second via hole 16b: second through part

16c : 제2 랜드부 20 : 절연재16c: second land portion 20: insulating material

30, 30a, 30b, 30c : 빌드업층 32 : 범프30, 30a, 30b, 30c: buildup layer 32: bump

본 발명은 전자 패키지 및 그 제조방법에 관한 것이다.The present invention relates to an electronic package and a method of manufacturing the same.

전자 패키지는 전자제품에서 사용되는 디바이스를 효율적으로 포장하는 기술로서, 낱개로 잘려진 반도체 칩을 기판(substrate)에 접착하고 전기적으로 연결하여 모듈화하는 칩 패키징(chip packaging) 기술을 포함하며, 초기의 삽입형 패키지 기술에서, 크기가 작고 전기적 성능이 우수한 표면실장용 패키지 기술을 거쳐, 최근에는 고밀도 실장기술, 주변 실장기술을 적용하여 BGA(Ball Grid Array), CSP(Chip Scale Package)와 같은 면실장 형태의 미소, 경량화 추세로 급속하게 발전하고 있다.Electronic packaging is a technology for efficiently packaging devices used in electronic products, and includes chip packaging technology that bonds and cuts semiconductor chips into substrates and electrically connects them. In package technology, through small size and excellent surface mount package technology, recently high density package technology and peripheral package technology are applied to surface mount type such as ball grid array (BGA) and chip scale package (CSP). It is rapidly developing into a smile and light weight trend.

현재의 CSP(Chip Scale Package)에는 플립칩(Flip chip) 공법이 적용되어, 칩 간 또는 칩과 기판 간의 전기적 연결을 위해 범프볼(Bump Ball) 기술이 필수적으로 사용되고 있다. 이러한 범프볼(Bump ball) 기술은 칩패드(chip pad)와의 연결부에서 열응력 등으로 인한 피로 균열(solder fatigue failure)이 발생하여 신뢰도에 문제가 있으며, 범프볼의 미세화의 한계로 인하여 패키지의 I/O 수가 제한된다는 문제가 야기되는 실정이다.The current Chip Scale Package (CSP) is a flip chip method, and the bump ball technology is essentially used for electrical connection between chips or between a chip and a substrate. The bump ball technology has a problem of reliability due to the occurrence of solder fatigue failure due to thermal stress at the connection with the chip pad, and the I of the package due to the limitation of the miniaturization of the bump ball. The problem is that the number of / O is limited.

이러한 범프볼 기술이 적용되는 플립칩 공법은 전술한 신뢰도 문제를 보완하기 위해 언더필(under fill) 공정이 추가되어야 하므로 전체적으로 공정이 복잡하고 비용(cost)이 상승한다는 추가적인 문제를 발생시키게 된다.The flip chip method to which the bump ball technology is applied generates an additional problem that the overall process is complicated and costs are increased because an underfill process must be added to supplement the reliability problem described above.

이러한 문제를 보완하기 위해 도 1 및 도 2에 도시된 것과 같이 칩(chip) 상부의 전기접점 패턴(pattern)으로부터 금속(metal)층을 빌드업(build-up)해 나가는 이른바 '빌드업 기술'이 개발되었다. 그러나, 빌드업 기술의 경우에도 SIP(System In Package) 등의 패키지 구조를 형성하는 과정에서 패키지의 전제 사이즈가 커지게 된다는 문제를 안고 있다. 즉, 복수의 칩(multi Chip)을 사용하는 패키지의 경우에는 각각의 칩을 수평 정렬(horizontal array) 방식으로 실장해야 하므로 전체 세트(set)상의 패턴 사이즈를 최소화하기가 곤란하게 된다.In order to solve this problem, a so-called 'build-up technology' that builds up a metal layer from an electrical contact pattern on a chip as shown in FIGS. 1 and 2 is shown. This was developed. However, even in the case of the build-up technology, there is a problem that the overall size of the package becomes large in the process of forming a package structure such as SIP (System In Package). That is, in the case of a package using a plurality of chips, it is difficult to minimize the pattern size on the entire set because each chip must be mounted in a horizontal array method.

본 발명은 복수의 칩이 적층되는 COC(chip on chip) 패키지에 빌드업 기술을 적용한 하이엔드(high end) 마이크로 프로세서용 전자 패키지 및 그 제조방법을 제공하는 것이다.The present invention provides an electronic package for a high end microprocessor and a method of manufacturing the same, in which a build-up technology is applied to a chip on chip (COC) package in which a plurality of chips are stacked.

본 발명의 일 측면에 따르면, 일면에 전기접점이 형성된 제1 칩(chip)의 타면을 방열판(Heat spreader)에 어태칭(attaching)하는 단계, 일면에 전기접점이 형성된 제2 칩의 타면을 제1 칩의 일면에 어태칭하여 제2 칩을 제1 칩에 스택(stack) 하는 단계, 방열판에 절연재를 코팅하여 제1 칩 및 제2 칩을 인캡슐레이팅(encapsulating)하는 단계, 및 절연재를 천공하여 전기접점과 전기적으로 연결되는 제1 비아(via)를 가공하는 단계를 포함하는 전자 패키지 제조방법이 제공된다.According to an aspect of the present invention, attaching the other surface of the first chip (electric contact) formed on one surface to a heat spreader (Heat spreader), the other surface of the second chip formed an electrical contact on one surface Stacking a second chip on the first chip by attaching to one surface of the first chip, encapsulating the first chip and the second chip by coating an insulating material on a heat sink, and perforating the insulating material A method of manufacturing an electronic package is provided that includes processing a first via electrically connected to an electrical contact.

가공단계 이후에, 절연재에 빌드업(build-up)층을 적층하고 빌드업층을 천공하여 제1 비아와 전기적으로 연결되는 제2 비아를 가공하는 빌드업 단계를 더 포함할 수 있다. 빌드업층은 복수로 적층되고, 제2 비아는 복수의 빌드업층에 각각 가공될 수 있다.After the processing step, a build-up step of stacking a build-up layer on the insulating material and drilling the build-up layer may further include a build-up step of processing a second via electrically connected to the first via. The buildup layer may be stacked in plural, and the second via may be processed in the plurality of buildup layers, respectively.

빌드업 단계 이후에, 빌드업층의 표면에 제2 비아와 전기적으로 연결되는 도전성 범프(bump)를 형성하는 단계를 더 포함할 수 있다. 절연재와 빌드업층은 동일한 재질로 이루어지는 것이 바람직하다.After the buildup step, the method may further include forming a conductive bump electrically connected to the second via on the surface of the buildup layer. It is preferable that an insulation material and a buildup layer consist of the same material.

어태칭 단계는, 제1 칩과 방열판 사이에 접착제(adhesive)를 개재시켜 제1 칩을 방열판에 접착시키는 단계를 포함할 수 있으며, 스택 단계는, 제2 칩과 제1 칩 사이에 접착제를 개재시켜 제2 칩을 제1 칩에 접착시키는 단계를 포함할 수 있다.The attaching step may include attaching the first chip to the heat sink by interposing an adhesive between the first chip and the heat sink, and the stacking step may include interposing an adhesive between the second chip and the first chip. And adhering the second chip to the first chip.

인캡슐레이팅 단계는, 제1 칩 및 제2 칩을 커버하도록 방열판에 액상의 수지를 도포하고 소성(curing)시키는 단계를 포함할 수 있다.The encapsulating step may include applying a liquid resin to the heat sink to cover the first chip and the second chip and firing the liquid.

가공단계는, 전기접점이 노출되도록 절연재를 드릴링(drilling)하여 비아홀(via hole)을 천공하는 단계, 및 비아홀의 표면을 도금(plating)하여 제1 비아를 형성하는 단계를 포함할 수 있다.The machining step may include drilling a via hole by drilling an insulating material to expose the electrical contact, and plating a surface of the via hole to form a first via.

또한, 본 발명의 다른 측면에 따르면, 방열판(Heat spreader)과, 일면이 방 열판에 접합되고, 타면에 전기접점이 형성된 제1 칩(chip)과, 일면이 제1 칩에 접합되고, 타면에 전기접점이 형성된 제2 칩과, 방열판에 적층되며, 제1 칩 및 제2 칩을 인캡슐레이팅(encapsulating)하는 절연재와, 절연재의 표면에 형성되는 제1 랜드부와 절연재에 삽입되어 제1 랜드부와 전기접점을 전기적으로 연결하는 제1 관통부로 이루어지는 제1 비아(via)를 포함하는 전자 패키지가 제공된다.In addition, according to another aspect of the invention, the heat spreader (Heat spreader), one side is bonded to the heat dissipation plate, the first chip (chip) having an electrical contact on the other side, and one side is bonded to the first chip, the other side A second chip formed with an electrical contact, an insulating material stacked on a heat sink and encapsulating the first chip and the second chip, a first land portion formed on the surface of the insulating material, and a first land inserted into the insulating material An electronic package is provided that includes a first via made of a first through portion electrically connecting a portion and an electrical contact.

한편, 절연재에 적층되는 빌드업(build-up)층과, 빌드업층을 관통하여 제1 비아와 전기적으로 연결되는 제2 비아를 더 포함할 수 있다. 빌드업층은 복수로 적층되고, 제2 비아는 복수의 빌드업층에 각각 가공되어 서로 전기적으로 연결되도록 복수로 형성될 수 있다.On the other hand, it may further include a build-up layer laminated on the insulating material, and a second via electrically connected to the first via through the build-up layer. The buildup layer may be stacked in plural, and the second via may be formed in plural to be processed in the plurality of buildup layers and electrically connected to each other.

복수의 제2 비아는 서로 이격되어 복수의 빌드업층을 각각 관통하는 복수의 제2 관통부와, 복수의 빌드업층의 표면에 각각 형성되어 제2 관통부와 전기적으로 연결되는 복수의 제2 랜드부를 포함할 수 있다.The plurality of second vias are spaced apart from each other, and the plurality of second through portions penetrating the plurality of build up layers, respectively, and the plurality of second land portions formed on the surfaces of the plurality of build up layers, respectively, and electrically connected to the second through portions. It may include.

빌드업층의 표면에 형성되어 제2 비아와 전기적으로 연결되는 도전성 범프(bump)를 더 포함할 수 있다. 절연재와 빌드업층은 동일한 재질로 이루어질 수 있다.The semiconductor device may further include a conductive bump formed on the surface of the build-up layer and electrically connected to the second via. The insulating material and the buildup layer may be made of the same material.

제1 관통부는, 전기접점이 노출되도록 절연재를 드릴링(drilling)하여 비아홀(via hole)을 형성하고, 비아홀의 표면을 도금(plating)함으로써 형성될 수 있다.The first through part may be formed by drilling an insulating material to expose an electrical contact to form a via hole, and plating a surface of the via hole.

전술한 것 외의 다른 측면, 특징, 잇점이 이하의 도면, 특허청구범위 및 발명의 상세한 설명으로부터 명확해질 것이다.Other aspects, features, and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

이하, 본 발명에 따른 전자 패키지 및 그 제조방법의 바람직한 실시예를 첨부도면을 참조하여 상세히 설명하기로 하며, 첨부 도면을 참조하여 설명함에 있어, 동일하거나 대응하는 구성 요소는 동일한 도면번호를 부여하고 이에 대한 중복되는 설명은 생략하기로 한다.Hereinafter, a preferred embodiment of an electronic package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings, in the description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals and Duplicate description thereof will be omitted.

도 3은 본 발명의 바람직한 일 실시예에 따른 전자 패키지 제조방법을 나타낸 순서도이고, 도 4는 본 발명의 바람직한 일 실시예에 따른 전자 패키지 제조공정을 나타낸 흐름도이다. 도 4를 참조하면, 방열판(10), 접착제(11), 제1 칩(12), 전기접점(13a, 13b), 제2 칩(14), 제1 비아(15), 제1 비아홀(15a), 제1 관통부(15b), 제1 랜드부(15c), 제2 비아(16), 제2 비아홀(16a), 제2 관통부(16b), 제2 랜드부(16c), 절연재(20), 빌드업층(30, 30a, 30b, 30c), 범프(32)가 도시되어 있다.3 is a flowchart illustrating a method of manufacturing an electronic package according to an exemplary embodiment of the present invention, and FIG. 4 is a flowchart illustrating a process of manufacturing an electronic package according to an exemplary embodiment of the present invention. Referring to FIG. 4, the heat sink 10, the adhesive 11, the first chip 12, the electrical contacts 13a and 13b, the second chip 14, the first via 15, and the first via hole 15a. ), The first through portion 15b, the first land portion 15c, the second via 16, the second via hole 16a, the second through portion 16b, the second land portion 16c, and the insulating material ( 20), build up layers 30, 30a, 30b, 30c and bump 32 are shown.

본 실시예는, 범프볼 대신 빌드업 기술을 적용하여 CSP(Chip Scale Package) 의 반도체 칩에 대한 전기적 연결의 신뢰성을 향상시키고, 복수의 칩이 내장되는 SIP(system in package) 구조에 동시적용이 가능한 이른바 'COC(chip on chip) 빌드업(build-up) SIP 구조'를 고안한 것으로, 방열판(10)상에 복수의 칩을 적층하고 빌드업 구조를 적용하여 칩과의 전기적 연결을 구현하여 패키지화한 것이다.This embodiment improves the reliability of electrical connection to a semiconductor chip of a chip scale package (CSP) by applying a build-up technology instead of bump balls, and simultaneously applies to a SIP (system in package) structure in which a plurality of chips are embedded. Invented a so-called 'chip on chip (COC) build-up SIP structure' as possible, by stacking a plurality of chips on the heat sink 10 and applying a build-up structure to implement electrical connection with the chip It's packaged.

즉, 본 실시예에 따라 전자 패키지를 제조하기 위해서는 먼저 방열판(10)상에 제1 칩(12)을 어태칭(attaching)한다(100). 어태칭 공정은 도 4의 (a)에 도시된 것처럼 접착제(11)를 개재시켜 칩을 방열판(10)에 접착시키는 공정으로 이루어진 다. 이로써, 저렴하고 신속하게 칩을 방열판(10)에 어태칭할 수 있게 된다.That is, in order to manufacture the electronic package according to the present embodiment, first attaching the first chip 12 onto the heat sink 10 (100). The attaching process is made of a process of adhering the chip to the heat sink 10 through the adhesive 11, as shown in Figure 4 (a). As a result, the chip can be attached to the heat sink 10 inexpensively and quickly.

제1 칩(12)의 한쪽 면에는 전기접점(13a)이 형성되어 있으며, 후술하는 것과 같이 빌드업 기술을 적용하여 전기접점(13a)에 대한 전기적 연결을 구현하기 위해 도 4의 (b)와 같이 전기접점(13a)이 형성된 면이 노출되도록, 즉 전기접점(13a)이 형성되지 않은 면을 방열판(10)에 접합한다.An electrical contact 13a is formed on one surface of the first chip 12, and as shown later in FIG. 4 (b) to implement electrical connection to the electrical contact 13a by applying a build-up technique. Likewise, the surface on which the electrical contact 13a is formed is exposed, that is, the surface on which the electrical contact 13a is not formed is bonded to the heat sink 10.

다음으로, 제2 칩(14)을 제1 칩(12)에 스택한다(110). 제2 칩(14)을 제1 칩(12)에 스택하는 공정도 도 4의 (c)에 도시된 것처럼 접착제(11)를 개재시켜 칩과 칩을 접착시키는 공정으로 이루어진다. 제2 칩(14)도 제1 칩(12)과 마찬가지로 한쪽 면에 전기접점(13b)이 형성되어 있으며, 빌드업 기술을 적용하기 위해 도 4의 (d)와 같이 전기접점(13b)이 형성된 면이 노출되도록, 즉 전기접점(13b)이 형성되지 않은 면을 제1 칩(12)에 접합하여 적층한다.Next, the second chip 14 is stacked on the first chip 12 (110). The process of stacking the second chip 14 on the first chip 12 also includes a process of adhering the chip to the chip via the adhesive 11 as shown in FIG. Like the first chip 12, the second chip 14 also has an electrical contact 13b formed on one surface thereof, and the electrical contact 13b is formed as shown in FIG. The surface where the surface is exposed, that is, the surface on which the electrical contact 13b is not formed is bonded to the first chip 12 and laminated.

제1 칩(12)에 제2 칩(14)이 스택된 상태에서 방열판(10)에 절연재(20)를 코팅하여 적층된 칩들을 절연재(20) 내에 수용시켜 커버하는 인캡슐레이팅(encapsulating) 공정을 진행한다(120). 본 실시예에서는 2개의 칩이 스택된 상태를 예로 들어 설명하였으나, 패키지의 설계에 따라서는 3개 이상의 칩을 적층하여 인캡슐레이팅할 수도 있음은 물론이다.Encapsulating process of coating the insulating material 20 on the heat sink 10 in the state in which the second chip 14 is stacked on the first chip 12 to accommodate the stacked chips in the insulating material 20 to cover the encapsulating process. Proceed to (120). In the present exemplary embodiment, two chips are stacked in an example, but according to a package design, three or more chips may be stacked and encapsulated.

인캡슐레이팅 공정은 도 4의 (e)와 같이 방열판(10) 상에 액상의 PI(polyimide) 레진(resin)을 도포하여 적층된 칩을 커버하고 이를 소성시키는 공정으로 진행될 수 있다.The encapsulating process may be performed by applying a liquid polyimide (PI) resin (resin) on the heat sink 10 to cover the stacked chips and firing them, as shown in FIG.

절연재(20)가 경화된 후에는 빌드업 기술을 적용하여 칩(12, 14)의 전기접 점(13a, 13b)의 위치에 상응하는 제1 비아(15)를 가공한다(130). 제1 비아(15)의 가공은 도 4의 (f)와 같이 전기접점(13a, 13b)이 노출되도록 레이저(laser) 드릴 등을 사용하여 절연재(20)를 천공하고(132), 도 4의 (g)와 같이 제1 비아홀(15a)의 표면에 Cu 스퍼터링(sputtering), 도전성 페이스트 충전 등의 공정을 적용하여 도금층이 형성되도록 한다(134). 이로써, 내장된 칩(12, 14)의 전기접점(13a, 13b)이 외부와 전기적으로 연결될 수 있게 된다. 비아홀의 천공에 사용되는 드릴링 공정 및 비아홀을 전기적으로 도통시키기 위한 도금 공정이 전술한 실시예에 한정되지 않음은 물론이다.After the insulating material 20 is cured, the build-up technique is applied to process the first via 15 corresponding to the positions of the electrical contacts 13a and 13b of the chips 12 and 14 (130). The processing of the first via 15 is performed by drilling the insulating material 20 using a laser drill or the like so as to expose the electrical contacts 13a and 13b as shown in FIG. As shown in (g), a plating layer is formed on the surface of the first via hole 15a by applying a process such as Cu sputtering or conductive paste filling (134). As a result, the electrical contacts 13a and 13b of the embedded chips 12 and 14 may be electrically connected to the outside. Of course, the drilling process used for drilling the via hole and the plating process for electrically conducting the via hole are not limited to the above-described embodiment.

도 4의 (g)에 도시된 것처럼 절연재(20)에 제1 비아홀(15a)을 천공하고 그 표면을 도금하여 제1 비아(15)를 형성할 경우, 제1 비아(15)는 절연재(20)를 관통하여 칩(12, 14)의 전기접점(13a, 13b)과 전기적 연결통로를 이루는 부분과, 그에 연결되어 절연재(20)의 표면에 일부 적층되는 부분으로 이루어지며, 이하 전자를 관통부, 후자를 랜드부로 명명하여 설명한다. 즉, 제1 비아(15)는 제1 비아홀(15a), 제1 관통부(15b), 제1 랜드부(15c)로 이루어진다.As shown in FIG. 4G, when the first via hole 15a is drilled in the insulating material 20 and the surface thereof is plated to form the first via 15, the first via 15 is the insulating material 20. ), And a portion of the chip 12 and 14 that forms an electrical connection path with the electrical contacts 13a and 13b, and a portion that is connected to and partially stacked on the surface of the insulating material 20. The latter is named and described as land part. That is, the first via 15 includes the first via hole 15a, the first through part 15b, and the first land part 15c.

다음으로, 필요에 따라 빌드업 공정을 계속 진행하여 반도체 칩과의 전기적 연결통로를 형성한다. 빌드업층(30)의 적층 횟수 및 비아홀의 가공은 전자 패키지의 설계에 따라 달라질 수 있다. 도 4는 총 3개의 빌드업층(30)을 적층하고 솔더볼 범프를 결합한 사례를 도시한 것이다.Next, if necessary, the build-up process is continued to form an electrical connection path with the semiconductor chip. The number of stacks of the build-up layer 30 and the processing of the via holes may vary depending on the design of the electronic package. 4 illustrates a case in which a total of three buildup layers 30 are stacked and solder ball bumps are combined.

즉, 도 4의 (h)와 같이 절연재(20)에 첫번째 빌드업층(30a)을 적층한다. 빌드업층(30a)은 절연성 재질로 이루어지며, 절연재(20)와 동일한 재료인 액상 PI를 도포하여 경화시키거나, PI 필름을 적층하여 구현할 수 있다.That is, as shown in FIG. 4H, the first build-up layer 30a is laminated on the insulating material 20. The build-up layer 30a may be made of an insulating material, and may be formed by applying liquid PI, which is the same material as the insulating material 20, to be cured, or by stacking PI films.

빌드업층(30)을 절연재(20)와 동일한 재료로 할 경우에는 칩의 인캡슐레이팅 공정과 빌드업층(30)의 적층 공정, 즉 빌드업 공정을 동일한 프로세스로 할 수 있어 가공성이 우수하고 비용이 저렴하며, 칩에서 발생하는 열로 인한 전자 패키지의 수축, 팽창이 절연재(20)와 빌드업층(30)에서 다르지 않기 때문에 열응력에 의한 에러를 방지할 수 있다. 따라서, 본 실시예에 따른 절연재(20) 및 빌드업층(30)의 재질의 동일함은 같은 재료뿐만 아니라 가공성, 비용, 열에 의한 수축, 팽창 정도 등에 있어서 같은 성질을 갖는 '동종의 재료'를 포함하는 개념이다.When the buildup layer 30 is made of the same material as the insulating material 20, the encapsulation process of the chip and the stacking process of the buildup layer 30, that is, the buildup process, can be performed in the same process. Since it is inexpensive, shrinkage and expansion of the electronic package due to heat generated from the chip are not different in the insulating material 20 and the buildup layer 30, thereby preventing errors due to thermal stress. Therefore, the same material of the insulating material 20 and the build-up layer 30 according to the present embodiment includes not only the same material but also the same material having the same properties in processability, cost, heat shrinkage, expansion degree, and the like. It is a concept.

다음으로 도 4의 (i)와 같이 제1 비아(15)의 위치에서 첫번째 빌드업층(30a)을 드릴링하여 제2 비아홀(16a)을 천공하고, 도 4의 (j)와 같이 제2 비아홀(16a)의 내면을 도금하여 제2 비아(16)를 형성한다(140). 제2 비아(16)도 제1 비아(15)와 마찬가지로 제2 비아홀(16a), 제2 랜드부(16c), 제2 관통부(16b)로 이루어지며, 도 4의 (j)에 도시된 것처럼 제1 랜드부(15c)가 노출되도록 제2 비아홀(16a)을 천공함으로써 제2 관통부(16b)가 제1 랜드부(15c)와 전기적으로 연결된다. 이로써, 반도체 칩(12, 14)의 전기접점(13a, 13b)으로부터의 전기적 연결통로가 구현된다.Next, as shown in FIG. 4 (i), the first build-up layer 30a is drilled at the position of the first via 15 to drill the second via hole 16a, and as shown in FIG. 4 (j), the second via hole ( An inner surface of 16a is plated to form second via 16 (140). Similarly to the first via 15, the second via 16 also includes a second via hole 16a, a second land portion 16c, and a second through portion 16b, as shown in FIG. 4J. As described above, the second through part 16b is electrically connected to the first land part 15c by drilling the second via hole 16a to expose the first land part 15c. As a result, electrical connection paths from the electrical contacts 13a and 13b of the semiconductor chips 12 and 14 are realized.

도 4는 3개의 빌드업층(30)을 적층하는 빌드업 공정의 예로서, 첫번째 빌드업 공정을 3회 반복한다. 즉, 도 4의 (k)와 같이 두번째 빌드업층(30b)을 적층하고, 도 4의 (l)과 같이 첫번째 빌드업층(30a)의 제2 비아(16)의 위치에서 제2 비아홀(16a)을 천공한 후, 도 4의 (m)과 같이 천공된 제2 비아홀(16a)을 도금하여 제2 비아(16)가 두번째 빌드업층(30b)까지 더 연결되도록 한다.4 is an example of a buildup process in which three buildup layers 30 are stacked, and the first buildup process is repeated three times. That is, the second buildup layer 30b is stacked as shown in FIG. 4 (k), and the second via hole 16a is positioned at the position of the second via 16 of the first buildup layer 30a as shown in FIG. After drilling, the perforated second via hole 16a is plated as shown in FIG. 4 (m) so that the second via 16 is further connected to the second buildup layer 30b.

이러한 공정을 세번째 빌드업층(30c)의 경우에도 반복하여, 도 4의 (n)과 같이 세번째 빌드업층(30c)을 적층하고, 도 4의 (o)와 같이 두번째 빌드업층(30b)의 제2 비아(16)의 위치에서 제2 비아홀(16a)을 천공한 후, 도 4의 (p)와 같이 천공된 제2 비아홀(16a)을 도금하여 제2 비아(16)가 세번째 빌드업층(30c)까지 더 연결되도록 한다.This process is repeated for the third buildup layer 30c, and the third buildup layer 30c is laminated as shown in FIG. 4 (n), and the second buildup layer 30b as shown in FIG. After drilling the second via hole 16a at the position of the via 16, the second via hole 16a is plated as shown in FIG. 4 (p) so that the second via 16 forms the third build-up layer 30c. Until more connections are made.

전술한 것과 같이 빌드업 공정은 전자 패키지의 설계에 따라 필요한 횟수만큼 복수로 진행되며, 이에 따라 빌드업층(30)이 복수로 적층되고 각 빌드업층(30)에 제2 비아(16)가 가공되어 전기적 연결통로를 구현한다. 제2 비아(16)의 전기적 연결은 제1 비아(15)와의 전기적 연결과 마찬가지로 n번째 빌드업층의 제2 랜드부(16c)와 (n+1)번째 빌드업층의 제2 관통부(16b)가 서로 연결되도록 함으로써 구현된다.As described above, the build-up process is performed a plurality of times as necessary according to the design of the electronic package. Accordingly, a plurality of build-up layers 30 are stacked and a second via 16 is processed in each build-up layer 30. Implement electrical connection paths. The electrical connection of the second via 16 is similar to the electrical connection with the first via 15, the second land portion 16c of the nth buildup layer and the second through portion 16b of the (n + 1) th buildup layer. Is implemented by allowing the to be connected to each other.

빌드업 공정이 완료된 후에는 도 4의 (q)와 같이 빌드업층(30)의 표면에 형성된 제2 랜드부(16c)에 솔더볼(solder ball) 등의 도전성 범프를 결합하여 전자 패키지와 외부 장치와의 전기적 연결을 위한 접점을 형성한다(150).After the build-up process is completed, as shown in (q) of FIG. 4, a conductive bump such as a solder ball is coupled to the second land portion 16c formed on the surface of the build-up layer 30, thereby forming an electronic package and an external device. Form a contact for electrical connection of the 150 (150).

도 5는 본 발명의 바람직한 일 실시예에 따른 전자 패키지를 나타낸 단면도이다. 도 5를 참조하면, 방열판(10), 접착제(11), 제1 칩(12), 전기접점(13a, 13b), 제2 칩(14), 제1 비아(15), 제1 관통부(15b), 제1 랜드부(15c), 제2 비아(16), 제2 관통부(16b), 제2 랜드부(16c), 절연재(20), 빌드업층(30), 범프(32)가 도시되어 있다.5 is a cross-sectional view illustrating an electronic package according to an exemplary embodiment of the present invention. Referring to FIG. 5, the heat sink 10, the adhesive 11, the first chip 12, the electrical contacts 13a and 13b, the second chip 14, the first via 15, and the first through portion ( 15b), the first land portion 15c, the second via 16, the second through portion 16b, the second land portion 16c, the insulating material 20, the buildup layer 30, and the bump 32 Is shown.

본 실시예에 따른 전자 패키지는 반도체 칩의 하부에 방열판(Heat spreader)(10)이 부착되어 있어 칩으로부터 발생되는 열을 보다 효율적으로 방출시킬 수 있으며, 방열판(10)과 제1 칩(12)의 어태칭 및 제1 칩(12)에 제2 칩(14)을 스택하는 공정은 반도체 칩의 실장을 위한 복잡한 공정 대신 단순히 접착제(11)를 사용하여 칩을 접합하는 공정으로 수행될 수 있어 저렴하고 신속하게 진행될 수 있다.In the electronic package according to the present embodiment, a heat spreader 10 is attached to a lower portion of the semiconductor chip to more efficiently dissipate heat generated from the chip, and the heat sink 10 and the first chip 12 may be used. Attaching and stacking the second chip 14 on the first chip 12 may be performed by simply bonding the chip using the adhesive 11 instead of the complicated process for mounting the semiconductor chip. Can proceed quickly.

반도체 칩으로부터의 전기적 연결통로(electrical path)는 칩(12, 14)의 전기접점(13a, 13b)으로부터 빌드업 공정을 진행하여 구현되므로 보다 미세한 피치의 구현이 가능하다. 예를 들어, 종래의 범프볼 기술을 적용하여 100마이크로미터 정도의 피치를 구현한다고 할 때, 본 실시예에 따른 빌드업 기술을 적용하여 30마이크로미터 정도의 피치를 구현할 수 있어 미세 피치 구현 및 그로 인한 패키지의 소형화에 기여할 수 있다.Since the electrical path from the semiconductor chip is implemented through the build-up process from the electrical contacts 13a and 13b of the chips 12 and 14, a finer pitch can be realized. For example, when a pitch of about 100 micrometers is realized by applying a conventional bump ball technique, a pitch of about 30 micrometers may be realized by applying a build-up technique according to the present embodiment, thereby realizing fine pitch and This can contribute to the miniaturization of the package.

도 5에 도시된 것처럼, 본 실시예에 따른 전자 패키지는 방열판(10)에 제1 칩(12)과 제2 칩(14)이 순차적으로 적층되어 반도체 칩이 스택된 구조를 이루고 있어, 종래 빌드업 공법을 적용한 SIP에서 복수의 칩을 실장할 때 수평 정렬 방식으로 실장해야 함으로써 패턴 사이즈를 최소화하기 곤란하다는 문제를 극복할 수 있다.As shown in FIG. 5, the electronic package according to the present exemplary embodiment has a structure in which the first chip 12 and the second chip 14 are sequentially stacked on the heat sink 10 so that the semiconductor chips are stacked. When mounting a plurality of chips in SIP using the up method, it is necessary to mount in horizontal alignment to overcome the problem that it is difficult to minimize the pattern size.

방열판(10)은 전술한 바와 같이 반도체 칩으로부터 발생된 열을 효율적으로 방출하기 위한 것이며, 방열판(10)상에 제1 칩(12)을 어태칭하고 제1 칩(12)에 제2 칩(14)을 스택하는 공정은 접착제(11)를 사용함으로써 저렴하고 신속하게 진행할 수 있다. 방열판(10)상에 접합되는 제1 칩(12) 및 제2 칩(14)은 모두 전기접 점(13a, 13b)이 노출되도록 함으로써 빌드업 공정에 의한 전기적 연결통로 구현을 가능하게 한다.The heat sink 10 is for efficiently dissipating heat generated from the semiconductor chip as described above, attaching the first chip 12 on the heat sink 10 and the second chip 14 on the first chip 12. ) Process can be carried out cheaply and quickly by using the adhesive (11). Both the first chip 12 and the second chip 14 bonded on the heat sink 10 allow the electrical contacts 13a and 13b to be exposed, thereby enabling the electrical connection path by the build-up process.

방열판(10)상에 스택된 복수의 반도체 칩은 액상의 PI 레진(resin)을 도포하는 등 절연재(20)를 사용하여 인캡슐레이팅(encapsulating)한다. 반도체 칩의 몰딩은 EMC(Epoxy molding compound) 등 기존의 몰딩재로 인캡슐레이팅할 수도 있으며, 빌드업층(30)의 재질과 동일한 PI 레진 등을 사용하면 칩 인캡슐레이팅 공정과 빌드업 공정을 동일한 프로세스로 진행할 수 있어 공정이 단순하고, 재료 간의 물성차이로 인한 패키지의 에러를 방지할 수 있다.The plurality of semiconductor chips stacked on the heat sink 10 are encapsulated using the insulating material 20, for example, by applying a liquid PI resin. The molding of the semiconductor chip may be encapsulated with an existing molding material such as an epoxy molding compound (EMC). If the same PI resin is used as the material of the buildup layer 30, the chip encapsulation process and the buildup process may be identical. The process can be carried out in a simple process, and can prevent package errors due to material differences between materials.

제1 칩(12) 및 제2 칩(14)을 그 내부에 수용하여 인캡슐레이팅한 절연재(20)에는 제1 비아(15)가 관삽(貫揷)되어 제1 칩(12) 및 제2 칩(14)과의 전기적 연결통로를 구성한다. 제1 비아(15)는 절연재(20)의 표면에 형성되는 제1 랜드부(15c)와, 절연재(20)에 삽입되는 제1 관통부(15b)로 이루어지며, 도 4에서 설명한 바와 같이 제1 관통부(15b)는 전기접점(13a, 13b)이 노출되도록 절연재(20)를 드릴링하여 비아홀을 천공하고, 비아홀의 표면을 도금함으로써 형성된다. 이로써, 제1 비아(15)가 절연재(20)에 관삽된 형태로 칩과의 전기적 연결통로를 구현하게 된다.The first via 15 is inserted into the insulating material 20 encapsulated by accommodating the first chip 12 and the second chip 14 therein, so that the first chip 12 and the second chip 14 are inserted. An electrical connection path with the chip 14 is formed. The first via 15 is composed of a first land portion 15c formed on the surface of the insulating material 20 and a first through portion 15b inserted into the insulating material 20, as described with reference to FIG. 4. The first through part 15b is formed by drilling the insulating material 20 so that the electrical contacts 13a and 13b are exposed to drill the via hole and plating the surface of the via hole. As a result, the first via 15 is inserted into the insulating material 20 to implement an electrical connection path with the chip.

본 실시예에 따른 빌드업 공법을 적용하게 되면, 절연재(20)에는 빌드업층(30)이 하나 또는 복수로 적층되며, 빌드업층(30)에는 제1 비아(15)와 전기적으로 연결되는 제2 비아(16)가 관삽된다. 제2 비아(16)는 각 빌드업층(30)에 형성되어 반도체 칩(12, 14)의 전기접점(13a, 13b)으로부터의 전기적 연결통로를 형성하는 역할을 한다.When the build-up method according to the present embodiment is applied, one or more build-up layers 30 are stacked on the insulating material 20, and a second electrically connected to the first via 15 is formed on the build-up layer 30. Via 16 is inserted. The second via 16 is formed in each buildup layer 30 to form an electrical connection path from the electrical contacts 13a and 13b of the semiconductor chips 12 and 14.

제2 비아(16) 또한 제1 비아(15)와 마찬가지로 빌드업층(30)에 관삽된 제2 관통부(16b)와 빌드업층(30)의 표면에 적층된 제2 랜드부(16c)로 이루어지며, 각 빌드업층(30)에 형성되는 복수의 제2 비아(16)는 도 5에 도시된 것처럼, 어느 한 층의 제2 관통부(16b)와 그에 인접한 층의 제2 랜드부(16c)가 서로 전기적으로 연결되는 구조로 형성된다. 이는 전기접점(13a, 13b)으로부터의 전기적 통로를 구현하기 위해 빌드업 공정을 적용함에 따라 형성되는 구조로서, 반드시 관통부와 랜드부가 접하는 형태로 이루어져야 하는 것은 아니며, 필요에 따라서는, 관통부끼리 연통되도록 하는 이른바 '스택 비아(stack via)' 구조 또는 적층된 전체 빌드업층(30)을 관통하는 쓰루홀(through hole) 구조로 전기적 통로가 구현될 수 있음은 물론이다.Like the first via 15, the second via 16 also includes a second through portion 16b inserted into the buildup layer 30 and a second land portion 16c stacked on the surface of the buildup layer 30. As shown in FIG. 5, the plurality of second vias 16 formed in each build-up layer 30 may include the second through portion 16b of one layer and the second land portion 16c of the layer adjacent thereto. Are formed in a structure that is electrically connected to each other. This is a structure formed by applying a build-up process to implement the electrical passages from the electrical contacts 13a and 13b. The penetrating portion and the land portion do not necessarily have to be in contact with each other. It is a matter of course that the electrical passage may be implemented in a so-called 'stack via' structure that allows communication or a through hole structure that penetrates the entire stacked up build-up layer 30.

빌드업 공정이 완료된 후에는 전자 패키지를 외부 장치에 SMT(surface mount technology) 실장 등을 통해 연결하기 위해 빌드업층(30)의 표면에 솔더볼 등의 도전성 범프를 결합한다. 도전성 범프는 빌드업층(30)에 형성된 제2 비아(16)와 전기적으로 연결되어 전자 패키지와 외부 장치 간의 전기적 연결을 위한 접점을 이루게 된다.After the buildup process is completed, a conductive bump such as solder balls is coupled to the surface of the buildup layer 30 to connect the electronic package to an external device through surface mount technology (SMT) mounting. The conductive bumps are electrically connected to the second vias 16 formed in the buildup layer 30 to form contacts for electrical connection between the electronic package and the external device.

전술한 실시예 외의 많은 실시예들이 본 발명의 특허청구범위 내에 존재한다.Many embodiments other than the above-described embodiments are within the scope of the claims of the present invention.

상술한 바와 같이 본 발명의 바람직한 실시예에 따르면, 반도체 칩에 다른 칩을 더 적층(stack)하여 COC(chip on chip) 패키지를 구성하고, 여기에 빌드업 기술을 적용하여 반도체 칩과의 전기적 연결을 구현함으로써 고밀도 및 신뢰성이 우수한 SIP(system in package)을 실현할 수 있다.As described above, according to the preferred embodiment of the present invention, another chip is further stacked on the semiconductor chip to form a chip on chip (COC) package, and a build-up technique is applied thereto to electrically connect the semiconductor chip. The high density and reliability of SIP (system in package) can be realized.

Claims (16)

일면에 전기접점이 형성된 제1 칩(chip)의 타면을 방열판(Heat spreader)에 어태칭(attaching)하는 단계;Attaching the other surface of the first chip having an electrical contact formed on one surface to a heat spreader; 일면에 전기접점이 형성된 제2 칩의 타면을 상기 제1 칩의 일면에 어태칭하여 상기 제2 칩을 상기 제1 칩에 스택(stack)하는 단계;Stacking the second chip on the first chip by attaching the other surface of the second chip having an electrical contact formed on one surface to one surface of the first chip; 상기 방열판에 절연재를 코팅하여 상기 제1 칩 및 상기 제2 칩을 인캡슐레이팅(encapsulating)하는 단계; 및Coating an encapsulant on the heat sink to encapsulate the first chip and the second chip; And 상기 절연재를 천공하여 상기 전기접점과 전기적으로 연결되는 제1 비아(via)를 가공하는 단계를 포함하는 전자 패키지 제조방법.Perforating the insulating material to process a first via electrically connected to the electrical contact. 제1항에 있어서,The method of claim 1, 상기 가공단계 이후에,After the processing step, 상기 절연재에 빌드업(build-up)층을 적층하고 상기 빌드업층을 천공하여 상기 제1 비아와 전기적으로 연결되는 제2 비아를 가공하는 빌드업 단계를 더 포함하는 전자 패키지 제조방법.Stacking a build-up layer on the insulating material and drilling the build-up layer to process a second via electrically connected to the first via. 제2항에 있어서,The method of claim 2, 상기 빌드업층은 복수로 적층되고, 상기 제2 비아는 복수의 상기 빌드업층에 각각 가공되는 것을 특징으로 하는 전자 패키지 제조방법.The build-up layer is stacked in plural, the second via is a method for manufacturing an electronic package, characterized in that each of the plurality of build-up layer is processed. 제2항에 있어서,The method of claim 2, 상기 빌드업 단계 이후에,After the buildup phase above, 상기 빌드업층의 표면에 상기 제2 비아와 전기적으로 연결되는 도전성 범프(bump)를 형성하는 단계를 더 포함하는 전자 패키지 제조방법.And forming a conductive bump electrically connected to the second via on the surface of the build-up layer. 제2항에 있어서,The method of claim 2, 상기 절연재와 상기 빌드업층은 동일한 재질로 이루어진 것을 특징으로 하는 전자 패키지 제조방법.The insulating material and the build-up layer is an electronic package manufacturing method, characterized in that made of the same material. 제1항에 있어서,The method of claim 1, 상기 어태칭 단계는, 상기 제1 칩과 상기 방열판 사이에 접착제(adhesive)를 개재시켜 상기 제1 칩을 상기 방열판에 접착시키는 단계를 포함하는 것을 특징으로 하는 전자 패키지 제조방법.The attaching step includes the step of adhering the first chip to the heat sink through the adhesive (adhesive) between the first chip and the heat sink. 제1항에 있어서,The method of claim 1, 상기 스택 단계는, 상기 제2 칩과 상기 제1 칩 사이에 접착제를 개재시켜 상기 제2 칩을 상기 제1 칩에 접착시키는 단계를 포함하는 것을 특징으로 하는 전자 패키지 제조방법.The stacking step includes attaching the second chip to the first chip through an adhesive between the second chip and the first chip. 제1항에 있어서,The method of claim 1, 상기 인캡슐레이팅 단계는, 상기 제1 칩 및 상기 제2 칩을 커버하도록 상기 방열판에 액상의 수지를 도포하고 소성(curing)시키는 단계를 포함하는 것을 특징으로 하는 전자 패키지 제조방법.The encapsulating step includes applying a liquid resin to the heat sink to cover the first chip and the second chip and baking the liquid. 제1항에 있어서,The method of claim 1, 상기 가공단계는,The processing step, 상기 전기접점이 노출되도록 상기 절연재를 드릴링(drilling)하여 비아홀(via hole)을 천공하는 단계; 및Drilling through the insulating material to expose the electrical contact to drill a via hole; And 상기 비아홀의 표면을 도금(plating)하여 상기 제1 비아를 형성하는 단계를 포함하는 것을 특징으로 하는 전자 패키지 제조방법.And plating the surface of the via hole to form the first via. 방열판(Heat spreader)과;A heat spreader; 일면이 상기 방열판에 접합되고, 타면에 전기접점이 형성된 제1 칩(chip)과;A first chip having one surface bonded to the heat sink and an electrical contact formed at the other surface; 일면이 상기 제1 칩에 접합되고, 타면에 전기접점이 형성된 제2 칩과;A second chip having one surface bonded to the first chip and having an electrical contact formed on the other surface thereof; 상기 방열판에 적층되며, 상기 제1 칩 및 상기 제2 칩을 인캡슐레이팅(encapsulating)하는 절연재와;An insulating material stacked on the heat sink and encapsulating the first chip and the second chip; 상기 절연재의 표면에 형성되는 제1 랜드부와 상기 절연재에 삽입되어 상기 제1 랜드부와 상기 전기접점을 전기적으로 연결하는 제1 관통부로 이루어지는 제1 비아(via)와;A first via formed of a first land portion formed on the surface of the insulating material and a first through portion inserted into the insulating material to electrically connect the first land portion and the electrical contact; 상기 절연재에 적층되는 빌드업(build-up)층과;A build-up layer laminated on the insulating material; 상기 빌드업층을 관통하여 상기 제1 비아와 전기적으로 연결되는 제2 비아를 포함하는 전자 패키지.An electronic package including a second via penetrating the build-up layer and electrically connected to the first via. 삭제delete 제10항에 있어서,The method of claim 10, 상기 빌드업층은 복수로 적층되고, 상기 제2 비아는 복수의 상기 빌드업층에 각각 가공되어 서로 전기적으로 연결되도록 복수로 형성되는 것을 특징으로 하는 전자 패키지.The build-up layer is stacked in plural, the second via is a plurality of electronic packages, characterized in that formed in plurality to be processed in each of the build-up layer and electrically connected to each other. 제12항에 있어서,The method of claim 12, 복수의 상기 제2 비아는 서로 이격되어 복수의 상기 빌드업층을 각각 관통하는 복수의 제2 관통부와, 복수의 상기 빌드업층의 표면에 각각 형성되어 상기 제2 관통부와 전기적으로 연결되는 복수의 제2 랜드부를 포함하는 것을 특징으로 하는 전자 패키지.The plurality of second vias may be spaced apart from each other, and the plurality of second through portions may respectively penetrate the plurality of buildup layers, and the plurality of second vias may be formed on surfaces of the plurality of buildup layers, respectively. And an second land portion. 제10항에 있어서,The method of claim 10, 상기 빌드업층의 표면에 형성되어 상기 제2 비아와 전기적으로 연결되는 도전성 범프(bump)를 더 포함하는 전자 패키지.And a conductive bump formed on a surface of the build-up layer and electrically connected to the second via. 제10항에 있어서,The method of claim 10, 상기 절연재와 상기 빌드업층은 동일한 재질로 이루어진 것을 특징으로 하는 전자 패키지.The insulating material and the build-up layer is an electronic package, characterized in that made of the same material. 제10항에 있어서,The method of claim 10, 상기 제1 관통부는, 상기 전기접점이 노출되도록 상기 절연재를 드릴링(drilling)하여 비아홀(via hole)을 형성하고, 상기 비아홀의 표면을 도금(plating)함으로써 형성되는 것을 특징으로 하는 전자 패키지.And the first through part is formed by drilling the insulating material to expose the electrical contact to form a via hole, and plating a surface of the via hole.
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JP2002334968A (en) * 2001-05-07 2002-11-22 Sony Corp Three-dimensional semiconductor chip

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002334968A (en) * 2001-05-07 2002-11-22 Sony Corp Three-dimensional semiconductor chip

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