TW201611213A - 封裝結構及其製法 - Google Patents

封裝結構及其製法 Download PDF

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Publication number
TW201611213A
TW201611213A TW103130350A TW103130350A TW201611213A TW 201611213 A TW201611213 A TW 201611213A TW 103130350 A TW103130350 A TW 103130350A TW 103130350 A TW103130350 A TW 103130350A TW 201611213 A TW201611213 A TW 201611213A
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Taiwan
Prior art keywords
carrier
package structure
electronic component
disposed
insulating layer
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TW103130350A
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English (en)
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TWI566348B (zh
Inventor
蔣靜雯
陳光欣
陳賢文
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW103130350A priority Critical patent/TWI566348B/zh
Priority to CN201410538088.2A priority patent/CN105575915A/zh
Priority to US14/610,910 priority patent/US10249562B2/en
Publication of TW201611213A publication Critical patent/TW201611213A/zh
Application granted granted Critical
Publication of TWI566348B publication Critical patent/TWI566348B/zh

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Abstract

一種封裝結構之製法，提供一具有凹槽之承載件，再設置電子元件於該凹槽中，並以絕緣層包覆該電子元件，之後形成線路部於該承載件上方以電性連接該電子元件，接著形成複數貫穿該承載件之穿孔，再形成導電材於該穿孔中以作為電性連接該線路部之導電體，故藉由該承載件作為基板本體，以避免發生翹曲的現象。本發明復提供該封裝結構。

Description

封裝結構及其製法
本發明係有關一種封裝結構，尤指一種具電子元件之封裝結構及其製法。
隨著電子產業的發達，現今的電子產品已趨向輕薄短小與功能多樣化的方向設計，半導體封裝技術亦隨之開發出不同的封裝型態。為滿足半導體裝置之高積集度(Integration)、微型化(Miniaturization)以及高電路效能等需求，使封裝堆疊(Package On Package，簡稱POP)技術越趨於成熟，遂而發展出三維積體電路(3 Dimension Integrated Circuit)之堆疊技術。
第1A至1G圖係為習知封裝結構1之製法之剖視示意圖。
如第1A圖所示，提供一具有離形層100之第一載板10，以及一具有相對之主動面11a及非主動面11b之晶片11，該晶片11以該主動面11a設置於該離形層100上，其中，該主動面11a具有複數個電極墊110。
如第1B圖所示，利用模封(molding compound)製程 形成封裝膠體12於該第一載板10上，且該封裝膠體12包覆該晶片11之周圍。
如第1C圖所示，移除該第一載板10，將一第二載板10’以其離形層101設置於該晶片11之非主動面11b上。
如第1D圖所示，於該晶片11之主動面11a上形成電性連接該些電極墊110之線路部13，該線路部13係包含至少一介電層130、設於該介電層130上之線路層131及設於該介電層130中並電性連接該線路層131的複數導電盲孔132，且該線路層131係電性連接該些電極墊110，且於最外側之線路層131具有凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)134。
如第1E圖所示，移除該第二載板10’，且於該線路部13上設置一具有離形層102之第三載板10”。
如第1F圖所示，於該封裝膠體12與該非主動面11b上形成一介電層17，再以雷射製程於該封裝膠體12上形成盲孔，以於該盲孔中形成導電體16，且於該介電層17上形成電性連接該導電體16之線路層18，之後於該介電層17上形成絕緣保護層17’，且該絕緣保護層17’具有複數外露該線路層18之開孔170。
如第1G圖所示，移除該第三載板10”，再於該凸塊底下金屬層134上形成銲球19。
惟，習知封裝結構1之製法中，需設置第一至第三載板10,10’,10”以進行該線路部13與線路層18之製作，不僅增加製程步驟，且增加材料(載板)之成本。
再者，由於該封裝膠體12係為液態成型，故需待該封裝膠體12固化後才可進行移除該第一載板10之製程，因而增加製程時間，導致製造成本提高。
又，當移除該第一載板10後，該封裝膠體12易發生翹曲(warpage)的現象，致使該封裝結構1之可靠度降低。
另外，該封裝膠體12係為顆粒狀合成材質，故於形成盲孔時，該盲孔之壁面會產生凹凸不平整之問題，導致該導電體16之結構不完整而易發生電性不良之情況。
因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明係提供一種封裝結構，係包括：承載件，係具有相對之第一表面與第二表面，且該第一表面上形成有至少一凹槽；至少一電子元件，係設於該凹槽中；絕緣層，係設於該凹槽中，以包覆該電子元件；線路部，係設於該承載件之第一表面上且電性連接該電子元件；以及複數導電體，係設於該承載件中並連通該承載件之第一表面與第二表面，且該導電體電性連接該線路部。
本發明復提供一種封裝結構之製法，係包括：提供一具有相對之第一表面與第二表面之承載件，且該第一表面上形成有至少一凹槽；設置至少一電子元件於該凹槽中；形成絕緣層於該凹槽中，以包覆該電子元件，且該電子元件外露於該絕緣層；形成線路部於該承載件之第一表面上 方，且該線路部電性連接該電子元件；形成複數貫穿該承載件之該第一表面與該第二表面之穿孔；以及形成導電材於該穿孔中以作為導電體，且該導電體電性連接該線路部。
前述之封裝結構及其製法中，該承載件係為封裝基板、半導體晶片、晶圓、中介板、經封裝或未經封裝之半導體元件。
前述之封裝結構及其製法中，該電子元件外露於該承載件之第二表面。
前述之封裝結構及其製法中，該電子元件係凸出該第一表面。
前述之封裝結構及其製法中，該絕緣層之表面係與該電子元件之表面齊平。
前述之封裝結構及其製法中，形成該絕緣層之材質係為模封材、乾膜材、線路增層材或光阻材。
前述之封裝結構及其製法中，復包括形成至少一介電層於該承載件之第二表面上，且形成線路層於該介電層上，該線路層電性連接該導電體。
前述之封裝結構及其製法中，復包括形成複數導電元件於該線路部上。
另外，前述之封裝結構及其製法中，復包括設置另一電子元件於該承載件之第二表面上，且該另一電子元件電性連接該導電體。
由上可知，本發明之封裝結構及其製法，藉由該承載件形成凹槽以收納該電子元件，故相較於習知封裝膠體作 為基板本體，本發明不需使用習知第一載板，且不需進行製作封裝膠體之製程，因而能有效減少製程步驟，且能減少耗材之使用以降低材料成本。需注意，本發明之製法係先製作該線路部，再製作該穿孔與該導電體，以簡化製程步驟，且於製程中之治具較簡易。
再者，由於該承載件作為基板本體，故該絕緣層之製作時間大幅縮短，因而相較於習知技術之封裝膠體，本發明可縮短製程時間。
又，本發明使用該承載件作為基板本體，故可避免發生翹曲的現象，以提升該封裝結構之可靠度。
另外，本發明係於該承載件中形成該些穿孔，故該些穿孔之壁面具有較佳之平整性，因而能提升產品之可靠度。
1,2‧‧‧封裝結構
10‧‧‧第一載板
10’‧‧‧第二載板
10”‧‧‧第三載板
100,101,102,241‧‧‧離形層
11‧‧‧晶片
11a,21a‧‧‧主動面
11b,21b‧‧‧非主動面
110,210‧‧‧電極墊
12‧‧‧封裝膠體
13,23‧‧‧線路部
130,230,17,27‧‧‧介電層
131,231,18,28‧‧‧線路層
132,232‧‧‧導電盲孔
134,234‧‧‧凸塊底下金屬層
16,26‧‧‧導電體
17’‧‧‧絕緣保護層
170‧‧‧開孔
19‧‧‧銲球
20‧‧‧承載件
20a‧‧‧第一表面
20b,20b’,20b”‧‧‧第二表面
200‧‧‧凹槽
200a‧‧‧底面
21,3‧‧‧電子元件
22‧‧‧絕緣層
22a‧‧‧表面
24‧‧‧載板
25‧‧‧穿孔
29‧‧‧導電元件
4‧‧‧電子裝置
5‧‧‧封裝堆疊結構
D‧‧‧距離
第1A至1G圖係為習知封裝結構之製法的剖視示意圖；第2A至2G圖係為本發明封裝結構之製法之剖視示意圖；其中，第2D’圖係為第2D圖之另一實施例，第2G’圖係為第2G圖之另一實施例；以及第3圖係為第2G圖之後續製程之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小 等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明之封裝結構2之製法之剖視示意圖。
如第2A圖所示，提供一具有相對之第一表面20a與第二表面20b之承載件20，且該第一表面20a上形成有至少一凹槽200。接著，將具有相對之主動面21a及非主動面21b之電子元件21設置於該凹槽200中，該電子元件21之主動面21a具有複數個電極墊210，且該電子元件21係藉其非主動面21b結合於該凹槽200之底面200a。
於本實施例中，該承載件20係為封裝基板、半導體晶片、晶圓、中介板、經封裝或未經封裝之半導體元件，如第2A圖所示之矽板體。
再者，以乾蝕刻方式製作該凹槽200。
又，該電子元件21係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例 如電阻、電容及電感。
另外，該電子元件21係凸出該第一表面20a，即該該電子元件21之主動面21a高於該第一表面20a。
如第2B圖所示，形成一絕緣層22於該凹槽200中，以包覆該電子元件21，且該電子元件21之主動面21a外露於該絕緣層22。
於本實施例中，該絕緣層22復形成於該承載件20之第一表面20a上，且該絕緣層22之表面22a係與該主動面21a齊平。
再者，形成該絕緣層22係為模封材(molding compound)、乾膜材(dry film)、線路增層材或光阻材(photoresist)，例如，該乾膜材係以貼合方式形成，且該光阻材係以如噴霧濺鍍之塗佈方式形成。
如第2C圖所示，進行線路重佈層(Redistribution layer,RDL)製程，以形成一線路部23於該承載件20之第一表面20a上，即形成於該絕緣層22之表面22a與該電子元件21之主動面21a上，且該線路部23電性連接該電子元件21。
於本實施例中，該線路部23係包含至少一介電層230、設於該介電層230上之線路層231及設於該介電層230中並電性連接該線路層231的導電盲孔232，且該線路層231係電性連接該些電極墊210，且於最外側之線路層231上具有凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)234，供後續製程中接置其它外部元件。
如第2D圖所示，設置一具有離形層241之載板24於該線路部23上，再翻轉整體，之後研磨製程薄化該承載件20之第二表面20b，使該第二表面20b’與該非主動面21b之距離D縮短。
於本實施例中，該載板24係為矽或玻璃材質之板體。
於另一實施例中，如第2D’圖所示，該第二表面20b”與該非主動面21b亦可齊平，使該電子元件21外露於該承載件20之第二表面20b”。具體地，可於第2A圖之製程，先將該凹槽200貫穿該第一表面20a與第二表面20b，再置放該電子元件21於該凹槽200中；或者，可於第2B或2D圖之製程後，移除該承載件20之第二表面20b之部分材質，使該電子元件21外露於該承載件20之第二表面20b”。
如第2E圖所示，進行矽穿孔(Through-Silicon Via，簡稱TSV)製程，形成複數穿孔25於該承載件20之第二表面20b’上，且該穿孔25貫穿該承載件20之該第一表面20a與該第二表面20b’。
於本實施例中，以乾蝕刻方式製作該穿孔25，且該穿孔25復延伸至該絕緣層22，以令該線路部23之部分線路層231外露於該穿孔25。
如第2F圖所示，形成導電材於該些穿孔25中以作為導電體26，且該導電體26電性連接該線路部23之線路層231。
於本實施例中，該導電體26係為柱體。
於其它實施例中，亦可先製作該穿孔25與該導電體 26，再製作該線路部23。本發明之製法係先製作該線路部23，再製作該穿孔25與該導電體26，故能簡化製程步驟，且於製程中之治具較簡易。
如第2G圖所示，進行線路重佈層(Redistribution layer,RDL)製程，形成一如氧化層之介電層27於該承載件20之第二表面20b上，再形成一線路層28於該介電層27上，且該線路層28電性連接該導電體26。
接著，移除該載板24，並形成複數如含有銲錫材料或金屬凸塊之導電元件29於該線路部23之凸塊底下金屬層234上。
於本實施例中，該介電層27與該線路層28之數量可依需求設計為多層，而不限於上述之一層。
再者，於另一實施例中，該電子元件21之主動面21a未凸出該第一表面20a，如齊平，使該絕緣層22之表面22a係與該電子元件21之主動面21a齊平，如第2G’圖所示。
本發明之製法，藉由該承載件20形成凹槽200以收納該電子元件21，故相較於習知技術，本發明使用該承載件20取代習知封裝膠體作為基板本體，因而不需使用習知第一載板，且不需進行製作封裝膠體之製程，進而能有效減少製程步驟，且能減少耗材之使用以降低材料成本。
再者，本發明之絕緣層22若為乾膜材或光阻材，可直接進行後續製程，而不需等待該絕緣層22固化，故能縮短製程時間，以降低製造成本。若該絕緣層22為模封材(液態成型)，由於該承載件20作為基板本體，故該絕緣層 22之佈設體積遠小於習知封裝膠體之佈設體積，因而相較於習知技術，仍可縮短製程時間。
又，本發明使用該承載件20作為基板本體，故相較於習知技術之封裝膠體，本發明可避免發生翹曲的現象，以提升該封裝結構2之強度與可靠度。
另外，本發明係於該承載件20中形成該些穿孔25，故相較於習知技術之封裝膠體，該些穿孔25之壁面具有較佳之平整性，因而能得到結構較佳之垂直導通線路(即該導電體16)，以提升產品之可靠度。
另一方面，於後續製程中，如第3圖所示，設置另一電子元件3於該承載件20之第二表面20b’上之線路層28上，且該另一電子元件3藉由該線路層28電性連接該導電體26，而該封裝結構2以其導電元件29接置一如電路板之電子裝置4，以形成一封裝堆疊結構5。
於本實施例中，該電子元件3係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
本發明復提供一種封裝結構，係包括：一承載件20、至少一電子元件21、一絕緣層22、一線路部23、以及複數導電體26。
所述之承載件20係具有相對之第一表面20a與第二表面20b’，且該第一表面20a上形成有至少一凹槽200。該承載件20係為封裝基板、半導體晶片、晶圓、中介板、經封裝或未經封裝之半導體元件。
所述之電子元件21係設於該凹槽200中。
所述之絕緣層22係設於該凹槽200中以包覆該電子元件21，且形成該絕緣層22之材質係為模封材、乾膜材或光阻材。
所述之線路部23係設於該承載件20之第一表面20a上且電性連接該電子元件21。
所述之導電體26係設於該承載件20中並連通該承載件20之第一表面20a與第二表面20b’，且該導電體26電性連接該線路部23。
於一實施例中，該電子元件21係外露於該承載件20之第二表面20b”。
於一實施例中，該電子元件21係凸出該承載件20之第一表面20a。
於一實施例中，該絕緣層22之表面22a係與該電子元件21之表面(主動面21a)齊平。
於一實施例中，所述之封裝結構2復包括一設於該承載件20之第二表面20b’上的介電層27，且一線路層28係設於該介電層27上並電性連接該導電體26。
於一實施例中，所述之封裝結構2復包括複數導電元件29，係設於該線路部23上。
於一實施例中，所述之封裝結構2復包括另一電子元件3，係設於該承載件20之第二表面20b’上並電性連接該導電體26。
綜上所述，本發明之封裝結構及其製法，藉由該承載 件取代習知封裝膠體，因而能有效減少製程步驟與縮短製程時間，且能降低材料成本，並能避免發生翹曲的現象。
再者，本發明於該承載件中形成該些穿孔，故能提升該些穿孔之壁面平整性，以提升產品之可靠度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧封裝結構
20‧‧‧承載件
20a‧‧‧第一表面
20b’‧‧‧第二表面
200‧‧‧凹槽
21‧‧‧電子元件
22‧‧‧絕緣層
23‧‧‧線路部
234‧‧‧凸塊底下金屬層
26‧‧‧導電體
27‧‧‧介電層
28‧‧‧線路層
29‧‧‧導電元件

Claims (20)

  1. 一種封裝結構，係包括：承載件，係具有相對之第一表面與第二表面，且該第一表面上形成有至少一凹槽；至少一電子元件，係設於該凹槽中；絕緣層，係形成於該凹槽中，以包覆該電子元件；線路部，係形成於該承載件之第一表面上且電性連接該電子元件；以及複數導電體，係設於該承載件中並連通該承載件之第一表面與第二表面，且該導電體電性連接該線路部。
  2. 如申請專利範圍第1項所述之封裝結構，其中，該承載件係為經封裝或未經封裝之半導體元件。
  3. 如申請專利範圍第1項所述之封裝結構，其中，該承載件係為封裝基板、半導體晶片、晶圓或中介板。
  4. 如申請專利範圍第1項所述之封裝結構，其中，該電子元件係外露於該承載件之第二表面。
  5. 如申請專利範圍第1項所述之封裝結構，其中，該電子元件係凸出該第一表面。
  6. 如申請專利範圍第1項所述之封裝結構，其中，該絕緣層之表面係與該電子元件之表面齊平。
  7. 如申請專利範圍第1項所述之封裝結構，其中，形成該絕緣層之材質係為模封材、乾膜材、線路增層材或光阻材。
  8. 如申請專利範圍第1項所述之封裝結構，復包括至少一設於該承載件之第二表面上的介電層，且於該介電層上設有一電性連接該導電體之線路層。
  9. 如申請專利範圍第1項所述之封裝結構，復包括複數導電元件，係設於該線路部上。
  10. 如申請專利範圍第1項所述之封裝結構，復包括另一電子元件，係設於該承載件之第二表面上並電性連接該導電體。
  11. 一種封裝結構之製法，係包括：提供一具有相對之第一表面與第二表面之承載件，且該第一表面上形成有至少一凹槽；設置至少一電子元件於該凹槽中；形成絕緣層於該凹槽中，以包覆該電子元件，且該電子元件外露於該絕緣層；形成線路部於該承載件之第一表面上，且該線路部電性連接該電子元件；形成複數貫穿該承載件之該第一表面與該第二表面之穿孔；以及形成導電材於該穿孔中以作為導電體，並令該些導電體電性連接該線路部。
  12. 如申請專利範圍第11項所述之封裝結構之製法，其中，該承載件係為經封裝或未經封裝之半導體元件。
  13. 如申請專利範圍第11項所述之封裝結構之製法，其中，該承載件係為封裝基板、半導體晶片、晶圓或中 介板。
  14. 如申請專利範圍第11項所述之封裝結構之製法，其中，該電子元件外露於該承載件之第二表面。
  15. 如申請專利範圍第11項所述之封裝結構之製法，其中，該電子元件係凸出該第一表面。
  16. 如申請專利範圍第11項所述之封裝結構之製法，其中，該絕緣層之表面係與該電子元件之表面齊平。
  17. 如申請專利範圍第11項所述之封裝結構之製法，其中，形成該絕緣層之材質係為模封材、乾膜材、線路增層材或光阻材。
  18. 如申請專利範圍第11項所述之封裝結構之製法，復包括形成至少一介電層於該承載件之第二表面上，且形成線路層於該介電層上，該線路層電性連接該導電體。
  19. 如申請專利範圍第11項所述之封裝結構之製法，復包括形成複數導電元件於該線路部上。
  20. 如申請專利範圍第11項所述之封裝結構之製法，復包括設置另一電子元件於該承載件之第二表面上，且該另一電子元件電性連接該導電體。
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