CN106206510A - 多芯片封装结构、晶圆级芯片封装结构及其方法 - Google Patents

多芯片封装结构、晶圆级芯片封装结构及其方法 Download PDF

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CN106206510A
CN106206510A CN201510393369.8A CN201510393369A CN106206510A CN 106206510 A CN106206510 A CN 106206510A CN 201510393369 A CN201510393369 A CN 201510393369A CN 106206510 A CN106206510 A CN 106206510A
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chip
those
insulating barrier
ditches
irrigation canals
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周世文
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Chipmos Technologies Inc
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Chipmos Technologies Bermuda Ltd
Chipmos Technologies Inc
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    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Abstract

本发明提供一种多芯片封装结构、晶圆级芯片封装结构及其方法，包括第一、第二芯片、线路层、多个第一、第二导电凸块及底填胶。第一芯片具有芯片接合区、多个第一内接点及多个第一外接点。线路层配置于第一芯片上且包括多层绝缘层以及至少一金属层。绝缘层上具有沟渠，分布于第一内接点与第一外接点之间，且沿着第一内接点周缘设置。第一导电凸块配置于第一外接点上。第二芯片覆置于芯片接合区上。各第一内接点通过第二导电凸块与第二芯片的第二接点电性连接。底填胶位于第一与第二芯片之间以包覆第一导电凸块，所述方法通过设置沟渠避免底填胶沾附到第一导电凸块，而影响第一导电凸块与线路板之间的电性连接品质。

Description

多芯片封装结构、晶圆级芯片封装结构及其方法
技术领域
本发明是有关于一种封装结构及方法，且特别是有关于一种多芯片封装结构、晶圆级芯片封装结构及其方法。
背景技术
随着电子产品的需求朝向高功能化、信号传输高速化及电路元件高密度化，集成电路芯片所呈现的功能也越强大，而针对消费性电子产品，搭配的被动元件数量也随之剧增。再者，在电子产品强调轻薄短小之际，如何在有限的安装空间中容纳数目庞大的电子元件，已成为电子安装业者急待解决与克服的技术瓶颈。为了解决此一问题，安装技术逐渐走向单安装系统(Systemin Package,简称SIP)的系统整合阶段，特别是多芯片模块(Multi-Chip Module,简称MCM)的安装。
以多芯片封装结构为例，主要是将第一芯片以面对面(face-to-face)的方式配置于第二芯片上，并通过导电凸块作为芯片之间电性连接的媒介，且上述第二芯片则会通过凸块或打线(wire bonding)的方式与线路板电性连接。
在此类封装结构中，由于芯片上的空间日益狭窄，当第一芯片与第二芯片的尺寸接近时，第一芯片边缘会相当靠近第二芯片上用以连接至线路板的导电凸块。因此，当在填充第一芯片与第二芯片之间填入底填胶时，底填胶容易溢流至第二芯片上用以连接至线路板的导电凸块的焊垫上，进而影响了第二芯片与线路板之间电性连接的可靠度。
发明内容
本发明提供一种多芯片封装结构，其具有可阻挡底填胶溢流的沟渠。
本发明提供一种晶圆级芯片封装结构，其可切割出多个上述的多芯片封装结构。
本发明提供一种晶圆级芯片封装方法，其可制作出上述的晶圆级芯片封装结构。
本发明的一种多芯片封装结构，包括第一芯片、线路层、多个第一导电凸块、第二芯片、多个第二导电凸块及底填胶。第一芯片具有芯片接合区、多个位于芯片接合区内的第一内接点以及多个位于芯片接合区外的第一外接点。线路层配置于第一芯片上，线路层包括多层绝缘层以及至少一设置于这些绝缘层之间的金属层，这些绝缘层上具有至少一道沟渠，沟渠分布于这些第一内接点与这些第一外接点之间，且沟渠沿着这些第一内接点周缘设置。这些第一导电凸块配置于这些第一外接点上。第二芯片覆置于(flip on)芯片接合区上，且第二芯片具有多个第二接点。这些第二导电凸块位于这些第一内接点与这些第二接点之间，各第一内接点分别通过对应的第二导电凸块与对应的第二接点电性连接。底填胶位于第一芯片与第二芯片之间以包覆这些第二导电凸块。
本发明的一种晶圆级芯片封装方法，包括下列步骤：提供晶圆，晶圆包括多个阵列排列的第一芯片以及配置于第一芯片上的线路层，其中各第一芯片分别具有芯片接合区、多个位于芯片接合区内的第一内接点及多个位于芯片接合区外的第一外接点，线路层包括多层绝缘层以及至少一设置于这些绝缘层之间的金属层，绝缘层上具有至少一沟渠，沟渠分布于这些第一内接点与这些第一外接点之间，且沟渠沿这些第一内接点周缘设置；于这些第一外接点上形成多个第一导电凸块；提供多个第二芯片，各第二芯片分别具有多个第二接点，且这些第二接点上形成有多个第二导电凸块；将这些第二芯片覆设于这些芯片接合区上，以使这些第二导电凸块位于这些第一内接点与这些第二接点之间，且各第一内接点分别通过对应的第二导电凸块而与对应的第二接点电性连接；以及于第一芯片与第二芯片之间形成底填胶，以包覆这些第二导电凸块。
本发明的一种晶圆级芯片封装结构，包括晶圆、多个第一导电凸块、多个第二芯片、多个第二导电凸块及底填胶。晶圆包括多个阵列排列的第一芯片以及配置于第一芯片上的线路层，其中各第一芯片分别具有芯片接合区、多个位于芯片接合区内的第一内接点及多个位于芯片接合区外的第一外接点，线路层包括多层绝缘层以及至少一设置于这些绝缘层之间的重布线路层，重布线路层具有多个位于这些绝缘层中的沟渠，这些沟渠分布于这些第一内接点与这些第一外接点之间，且这些沟渠沿着这些第一内接点周缘设置。这些第一导电凸块，配置于这些第一外接点上。这些第二芯片覆置于些芯片接合区上，且各第二芯片具有多个第二接点。这些第二导电凸块，位于这些第一内接点与这些第二接点之间，各第一内接点分别通过对应的第二导电凸块与对应的第二接点电性连接。底填胶位于这些第一芯片与这些第二芯片之间以包覆这些第二导电凸块。
基于上述，本发明的多芯片封装结构通过在这些绝缘层上形成沟渠，沟渠分布于这些第一内接点与这些第一外接点之间且沿着这些第一内接点周缘设置，来使第一芯片与第二芯片之间的多余的底填胶溢流时能够流入沟渠，以避免沾附到第一导电凸块，而影响第一导电凸块与线路板之间的电性连接品质。本发明还提供能切割出多个上述的多芯片封装结构的晶圆级芯片封装结构以及封装方法。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1是本发明的一实施例的一种多芯片封装结构的示意图；
图2A是隐藏图1的多芯片封装结构的线路板的俯视图；
图2B至图2D是本发明的其他实施例的一种多芯片封装结构的隐藏线路板的俯视图；
图3是本发明的一实施例的一种晶圆级芯片封装结构的示意图；
图4至图12是制造本发明的一实施例的一种晶圆级芯片封装结构的局部剖面示意图；
图13是本发明的一实施例的一种晶圆级芯片封装方法的流程图。
附图标记说明：
12：介质金属层；
14：光阻层；
100、100a、100b、100c：多芯片封装结构；
110：第一芯片；
112：芯片接合区；
114：第一内接点；
116：第一外接点；
120：线路层；
122：第一绝缘层；
122a：凹沟；
124：金属层；
126：第二绝缘层；
126a：穿槽；
128、128a、128b、128c：沟渠；
130：第一导电凸块；
135：第二导电凸块
140：第二芯片；
142：第二接点；
150：底填胶；
160：线路板；
200：晶圆级芯片封装结构；
202：晶圆；
300：晶圆级芯片封装方法；
310-370：步骤。
具体实施方式
图1是本发明的一实施例的一种多芯片封装结构的示意图。请参照图1，本实施例的多芯片封装结构100包括第一芯片110、线路层120、多个第一导电凸块130、多个第二导电凸块135、第二芯片140、底填胶150及线路板160。
第一芯片110具有芯片接合区112、多个位于芯片接合区112内的第一内接点114以及多个位于芯片接合区112外的第一外接点116。
线路层120配置于第一芯片110上，线路层120包括多层绝缘层122、126以及至少一设置于这些绝缘层122、126之间的金属层124。详细地说，线路层120的这些绝缘层包括第一绝缘层122及第二绝缘层126。第一绝缘层122配置于第一芯片110上并且暴露出这些第一内接点114以及这些第一外接点116。金属层124配置于第一绝缘层122上并与这些第一内接点114电性连接。第二绝缘层126覆盖于第一绝缘层122以及金属层124上以暴露出部分的金属层124以及这些第一外接点116。在本实施例中，金属层124可向外延伸成为重布线路层(Redistribution Layer，简称RDL)，而配置于第一绝缘层122上并与这些第一内接点114电性连接。在其它实施例中，金属层124也可以是对应第一内接点114的柱状的金属层。
在本实施例中，第一芯片110的尺寸大于第二芯片140的尺寸，尺寸较小的第二芯片140覆置于尺寸较大的第一芯片110的芯片接合区112上。第二芯片140具有多个第二接点142。第二导电凸块135位于第一芯片110的第一内接点114与第二芯片140的第二接点142之间。第一芯片110的第一内接点114通过金属层124、对应的第二导电凸块135与第二芯片140的上对应的第二接点142电性连接，以使第一芯片110与第二芯片140电性连接。
底填胶(underfill)150位于第一芯片110与第二芯片140之间以包覆这些第二导电凸块135。底填胶150的材质例如为环氧树脂(Epoxy)，底填胶150可用来提供第一芯片110与第二芯片140之间的固定效果，并能够提供缓冲及防潮防尘等效果来提升多芯片封装结构100的可靠度。
第一导电凸块130配置于第一芯片110的第一外接点116上，第一芯片110能够通过第一导电凸块130而与线路板160电性连接。在本实施例中，由于第二芯片140与第二导电凸块135位于线路板160与第一芯片110之间，第一导电凸块130的高度会大于第二导电凸块135的高度。更进一步地说，第一导电凸块130的高度会大于第二导电凸块135与第二芯片140的总高度。
本实施例的多芯片封装结构100在制作时会先将第二芯片140覆置并电性连接于第一芯片110，在第一芯片110与第二芯片140之间填入底填胶150，再将第一芯片110通过第一导电凸块130连接至线路板160，以使第一芯片110、第二芯片140与线路板160三者之间电性连接。如图1所示，由于第一芯片110与第二芯片140的尺寸接近，当底填胶150被填入第一芯片110与第二芯片140之间的部位时，底填胶150可能会往外溢流而接触到第一导电凸块130。
为了避免第一导电凸块130被底填胶150沾附而影响到之后连接至与线路板160之间的连接能力，在本实施例中，第一绝缘层122与第二绝缘层126上具有至少一道沟渠128，沟渠128分布于这些第一内接点114与这些第一外接点116之间，且沟渠128沿着这些第一内接点114周缘设置。更进一步地说，在本实施例中，多芯片封装结构100通过在第一绝缘层122与第二绝缘层126上制作出沟渠128，以供部分底填胶150填入沟渠128中，而避免多余的底填胶150溢出而沾附到第一导电凸块130。
需说明的是，在本实施例中，沟渠128的深度等于第一绝缘层122与第二绝缘层126的厚度总和，但在其他实施例中，沟渠128的深度也可以小于第一绝缘层122与第二绝缘层126的厚度总和。
图2A是隐藏图1的多芯片封装结构的线路板的俯视图。如图1与图2A所示，在本实施例中，沟渠128为环形沟渠，且沟渠128位在第一绝缘层122与第二绝缘层126上的位置对应于第二芯片140的外轮廓，且环绕这些第二导电凸块135。当底填胶150填充至第一芯片110与第二芯片140之间以包覆第二导电凸块135时，多余的底填胶150会填入沟渠128，有效地避免底填胶150向外溢流至第一导电凸块130的机率。因此，第一导电凸块130便不会被底填胶150污染而影响了与线路板160连接的品质。
需说明的是，上面仅显示其中一种沟渠128的形式，但沟渠128的形状与轮廓并不以此为限制。图2B至图2D是本发明的其他实施例的一种多芯片封装结构的隐藏线路板的俯视图。为了方便了解，在图2B至图2D中，相同的元件以与前一实施例相同的元件编号来表示。请先参照图2B，沟渠128a也是环形沟渠。本实施例的多芯片封装结构100a的沟渠128a与前一实施例的沟渠128的主要差异在于，在本实施例中，沟渠128a的局部区域会朝向第一导电凸块130之间的空间凹陷，而使得沟渠128a的外轮廓上会呈现出直线与弧线交错的轮廓，相对的，使容纳溢胶之空间得以增加。
请参照图2C与图2D，沟渠128b、128c可包括多个彼此分离的条形沟渠，且这些沟渠128b、128c排列成环状以环绕这些第二导电凸块135。更详细地说，在图2C中，多芯片封装结构100b具有四个长直条形的沟渠128b，分别配置在第二导电凸块135的四周，以排列呈矩形。在图2D中，多芯片封装结构100c的沟渠128c中，一部分呈长直条形，另一部分具有弯角。长直条形的沟渠128c位在第二导电凸块135的四周而形成矩形的四边，具有弯角的沟渠128c形成矩形的四角。当然，沟渠128、128a、128b、128c的实际形状并不以上述为限制，只要能够降低底填胶150向外溢流至第一导电凸块130的机率即可。
在上面的实施例中，沟渠128、128a、128b、128c是制作在芯片附接在芯片(Chip on Chip,简称COC)的封装阶段中，但在其他实施例中，沟渠128、128a、128b、128c也可以制作在芯片附接在晶圆(Chip on Wafer,简称COW)的封装阶段。图3是本发明的一实施例的一种晶圆级芯片封装结构的示意图。请参照图3，在晶圆202被切割之前，将上述的线路层120、第一导电凸块130、第二导电凸块135、第二芯片140、线路板160等元件配置在晶圆202上，并在晶圆202的线路层120上制作出沟渠128，而形成晶圆级芯片封装结构200。此晶圆级芯片封装结构200可切割成多个上述的多芯片封装结构100。
下面将以图3的晶圆级芯片封装结构200为例，详细地介绍晶圆级芯片封装结构200的其中一种晶圆级芯片封装方法。图4至图12是制造本发明的一实施例的一种晶圆级芯片封装结构的局部剖面示意图。图13是本发明的一实施例的一种晶圆级芯片封装方法的流程图。需说明的是，为了清楚显示各元件的细节，图4至图12仅示出晶圆级芯片封装结构200在制作过程之中的局部区域。更精确地说，图4至图12仅示出晶圆级芯片封装结构200的其中一个多芯片封装结构100的制作过程。并且，为了方便了解，图4至图12中所呈现的视角是以图3的A-A线段的剖面来绘示。此外，在本实施例中，相似或相同的元件以与前一实施例相同的元件编号来表示。
本实施例的晶圆级芯片封装方法300包括下列步骤：首先，如图13的步骤310所述以及配合图4至图12所示，提供晶圆202，晶圆202包括多个阵列排列的第一芯片110以及配置于第一芯片110上的线路层120，其中各第一芯片110分别具有芯片接合区112、多个位于芯片接合区112内的第一内接点114及多个位于芯片接合区112外的第一外接点116。线路层120包括多层绝缘层(例如是第一绝缘层122与第二绝缘层126)以及至少一设置于该些绝缘层之间的金属层，该绝缘层上具有至少一沟渠128，沟渠128分布于这些第一内接点14与这些第一外接点116之间，且沟渠128沿这些第一内接点114的周缘设置。
详细地说，请先参考图4，晶圆202包括多个第一芯片110，第一芯片110具有芯片接合区112、多个位于芯片接合区112内的第一内接点114以及多个位于芯片接合区112外的第一外接点116。一开始可选择性地对晶圆202进行清洗(Incoming Clean)的步骤，通过例如是高压水柱清洗的方式来移除第一芯片110表面的脏污。当然，在其他实施例中，也可以选择不对晶圆202进行清洗。
接着，如图5所示，在第一芯片110上形成图案化的第一绝缘层122。详细地说，可先在第一芯片110上涂布绝缘层，该绝缘层的材料可为一般的感光性光阻材料、聚酰亚胺(PI)层或是氮化硅(silicon nitride,简称Si3N4)，再罩设光罩(未示出)在绝缘层，并且进行曝光(Exposure)的程序，其中光罩的图案对应于所欲露出的第一芯片的图案。之后进行显影(Develop)的程序，以显影液将未曝光的绝缘层溶解并移除。接着，通过加热的方式固化(Curing)未被移除的绝缘层，再通过例如是氧气电浆的方式对固化的绝缘层进行表面处理，即可完成第一绝缘层122。
如图5所示，第一绝缘层122配置于这些第一芯片110上，第一绝缘层122暴露出这些第一内接点114以及这些第一外接点116，且第一绝缘层122具有凹沟122a。凹沟122a位在对应于第一内接点114及第一外接点116之间的位置，且围绕第一内接点114。在本实施例中，凹沟的深度等于第一绝缘层122的厚度，但在其他实施例中，凹沟的深度也可以小于第一绝缘层122的厚度。
再来，如图6所示，沉积介质金属层(UBM Deposition)12。在本实施例中，先通过氩气去移除第一绝缘层122、第一内接点114与第一外接点116上的氧化物。接着，在第一绝缘层122、第一内接点114与第一外接点116上依序溅镀钛钨层、金层与钛层，以形成介质金属层12，其中介质金属层12也会形成在第一绝缘层122的凹沟122a内。
接着，如图7所示，形成图案化的光阻层14与线路层124。详细地说，在本实施例中，先在图6的介质金属层12上涂布光阻，再进行曝光的程序。使光阻层14上对应于第一内接点114与第一外接点116的区域形成开孔后再进行一道电镀方法，而于该曝露的开孔中形成金属层124。接着，移除光阻层14及未被金属层124覆盖的介质金属层12，而留下了金属层124。如图8所示，该金属层124可向外延伸成为重布线路层(RDL)，而配置于第一绝缘层122上并与这些第一内接点114电性连接。
在其它实施例中，该光阻层14的开孔也可对应第一绝缘层122的凹沟122a形成较小区域的孔径，在进行电镀方法时，将在开孔中原向外延伸的金属层124对应该第一内接点114而缩小范围形成柱状的金属层。
其后，如图9所示，形成图案化的第二绝缘层126。在本实施例中，第二绝缘层126的材质例如为聚酰亚胺，如同第一绝缘层122的形成方式，通过曝光显影等步骤形成第二绝缘层126。第二绝缘层126覆盖于第一绝缘层122以及金属层124上，并暴露出部分的金属层124以及这些第一外接点116。其中，第二绝缘层126上还具有穿槽126a，第二绝缘层126的穿槽126a的位置对应于第一绝缘层122的凹沟122a的位置。在本实施例中，穿槽126a与凹沟122a共同形成沟渠。形成该沟渠128的方法(也就是第一绝缘层122的凹沟122a与第二绝缘层126穿槽126a的形成方法)包括黄光方法、雷射加工或反应离子蚀刻(Reactive-Ion Etching，简称RIE)。
在本实施例中，沟渠128位于第一绝缘层122与第二绝缘层126中，第一绝缘层122的凹沟122a的深度等于第一绝缘层122的厚度，且第二绝缘层126的穿槽126a的深度等于第二绝缘层126的厚度，而使得沟渠128的深度等于第一绝缘层122与第二绝缘层126的厚度总和。但在其他实施例中，第一绝缘层122的凹沟122a的深度也可以小于第一绝缘层122的厚度，而使得沟渠128的深度小于第一绝缘层122与第二绝缘层126的厚度总和。或者，在其他实施例中，沟渠128也可以只位在第二绝缘层126中。也就是说，第一绝缘层122并不存在凹沟122a。第二绝缘层126也可以只具有未穿透的凹陷沟槽，而非穿透的穿槽126a。
在本实施例中，通过图4至图9的程序完成了步骤310。再来，如图10所示，在这些第一外接点116上形成多个第一导电凸块130(步骤320)。形成的方式可包括植球、电镀、印刷等方式后回焊成型。
接着，如图11所示，提供多个第二芯片140，各第二芯片140具有多个第二接点142，且这些第二接点142上形成有多个第二导电凸块135(步骤330)。第一导电凸块130与第二导电凸块135的材质包括单一金属元素或合金，其材质可为含铅材料(例如铅或锡铅合金)或无铅材料，其包括金、银、铜、锡、镍或其合金。在本发明附图中，以球状为例，然而，其外观形状不仅可成型为球状、圆柱状或圆顶柱状，其所选用的材料也可采用单一种金属材料或采用两种或两种以上的金属材料电镀成型，例如，铜柱(Copper Pillar)上形成一层锡(Solder Cap)，或铜柱外壁覆盖一层金，均为本发明的可行的导电凸块。
将第二芯片140覆设于芯片接合区112上，以使这些第二导电凸块135位于这些第一内接点114与这些第二接点142之间，且各第一内接点114分别通过对应的第二导电凸块135而与对应的第二接点142电性连接(步骤340)，其中这些第二导电凸块135通过金属层124与这些第一内接点114电性连接。
接着，在第一芯片110与第二芯片140之间形成底填胶150，以包覆这些第二导电凸块135(步骤350)。
最后，如图12所示，进行晶圆切割步骤，以使这些第一芯片110彼此分离而形成多个多芯片封装结构100(步骤360)，接下来，再使这些单离化的多芯片封装结构100以这些第一导电凸块130电性连接至线路板160，其中第二芯片140、这些第一导电凸块130以及这些第二导电凸块135位于线路板160与第一芯片110之间(步骤370)。在本实施例的步骤340与步骤370中，可通过回焊作业来使第二导电凸块135连接至金属层124以及第一导电凸块130连接至线路板160。值得一提的是，该回焊作业可针对该第一导电凸块130与第二导电凸块135同时加热回焊，亦可先就第二导电凸块135回焊连接于第一芯片110上，再进行第二次回焊作业，使第一导电凸块130连接于缐路板160上，在实施作业上该回焊作业可随方法不同而作调整。
再次说明的是，图4至图12仅示出晶圆级芯片封装结构200的其中一部分，因此，在图12中显示出一个多芯片封装结构100，实际上，若以图3的角度观之，则可切割出多个多芯片封装结构100。
此外，虽然在本实施例中是先在这些第一外接点116上形成多个第一导电凸块130(步骤320)之后，再将第二芯片140覆设于芯片接合区112上(步骤330、340)。但在其他实施例中，也可以是先将第二芯片140覆设于芯片接合区112上，以使第二导电凸块135连接至第一内接点114(步骤330、340)，再在这些第一外接点116上形成多个第一导电凸块130(步骤320)，方法顺序上可视需求而调整。
综上所述，本发明的多芯片封装结构与晶圆级芯片封装结构通过在线路层的这些绝缘层上形成沟渠，沟渠分布于这些第一内接点与这些第一外接点之间且沿着这些第一内接点周缘设置，来使第一芯片与第二芯片之间的多余的底填胶溢流时能够流入沟渠，以避免沾附到第一导电凸块，而影响第一导电凸块与线路板之间的电性连接品质。本发明还提供上述晶圆级芯片封装结构的封装方法，而能够制作出底填胶不会流至第一导电凸块的晶圆级芯片封装结构。并且，此晶圆级芯片封装结构通过晶圆切割程序，便可形成多个上述的多芯片封装结构。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (20)

1.一种多芯片封装结构，其特征在于，包括：
第一芯片，具有芯片接合区、多个位于所述芯片接合区内的第一内接点以及多个位于所述芯片接合区外之第一外接点；
线路层，配置于所述第一芯片上，所述线路层包括多层绝缘层以及至少一设置于该些绝缘层之间的金属层，该些绝缘层上具有至少一道沟渠，所述沟渠分布于该些第一内接点与该些第一外接点之间，且所述沟渠沿着该些第一内接点周缘设置；
多个第一导电凸块，配置于该些第一外接点上；
第二芯片，覆置于所述芯片接合区上，且所述第二芯片具有多个第二接点；
多个第二导电凸块，位于该些第一内接点与该些第二接点之间，各所述第一内接点分别通过对应的所述第二导电凸块与对应的所述第二接点电性连接；以及
底填胶，位于所述第一芯片与所述第二芯片之间以包覆该些第二导电凸块。
2.根据权利要求1所述的多芯片封装结构，其特征在于，所述第一芯片的尺寸大于所述第二芯片的尺寸。
3.根据权利要求1所述的多芯片封装结构，其特征在于，所述线路层的该些绝缘层包括：
第一绝缘层，配置于所述第一芯片上并且暴露出该些第一内接点以及该些第一外接点；以及
第二绝缘层，覆盖于所述第一绝缘层上，其中所述金属层设置于所述第一绝缘层与所述第二绝缘层之间，且所述第二绝缘层暴露出部分的所述金属层以及该些第一外接点，其中该些第二导电凸块通过所述金属层与该些第一内接点电性连接。
4.根据权利要求3所述的多芯片封装结构，其特征在于，所述沟渠位于所述第一绝缘层与所述第二绝缘层中，且所述沟渠的深度等于或小于所述第一绝缘层与所述第二绝缘层的厚度总和。
5.根据权利要求1所述的多芯片封装结构，其特征在于，还包括线路板，其中所述线路板与该些第一导电凸块电性连接，且所述第二芯片、该些第一导电凸块以及该些第二导电凸块位于所述线路板与所述第一芯片之间。
6.根据权利要求1所述的多芯片封装结构，其特征在于，各所述第一导电凸块的高度大于各所述第二导电凸块的高度。
7.根据权利要求1所述的多芯片封装结构，其特征在于，所述沟渠包括环形沟渠，且所述沟渠环绕于该些第一内接点的周缘。
8.根据权利要求1所述的多芯片封装结构，其特征在于，所述沟渠包括多个彼此分离的条形沟渠，且该些条形沟渠排列成环状以环绕该些第一内接点。
9.一种晶圆级芯片封装方法，其特征在于，包括：
提供晶圆，所述晶圆包括多个阵列排列的第一芯片以及配置于所述第一芯片上的线路层，其中各所述第一芯片分别具有芯片接合区、多个位于所述芯片接合区内的第一内接点及多个位于所述芯片接合区外的第一外接点，所述线路层包括多层绝缘层以及至少一设置于该些绝缘层之间的金属层，所述绝缘层上具有至少一沟渠，所述沟渠分布于该些第一内接点与该些第一外接点之间，且所述沟渠沿该些第一内接点周缘设置；
在该些第一外接点上形成多个第一导电凸块；
提供多个第二芯片，各所述第二芯片分别具有多个第二接点，且该些第二接点上形成有多个第二导电凸块；
将该些第二芯片覆设于该些芯片接合区上，以使该些第二导电凸块位于该些第一内接点与该些第二接点之间，且各所述第一内接点分别通过对应的所述第二导电凸块而与对应的所述第二接点电性连接；以及
在所述第一芯片与所述第二芯片之间形成底填胶，以包覆该些第二导电凸块。
10.根据权利要求9所述的晶圆级芯片封装方法，其特征在于，各所述第一芯片的尺寸大于各所述第二芯片的尺寸。
11.根据权利要求9所述的晶圆级芯片封装方法，其特征在于，将该些第二芯片覆设于该些芯片接合区之前，在该些第一外接垫上形成该些第一导电凸块。
12.根据权利要求9所述的晶圆级芯片封装方法，其特征在于，还包括线路板，其中所述线路板与该些第二导电凸块电性连接，且所述第二芯片、该些第一导电凸块以及该些第二导电凸块位于所述线路板与所述第一芯片之间。
13.根据权利要求9所述的晶圆级芯片封装方法，其特征在于，所述线路层的该些绝缘层包括：
第一绝缘层，配置于所述第一芯片上并且暴露出该些第一内接点以及该些第一外接点；以及
第二绝缘层，覆盖于所述第一绝缘层上，其中所述金属层设置于所述第一绝缘层与所述第二绝缘层之间，且所述第二绝缘层暴露出部分的所述金属层以及该些第一外接点，其中该些第二导电凸块通过所述金属层与该些第一内接点电性连接。
14.根据权利要求13所述的晶圆级芯片封装方法，其特征在于，所述沟渠位于所述第一绝缘层与所述第二绝缘层中，且所述沟渠的深度等于或小于所述第一绝缘层与所述第二绝缘层的厚度总和。
15.根据权利要求9所述的晶圆级芯片封装方法，其特征在于，其进一步包括：
晶圆切割步骤，使该些第一芯片彼此分离而形成多个多芯片封装结构。
16.一种晶圆级芯片封装结构，其特征在于，包括：
晶圆，包括多个阵列排列的第一芯片以及配置于所述第一芯片上的线路层，其中各所述第一芯片分别具有芯片接合区、多个位于所述芯片接合区内的第一内接点及多个位于所述芯片接合区外的第一外接点，所述线路层包括多层绝缘层以及至少一设置于该些绝缘层之间的重布线路层，所述重布线路层具有多个位于该些绝缘层中的沟渠，该些沟渠分布于该些第一内接点与该些第一外接点之间，且该些沟渠沿着该些第一内接点周缘设置；
多个第一导电凸块，配置于该些第一外接点上；
多个第二芯片，覆置于该些芯片接合区上，且各所述第二芯片具有多个第二接点；
多个第二导电凸块，位于该些第一内接点与该些第二接点之间，各所述第一内接点分别通过对应的所述第二导电凸块与对应的所述第二接点电性连接；以及
底填胶，位于该些第一芯片与该些第二芯片之间以包覆该些第二导电凸块。
17.根据权利要求16所述的晶圆级芯片封装结构，其特征在于，各所述第一芯片的尺寸大于各所述第二芯片的尺寸。
18.根据权利要求16所述的晶圆级芯片封装结构，其特征在于，所述线路层的该些绝缘层包括：
第一绝缘层，配置于该些第一芯片上并且暴露出该些第一内接点以及该些第一外接点；以及
第二绝缘层，覆盖于所述第一绝缘层上，其中所述重布线路层设置于所述第一绝缘层与所述第二绝缘层之间，且所述第二绝缘层暴露出部分的所述重布线路层以及该些第一外接点，其中该些第二导电凸块通过所述重布线路层与该些第一内接点电性连接。
19.根据权利要求18所述的晶圆级芯片封装结构，其特征在于，该些沟渠位于所述第一绝缘层与所述第二绝缘层中，且该些沟渠的深度等于或小于所述第一绝缘层与所述第二绝缘层的厚度总和。
20.根据权利要求16所述的晶圆级芯片封装结构，其特征在于，各所述第一导电凸块的高度大于各所述第二导电凸块的高度。
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