TW201639095A - 多晶片封裝結構、晶圓級晶片封裝結構及其製程 - Google Patents

多晶片封裝結構、晶圓級晶片封裝結構及其製程 Download PDF

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TW201639095A
TW201639095A TW104113402A TW104113402A TW201639095A TW 201639095 A TW201639095 A TW 201639095A TW 104113402 A TW104113402 A TW 104113402A TW 104113402 A TW104113402 A TW 104113402A TW 201639095 A TW201639095 A TW 201639095A
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Taiwan
Prior art keywords
wafer
insulating layer
contacts
layer
conductive bumps
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TW104113402A
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English (en)
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TWI556387B (zh
Inventor
周世文
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南茂科技股份有限公司
百慕達南茂科技股份有限公司
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Priority to TW104113402A priority Critical patent/TWI556387B/zh
Priority to CN201510393369.8A priority patent/CN106206510A/zh
Priority to US14/856,546 priority patent/US9728479B2/en
Application granted granted Critical
Publication of TW201639095A publication Critical patent/TW201639095A/zh
Publication of TWI556387B publication Critical patent/TWI556387B/zh
Priority to US15/628,651 priority patent/US10002815B2/en

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    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Abstract

一種多晶片封裝結構，包括第一、第二晶片、線路層、多個第一、第二導電凸塊及底填膠。第一晶片具有晶片接合區、多個第一內接點及多個第一外接點。線路層配置於第一晶片上且包括多層絕緣層以及至少一金屬層。絕緣層上具有溝渠，分佈於第一內接點與第一外接點之間，且沿著第一內接點周緣設置。第一導電凸塊配置於第一外接點上。第二晶片覆置於晶片接合區上。各第一內接點透過第二導電凸塊與第二晶片的第二接點電性連接。底填膠位於第一與第二晶片之間以包覆第一導電凸塊。本發明更提供一種晶圓級晶片封裝結構及其製程。

Description

多晶片封裝結構、晶圓級晶片封裝結構及其製程
本發明是有關於一種封裝結構及製程，且特別是有關於一種多晶片封裝結構、晶圓級晶片封裝結構及其製程。
隨著電子產品的需求朝向高功能化、訊號傳輸高速化及電路元件高密度化，積體電路晶片所呈現的功能也越強大，而針對消費性電子產品，搭配的被動元件數量亦隨之遽增。再者，在電子產品強調輕薄短小之際，如何在有限的構裝空間中容納數目龐大的電子元件，已成為電子構裝業者急待解決與克服的技術瓶頸。為了解決此一問題，構裝技術逐漸走向單構裝系統(System in Package,SIP)的系統整合階段，特別是多晶片模組(Multi-Chip Module,MCM)的構裝。
以多晶片封裝結構為例，主要是將第一晶片以面對面(face-to-face)的方式配置於一第二晶片上，並藉由導電凸塊作為晶 片之間電性連接的媒介，且上述第二晶片則會藉由凸塊或打線(wire bonding)的方式與線路板電性連接。
在此類封裝結構中，由於晶片上的空間日益狹窄，當第一晶片與第二晶片的尺寸接近時，第一晶片邊緣會相當靠近第二晶片上用以連接至線路板的導電凸塊。因此，當在填充第一晶片與第二晶片之間填入底填膠時，底填膠容易溢流至第二晶片上用以連接至線路板的導電凸塊之銲墊上，進而影響了第二晶片與線路板之間電性連接的可靠度。
本發明提供一種多晶片封裝結構，其具有可阻擋底填膠溢流的溝渠。
本發明提供一種晶圓級晶片封裝結構，其可切割出多個上述的多晶片封裝結構。
本發明提供一種晶圓級晶片封裝結構製程，其可製作出上述的晶圓級晶片封裝結構。
本發明的一種多晶片封裝結構，包括一第一晶片、一線路層、多個第一導電凸塊、一第二晶片、多個第二導電凸塊及一底填膠。第一晶片具有一晶片接合區、多個位於晶片接合區內的第一內接點以及多個位於晶片接合區外之第一外接點。線路層配置於第一晶片上，線路層包括多層絕緣層以及至少一設置於這些絕緣層之間的金屬層，這些絕緣層上具有至少一道溝渠，溝渠分 佈於這些第一內接點與這些第一外接點之間，且溝渠沿著這些第一內接點周緣設置。這些第一導電凸塊配置於這些第一外接點上。第二晶片覆置於(flip on)晶片接合區上，且第二晶片具有多個第二接點。這些第二導電凸塊位於這些第一內接點與這些第二接點之間，各第一內接點分別透過對應的第二導電凸塊與對應的第二接點電性連接。底填膠位於第一晶片與第二晶片之間以包覆這些第二導電凸塊。
本發明的一種晶圓級晶片封裝製程，包括下列步驟：提供一晶圓，晶圓包括多個陣列排列的第一晶片以及一配置於第一晶片上的線路層，其中各第一晶片分別具有一晶片接合區、多個位於晶片接合區內的第一內接點及多個位於晶片接合區外的第一外接點，線路層包括多層絕緣層以及至少一設置於這些絕緣層之間的金屬層，絕緣層上具有至少一溝渠，溝渠分佈於這些第一內接點與這些第一外接點之間，且溝渠沿這些第一內接點周緣設置；於這些第一外接點上形成多個第一導電凸塊；提供多個第二晶片，各第二晶片分別具有多個第二接點，且這些第二接點上形成有多個第二導電凸塊；將這些第二晶片覆設於這些晶片接合區上，以使這些第二導電凸塊位於這些第一內接點與這些第二接點之間，且各第一內接點分別透過對應的第二導電凸塊而與對應的第二接點電性連接；以及於第一晶片與第二晶片之間形成一底填膠，以包覆這些第二導電凸塊。
本發明的一種晶圓級晶片封裝結構，包括一晶圓、多個 第一導電凸塊、多個第二晶片、多個第二導電凸塊及一底填膠。晶圓包括多個陣列排列的第一晶片以及一配置於第一晶片上的線路層，其中各第一晶片分別具有一晶片接合區、多個位於晶片接合區內的第一內接點及多個位於晶片接合區外的第一外接點，線路層包括多層絕緣層以及至少一設置於這些絕緣層之間的重佈線路層，重佈線路層具有多個位於這些絕緣層中的溝渠，這些溝渠分佈於這些第一內接點與這些第一外接點之間，且這些溝渠沿著這些第一內接點周緣設置。這些第一導電凸塊，配置於這些第一外接點上。這些第二晶片覆置於些晶片接合區上，且各第二晶片具有多個第二接點。這些第二導電凸塊，位於這些第一內接點與這些第二接點之間，各第一內接點分別透過對應的第二導電凸塊與對應的第二接點電性連接。底填膠位於這些第一晶片與這些第二晶片之間以包覆這些第二導電凸塊。
基於上述，本發明的多晶片封裝結構藉由在這些絕緣層上形成溝渠，溝渠分佈於這些第一內接點與這些第一外接點之間且沿著這些第一內接點周緣設置，來使第一晶片與第二晶片之間的多餘的底填膠溢流時能夠流入溝渠，以避免沾附到第一導電凸塊，而影響第一導電凸塊與線路板之間的電性連接品質。本發明更提供能切割出多個上述的多晶片封裝結構的晶圓級晶片封裝結構以及其製程。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
12‧‧‧介質金屬層
14‧‧‧光阻層
100、100a、100b、100c‧‧‧多晶片封裝結構
110‧‧‧第一晶片
112‧‧‧晶片接合區
114‧‧‧第一內接點
116‧‧‧第一外接點
120‧‧‧線路層
122‧‧‧第一絕緣層
122a‧‧‧凹溝
124‧‧‧金屬層
126‧‧‧第二絕緣層
126a‧‧‧穿槽
128、128a、128b、128c‧‧‧溝渠
130‧‧‧第一導電凸塊
135‧‧‧第二導電凸塊
140‧‧‧第二晶片
142‧‧‧第二接點
150‧‧‧底填膠
160‧‧‧線路板
200‧‧‧晶圓級晶片封裝結構
202‧‧‧晶圓
300‧‧‧晶圓級晶片封裝製程
310-370‧‧‧步驟
圖1是依照本發明的一實施例的一種多晶片封裝結構的示意圖。
圖2A是隱藏圖1的多晶片封裝結構的線路板的上視示意圖。
圖2B至圖2D是依照本發明的其他實施例的一種多晶片封裝結構的隱藏線路板的上視示意圖。
圖3是依照本發明的一實施例的一種晶圓級晶片封裝結構的示意圖。
圖4至圖12是製造本發明的一實施例的一種晶圓級晶片封裝結構的局部剖面示意圖。
圖13是依照本發明的一實施例的一種晶圓級晶片封裝製程的流程圖。
圖1是依照本發明的一實施例的一種多晶片封裝結構的示意圖。請參閱圖1，本實施例的多晶片封裝結構100包括一第一晶片110、一線路層120、多個第一導電凸塊130、多個第二導電凸塊135、一第二晶片140、一底填膠150及一線路板160。
第一晶片110具有一晶片接合區112、多個位於晶片接合區112內的第一內接點114以及多個位於晶片接合區112外之第 一外接點116。
線路層120配置於第一晶片110上，線路層120包括多層絕緣層122、126以及至少一設置於這些絕緣層122、126之間的金屬層124。詳細地說，線路層120的這些絕緣層包括一第一絕緣層122及一第二絕緣層126。第一絕緣層122配置於第一晶片110上並且暴露出這些第一內接點114以及這些第一外接點116。金屬層124配置於第一絕緣層122上並與這些第一內接點114電性連接。第二絕緣層126覆蓋於第一絕緣層122以及金屬層124上以暴露出部分的金屬層124以及這些第一外接點116。在本實施例中，金屬層124可向外延伸成為一重佈線路層(RDL)，而配置於第一絕緣層122上並與這些第一內接點114電性連接。於其它實施例中，金屬層124也可以是對應第一內接點114之柱狀的金屬層。
在本實施例中，第一晶片110的尺寸大於第二晶片140的尺寸，尺寸較小的第二晶片140覆置於尺寸較大的第一晶片110的晶片接合區112上。第二晶片140具有多個第二接點142。第二導電凸塊135位於第一晶片110的第一內接點114與第二晶片140的第二接點142之間。第一晶片110的第一內接點114透過金屬層124、對應的第二導電凸塊135與第二晶片140的上對應的第二接點142電性連接，以使第一晶片110與第二晶片140電性連接。
底填膠(underfill)150位於第一晶片110與第二晶片140之間以包覆這些第二導電凸塊135。底填膠150之材質例如為環氧 樹脂(Epoxy)，底填膠150可用來提供第一晶片110與第二晶片140之間的固定效果，並能夠提供緩衝及防潮防塵等效果來提昇多晶片封裝結構100的可靠度。
第一導電凸塊130配置於第一晶片110的第一外接點116上，第一晶片110能夠藉由第一導電凸塊130而與線路板160電性連接。在本實施例中，由於第二晶片140與第二導電凸塊135位於線路板160與第一晶片110之間，第一導電凸塊130的高度會大於第二導電凸塊135的高度。更進一步地說，第一導電凸塊130的高度會大於第二導電凸塊135與第二晶片140的總高度。
本實施例的多晶片封裝結構100在製作時會先將第二晶片140覆置並電性連接於第一晶片110，在第一晶片110與第二晶片140之間填入底填膠150，再將第一晶片110透過第一導電凸塊130連接至線路板160，以使第一晶片110、第二晶片140與線路板160三者之間電性連接。如圖1所示，由於第一晶片110與第二晶片140的尺寸接近，當底填膠150被填入第一晶片110與第二晶片140之間的部位時，底填膠150可能會往外溢流而接觸到第一導電凸塊130。
為了避免第一導電凸塊130被底填膠150沾附而影響到之後連接至與線路板160之間的連接能力，在本實施例中，第一絕緣層122與第二絕緣層126上具有至少一道溝渠128，溝渠128分佈於這些第一內接點114與這些第一外接點116之間，且溝渠128沿著這些第一內接點114周緣設置。更進一步地說，在本實施 例中，多晶片封裝結構100透過在第一絕緣層122與第二絕緣層126上製作出溝渠128，以供部分底填膠150填入溝渠128中，而避免多餘的底填膠150溢出而沾附到第一導電凸塊130。
需說明的是，在本實施例中，溝渠128的深度等於第一絕緣層122與第二絕緣層126的厚度總和，但在其他實施例中，溝渠128的深度也可以小於第一絕緣層122與第二絕緣層126的厚度總和。
圖2A是隱藏圖1的多晶片封裝結構的線路板的上視示意圖。如圖1與圖2A所示，在本實施例中，溝渠128為一環形溝渠，且溝渠128位在第一絕緣層122與第二絕緣層126上的位置對應於第二晶片140的外輪廓，且環繞這些第二導電凸塊135。當底填膠150填充至第一晶片110與第二晶片140之間以包覆第二導電凸塊135時，多餘的底填膠150會填入溝渠128，有效地避免底填膠150向外溢流至第一導電凸塊130的機率。因此，第一導電凸塊130便不會被底填膠150污染而影響了與線路板160連接的品質。
需說明的是，上面僅顯示其中一種溝渠128的形式，但溝渠128的形狀與輪廓並不以此為限制。圖2B至圖2D是依照本發明的其他實施例的一種多晶片封裝結構的隱藏線路板的上視示意圖。為了方便了解，在圖2B至圖2D中，相同的元件以與前一實施例相同的元件編號來表示。請先參閱圖2B，溝渠128a也是一環形溝渠。本實施例的多晶片封裝結構100a的溝渠128a與前 一實施例的溝渠128的主要差異在於，在本實施例中，溝渠128a的局部區域會朝向第一導電凸塊130之間的空間凹陷，而使得溝渠128a的外輪廓上會呈現出直線與弧線交錯的輪廓，相對的，使容納溢膠之空間得以增加。
請參閱圖2C與圖2D，溝渠128b、128c可包括多個彼此分離的條形溝渠，且這些溝渠128b、128c排列成環狀以環繞這些第二導電凸塊135。更詳細地說，在圖2C中，多晶片封裝結構100b具有四個長直條形的溝渠128b，分別配置在第二導電凸塊135的四周，以排列呈矩形。在圖2D中，多晶片封裝結構100c的溝渠128c中，一部分呈長直條形，另一部分具有彎角。長直條形的溝渠128c位在第二導電凸塊135的四周而形成矩形的四邊，具有彎角的溝渠128c形成矩形的四角。當然，溝渠128、128a、128b、128c的實際形狀並不以上述為限制，只要能夠降低底填膠150向外溢流至第一導電凸塊130的機率即可。
在上面的實施例中，溝渠128、128a、128b、128c是製作在晶片附接在晶片(Chip on Chip,COC)的封裝階段中，但在其他實施例中，溝渠128、128a、128b、128c也可以製作在晶片附接在晶圓(Chip on Wafer,COW)的封裝階段。圖3是依照本發明的一實施例的一種晶圓級晶片封裝結構的示意圖。請參閱圖3，在晶圓202被切割之前，將上述的線路層120、第一導電凸塊130、第二導電凸塊135、第二晶片140、線路板160等元件配置在晶圓202上，並在晶圓202的線路層120上製作出溝渠128，而形成晶圓級 晶片封裝結構200。此晶圓級晶片封裝結構200可切割成多個上述的多晶片封裝結構100。
下面將以圖3的晶圓級晶片封裝結構200為例，詳細地介紹晶圓級晶片封裝結構200的其中一種晶圓級晶片封裝製程。圖4至圖12是製造本發明的一實施例的一種晶圓級晶片封裝結構的局部剖面示意圖。圖13是依照本發明的一實施例的一種晶圓級晶片封裝製程的流程圖。需說明的是，為了清楚顯示各元件的細節，圖4至圖12僅繪示出晶圓級晶片封裝結構200在製作過程之中的局部區域。更精確地說，圖4至圖12僅繪示出晶圓級晶片封裝結構200的其中一個多晶片封裝結構100的製作過程。並且，為了方便了解，圖4至圖12中所呈現的視角是以圖3的A-A線段的剖面來繪示。此外，在本實施例中，相似或相同的元件以與前一實施例相同的元件編號來表示。
本實施例的晶圓級晶片封裝製程300包括下列步驟：首先，如圖13的步驟310所述以及配合圖4至圖12所示，提供一晶圓202，晶圓202包括多個陣列排列的第一晶片110以及一配置於第一晶片110上的線路層120，其中各第一晶片110分別具有一晶片接合區112、多個位於晶片接合區112內的第一內接點114及多個位於晶片接合區112外的第一外接點116。線路層120包括多層絕緣層(例如是第一絕緣層122與第二絕緣層126)以及至少一設置於第一絕緣層122與第二絕緣層126之間的金屬層124。第一絕緣層122與第二絕緣層126上具有至少一溝渠128，溝渠128分佈 於這些第一內接點14與這些第一外接點116之間，且溝渠128沿這些第一內接點114的周緣設置。
詳細地說，請先參考圖4，晶圓202包括多個第一晶片110，第一晶片110具有一晶片接合區112、多個位於晶片接合區112內的第一內接點114以及多個位於晶片接合區112外之第一外接點116。一開始可選擇性地對晶圓202進行清洗(Incoming Clean)的步驟，透過例如是高壓水柱清洗的方式來移除第一晶片110表面的髒污。當然，在其他實施例中，也可以選擇不對晶圓202進行清洗。
接著，如圖5所示，在第一晶片110上形成圖案化的一第一絕緣層122。詳細地說，可先在第一晶片110上塗佈一絕緣層，該絕緣層之材料可為一般之感光性光阻材料、聚醯亞胺(PI)層或是氮化矽(silicon nitride,Si3N4)，再罩設一光罩(未繪示)在絕緣層，並且進行曝光(Exposure)的程序，其中光罩的圖案對應於所欲露出的第一晶片的圖案。之後進行顯影(Develop)的程序，以顯影液將未曝光的絕緣層溶解並移除。接著，透過加熱的方式固化(Curing)未被移除的絕緣層，再透過例如是氧氣電漿的方式對固化的絕緣層進行表面處理，即可完成第一絕緣層122。
如圖5所示，第一絕緣層122配置於這些第一晶片110上，第一絕緣層122暴露出這些第一內接點114以及這些第一外接點116，且第一絕緣層122具有一凹溝122a。凹溝122a位在對應於第一內接點114及第一外接點116之間的位置，且圍繞第一 內接點114。在本實施例中，凹溝的深度等於第一絕緣層122的厚度，但在其他實施例中，凹溝的深度也可以小於第一絕緣層122的厚度。
再來，如圖6所示，沉積一介質金屬層(UBM Deposition)12。在本實施例中，先透過氬氣去移除第一絕緣層122、第一內接點114與第一外接點116上的氧化物。接著，在第一絕緣層122、第一內接點114與第一外接點116上依序濺鍍鈦鎢層、金層與鈦層，以形成介質金屬層12，其中介質金屬層12也會形成在第一絕緣層122的凹溝122a內。
接著，如圖7所示，形成圖案化的一光阻層14與一線路層124。詳細地說，在本實施例中，先在圖6的介質金屬層12上塗佈光阻，再進行曝光的程序。使光阻層14上對應於第一內接點114與第一外接點116之區域形成開孔後再進行一道電鍍製程，而於該曝露的開孔中形成金屬層124。接著，移除光阻層14及未被金屬層124覆蓋之介質金屬層12，而留下了金屬層124。如圖8所示，該金屬層124可向外延伸成為一重佈線路層(RDL)，而配置於第一絕緣層122上並與這些第一內接點114電性連接。
於其它實施例中，該光阻層14之開孔亦可對應第一絕緣層122之凹溝122a形成較小區域之孔徑，於進行電鍍製程時，將於開孔中原向外延伸之金屬層124對應該第一內接點114而縮小範圍形成柱狀之金屬層。
其後，如圖9所示，形成圖案化的一第二絕緣層126。在 本實施例中，第二絕緣層126的材質例如為聚醯亞胺，如同第一絕緣層122的形成方式，透過曝光顯影等步驟形成第二絕緣層126。第二絕緣層126覆蓋於第一絕緣層122以及金屬層124上，並暴露出部分的金屬層124以及這些第一外接點116。其中，第二絕緣層126上更具有一穿槽126a，第二絕緣層126的穿槽126a的位置對應於第一絕緣層122的凹溝122a的位置。在本實施例中，穿槽126a與凹溝122a共同形成溝渠。形成該溝渠128的方法(也就是第一絕緣層122的凹溝122a與第二絕緣層126穿槽126a的形成方法)包括黃光製程、雷射加工或反應離子蝕刻(RIE)。
在本實施例中，溝渠128位於第一絕緣層122與第二絕緣層126中，第一絕緣層122的凹溝122a的深度等於第一絕緣層122的厚度，且第二絕緣層126的穿槽126a的深度等於第二絕緣層126的厚度，而使得溝渠128的深度等於第一絕緣層122與第二絕緣層126的厚度總和。但在其他實施例中，第一絕緣層122的凹溝122a的深度也可以小於第一絕緣層122的厚度，而使得溝渠128的深度小於第一絕緣層122與第二絕緣層126的厚度總和。或者，在其他實施例中，溝渠128也可以只位在第二絕緣層126中。也就是說，第一絕緣層122並不存在凹溝122a。第二絕緣層126也可以只具有未穿透的凹陷溝槽，而非穿透的穿槽126a。
在本實施例中，透過圖4至圖9的程序完成了步驟310。再來，如圖10所示，於這些第一外接點116上形成多個第一導電凸塊130(步驟320)。形成的方式可包括植球、電鍍、印刷等方式 後迴焊成型。
接著，如圖11所示，提供第二晶片140，第二晶片140具有多個第二接點142，且這些第二接點142上形成有多個第二導電凸塊135(步驟330)。第一導電凸塊130與第二導電凸塊135的材質包括單一金屬元素或合金，其材質可為含鉛材料(例如鉛或錫鉛合金)或無鉛材料，其包括金、銀、銅、錫、鎳或其合金。於本發明圖式中，係列舉為球狀為例，然而，其外觀形狀不僅可成型為球狀、圓柱狀或圓頂柱狀，其所選用之材料亦可採用單一種金屬材料或採用兩種或兩種以上之金屬材料電鍍成型，例如，銅柱(Copper Pillar)上形成一層錫(Solder Cap)，或銅柱外壁覆蓋一層金，均為本發明之可行之導電凸塊。
將第二晶片140覆設於晶片接合區112上，以使這些第二導電凸塊135位於這些第一內接點114與這些第二接點142之間，且各第一內接點114分別透過對應的第二導電凸塊135而與對應的第二接點142電性連接(步驟340)，其中這些第二導電凸塊135透過金屬層124與這些第一內接點114電性連接。
接著，於第一晶片110與第二晶片140之間形成一底填膠150，以包覆這些第二導電凸塊135(步驟350)。
最後，如圖12所示，進行一晶圓切割步驟，以使這些第一晶片110彼此分離而形成多個多晶片封裝結構100(步驟360)，接下來，再使這些單離化之多晶片封裝結構100以這些第一導電凸塊130電性連接至一線路板160，其中第二晶片140、這些第一 導電凸塊130以及這些第二導電凸塊135位於線路板160與第一晶片110之間(步驟370)。在本實施例的步驟340與步驟370中，可透過一迴焊作業來使第二導電凸塊135連接至金屬層124以及第一導電凸塊130連接至線路板160。值得一提的是，該迴焊作業可針對該第一導電凸塊130與第二導電凸塊135同時加熱迴焊，亦可先就第二導電凸塊135迴焊連接於第一晶片110上，再進行第二次迴焊作業，使第一導電凸塊130連接於線路板160上，於實施作業上該迴焊作業可隨製程不同而作調整。
再次說明的是，圖4至圖12僅繪示出晶圓級晶片封裝結構200的其中一部分，因此，在圖12中顯示出一個多晶片封裝結構100，實際上，若以圖3的角度觀之，則可切割出多個多晶片封裝結構100。
此外，雖然在本實施例中是先在這些第一外接點116上形成多個第一導電凸塊130(步驟320)之後，再將第二晶片140覆設於晶片接合區112上(步驟330、340)。但在其他實施例中，也可以是先將第二晶片140覆設於晶片接合區112上，以使第二導電凸塊135連接至第一內接點114(步驟330、340)，再在這些第一外接點116上形成多個第一導電凸塊130(步驟320)，製程順序上可視需求而調整。
綜上所述，本發明的多晶片封裝結構與晶圓級晶片封裝結構藉由在線路層的這些絕緣層上形成溝渠，溝渠分佈於這些第一內接點與這些第一外接點之間且沿著這些第一內接點周緣設 置，來使第一晶片與第二晶片之間的多餘的底填膠溢流時能夠流入溝渠，以避免沾附到第一導電凸塊，而影響第一導電凸塊與線路板之間的電性連接品質。本發明更提供上述晶圓級晶片封裝結構的製程，而能夠製作出底填膠不會流至第一導電凸塊的晶圓級晶片封裝結構。並且，此晶圓級晶片封裝結構透過晶圓切割程序，便可形成多個上述的多晶片封裝結構。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧多晶片封裝結構
110‧‧‧第一晶片
112‧‧‧晶片接合區
114‧‧‧第一內接點
116‧‧‧第一外接點
120‧‧‧線路層
122‧‧‧第一絕緣層
124‧‧‧金屬層
126‧‧‧第二絕緣層
128‧‧‧溝渠
130‧‧‧第一導電凸塊
135‧‧‧第二導電凸塊
140‧‧‧第二晶片
142‧‧‧第二接點
150‧‧‧底填膠
160‧‧‧線路板

Claims (20)

  1. 一種多晶片封裝結構，包括：一第一晶片，具有一晶片接合區、多個位於該晶片接合區內的第一內接點以及多個位於該晶片接合區外之第一外接點；一線路層，配置於該第一晶片上，該線路層包括多層絕緣層以及至少一設置於該些絕緣層之間的金屬層，該些絕緣層上具有至少一道溝渠，該溝渠分佈於該些第一內接點與該些第一外接點之間，且該溝渠沿著該些第一內接點周緣設置；多個第一導電凸塊，配置於該些第一外接點上；一第二晶片，覆置於(flip on)該晶片接合區上，且該第二晶片具有多個第二接點；多個第二導電凸塊，位於該些第一內接點與該些第二接點之間，各該第一內接點分別透過對應的該第二導電凸塊與對應的該第二接點電性連接；以及一底填膠，位於該第一晶片與該第二晶片之間以包覆該些第二導電凸塊。
  2. 如申請專利範圍第1項所述的多晶片封裝結構，其中該第一晶片的尺寸大於該第二晶片的尺寸。
  3. 如申請專利範圍第1項所述的多晶片封裝結構，其中該線路層的該些絕緣層包括：一第一絕緣層，配置於該第一晶片上並且暴露出該些第一內接點以及該些第一外接點；以及 一第二絕緣層，覆蓋於該第一絕緣層上，其中該金屬層設置於該第一絕緣層與該第二絕緣層之間，且該第二絕緣層暴露出部分的該金屬層以及該些第一外接點，其中該些第二導電凸塊透過該金屬層與該些第一內接點電性連接。
  4. 如申請專利範圍第3項所述的多晶片封裝結構，其中該溝渠位於該第一絕緣層與該第二絕緣層中，且該溝渠的深度等於或小於該第一絕緣層與該第二絕緣層的厚度總和。
  5. 如申請專利範圍第1項所述的多晶片封裝結構，更包括一線路板，其中該線路板與該些第一導電凸塊電性連接，且該第二晶片、該些第一導電凸塊以及該些第二導電凸塊位於該線路板與該第一晶片之間。
  6. 如申請專利範圍第1項所述的多晶片封裝結構，其中各該第一導電凸塊的高度大於各該第二導電凸塊的高度。
  7. 如申請專利範圍第1項所述的多晶片封裝結構，其中該溝渠包括環形溝渠，且該溝渠環繞於該些第一內接點之周緣。
  8. 如申請專利範圍第1項所述的多晶片封裝結構，其中該溝渠包括多個彼此分離的條形溝渠，且該些條形溝渠排列成環狀以環繞該些第一內接點。
  9. 一種晶圓級晶片封裝製程，包括：提供一晶圓，該晶圓包括多個陣列排列的第一晶片以及一配置於該第一晶片上的線路層，其中各該第一晶片分別具有一晶片接合區、多個位於該晶片接合區內的第一內接點及多個位於該晶 片接合區外的第一外接點，該線路層包括多層絕緣層以及至少一設置於該些絕緣層之間的金屬層，該絕緣層上具有至少一溝渠，該溝渠分佈於該些第一內接點與該些第一外接點之間，且該溝渠沿該些第一內接點周緣設置；於該些第一外接點上形成多個第一導電凸塊；提供多個第二晶片，各該第二晶片分別具有多個第二接點，且該些第二接點上形成有多個第二導電凸塊；將該些第二晶片覆設於該些晶片接合區上，以使該些第二導電凸塊位於該些第一內接點與該些第二接點之間，且各該第一內接點分別透過對應的該第二導電凸塊而與對應的該第二接點電性連接；以及於該第一晶片與該第二晶片之間形成一底填膠，以包覆該些第二導電凸塊。
  10. 如申請專利範圍第9項所述的晶圓級晶片封裝製程，其中各該第一晶片的尺寸大於各該第二晶片的尺寸。
  11. 如申請專利範圍第9項所述的晶圓級晶片封裝製程，其中將該些第二晶片覆設於該些晶片接合區之前，於該些第一外接墊上形成該些第一導電凸塊。
  12. 如申請專利範圍第9項所述的晶圓級晶片封裝製程，更包括一線路板，其中該線路板與該些第二導電凸塊電性連接，且該第二晶片、該些第一導電凸塊以及該些第二導電凸塊位於該線路板與該第一晶片之間。
  13. 如申請專利範圍第9項所述的晶圓級晶片封裝製程，其中該線路層的該些絕緣層包括：一第一絕緣層，配置於該第一晶片上並且暴露出該些第一內接點以及該些第一外接點；以及一第二絕緣層，覆蓋於該第一絕緣層上，其中該金屬層設置於該第一絕緣層與該第二絕緣層之間，且該第二絕緣層暴露出部分的該金屬層以及該些第一外接點，其中該些第二導電凸塊透過該金屬層與該些第一內接點電性連接。
  14. 如申請專利範圍第13項所述的晶圓級晶片封裝製程，其中該溝渠位於該第一絕緣層與該第二絕緣層中，且該溝渠的深度等於或小於該第一絕緣層與該第二絕緣層的厚度總和。
  15. 如申請專利範圍第9項所述的晶圓級晶片封裝製程，其進一步包括：一晶圓切割步驟，使該些第一晶片彼此分離而形成多個多晶片封裝結構。
  16. 一種晶圓級晶片封裝結構，包括：一晶圓，包括多個陣列排列的第一晶片以及一配置於該第一晶片上的線路層，其中各該第一晶片分別具有一晶片接合區、多個位於該晶片接合區內的第一內接點及多個位於該晶片接合區外的第一外接點，該線路層包括多層絕緣層以及至少一設置於該些絕緣層之間的重佈線路層，該重佈線路層具有多個位於該些絕緣層中的溝渠，該些溝渠分佈於該些第一內接點與該些第一外接點 之間，且該些溝渠沿著該些第一內接點周緣設置；多個第一導電凸塊，配置於該些第一外接點上；多個第二晶片，覆置於該些晶片接合區上，且各該第二晶片具有多個第二接點；多個第二導電凸塊，位於該些第一內接點與該些第二接點之間，各該第一內接點分別透過對應的該第二導電凸塊與對應的該第二接點電性連接；以及一底填膠，位於該些第一晶片與該些第二晶片之間以包覆該些第二導電凸塊。
  17. 如申請專利範圍第16項所述的晶圓級晶片封裝結構，其中各該第一晶片的尺寸大於各該第二晶片的尺寸。
  18. 如申請專利範圍第16項所述的晶圓級晶片封裝結構，其中該線路層的該些絕緣層包括：一第一絕緣層，配置於該些第一晶片上並且暴露出該些第一內接點以及該些第一外接點；以及一第二絕緣層，覆蓋於該第一絕緣層上，其中該重佈線路層設置於該第一絕緣層與該第二絕緣層之間，且該第二絕緣層暴露出部分的該重佈線路層以及該些第一外接點，其中該些第二導電凸塊透過該重佈線路層與該些第一內接點電性連接。
  19. 如申請專利範圍第18項所述的晶圓級晶片封裝結構，其中該些溝渠位於該第一絕緣層與該第二絕緣層中，且該些溝渠的深度等於或小於該第一絕緣層與該第二絕緣層的厚度總和。
  20. 如申請專利範圍第16項所述的晶圓級晶片封裝結構，其中各該第一導電凸塊的高度大於各該第二導電凸塊的高度。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI766280B (zh) * 2020-05-14 2022-06-01 南茂科技股份有限公司 晶圓級晶片尺寸封裝結構及其製造方法

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI582903B (zh) * 2015-12-02 2017-05-11 南茂科技股份有限公司 半導體封裝結構及其製作方法
TWI582921B (zh) * 2015-12-02 2017-05-11 南茂科技股份有限公司 半導體封裝結構及其製作方法
KR20170065397A (ko) * 2015-12-03 2017-06-13 삼성전자주식회사 반도체 장치
US11676929B2 (en) 2016-10-21 2023-06-13 Sony Semiconductor Solutions Corporation Electronic substrate and electronic apparatus
JP6946316B2 (ja) * 2016-10-21 2021-10-06 ソニーセミコンダクタソリューションズ株式会社 電子基板、および電子装置
US20180226271A1 (en) * 2017-01-31 2018-08-09 Skyworks Solutions, Inc. Control of under-fill using a film during fabrication for a dual-sided ball grid array package
US10403578B2 (en) * 2017-09-30 2019-09-03 Intel Corporation Electronic device package
CN108260292A (zh) * 2017-12-08 2018-07-06 江西合力泰科技有限公司 一种smt之后增加底部填充胶覆盖率的方法
CN110416166B (zh) * 2018-04-27 2021-06-29 江苏长电科技股份有限公司 半导体封装结构及其制作方法
TWI659507B (zh) * 2018-05-18 2019-05-11 南茂科技股份有限公司 半導體封裝結構及其製造方法
CN111377394B (zh) * 2018-12-27 2023-08-25 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN110579516A (zh) * 2019-09-02 2019-12-17 青岛歌尔智能传感器有限公司 二氧化氮气体检测器件及其制作方法、以及电子产品
CN112445446B (zh) * 2019-09-05 2022-11-15 芯盟科技有限公司 半导体结构及其形成方法和芯片及其形成方法
KR20210041929A (ko) 2019-10-08 2021-04-16 삼성전자주식회사 웨이퍼 레벨 패키지
TWI701777B (zh) 2019-10-22 2020-08-11 財團法人工業技術研究院 影像感測器封裝件及其製造方法
CN111128910B (zh) * 2019-12-10 2022-04-15 深圳宏芯宇电子股份有限公司 芯片堆叠封装方法及芯片堆叠结构
TWI713166B (zh) * 2020-02-17 2020-12-11 頎邦科技股份有限公司 晶片封裝構造及其電路板
CN112234050A (zh) * 2020-09-22 2021-01-15 江苏盐芯微电子有限公司 多芯片集成电路封装结构
US20230066598A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming the same
CN115831897A (zh) * 2021-09-17 2023-03-21 长鑫存储技术有限公司 芯片封装结构及制备方法、半导体结构的封装方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291264B1 (en) * 2000-07-31 2001-09-18 Siliconware Precision Industries Co., Ltd. Flip-chip package structure and method of fabricating the same
JP4505983B2 (ja) * 2000-12-01 2010-07-21 日本電気株式会社 半導体装置
CN1315168C (zh) * 2002-01-30 2007-05-09 威盛电子股份有限公司 晶圆级封装制作工艺及其晶片结构
US6936929B1 (en) * 2003-03-17 2005-08-30 National Semiconductor Corporation Multichip packages with exposed dice
TWI313048B (en) * 2003-07-24 2009-08-01 Via Tech Inc Multi-chip package
US7359211B2 (en) * 2004-03-02 2008-04-15 Intel Corporation Local control of underfill flow on high density packages, packages and systems made therewith, and methods of making same
JP4291209B2 (ja) * 2004-05-20 2009-07-08 エルピーダメモリ株式会社 半導体装置の製造方法
US7179683B2 (en) * 2004-08-25 2007-02-20 Intel Corporation Substrate grooves to reduce underfill fillet bridging
JP4581768B2 (ja) * 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
US7851925B2 (en) * 2008-09-19 2010-12-14 Infineon Technologies Ag Wafer level packaged MEMS integrated circuit
KR101332916B1 (ko) * 2011-12-29 2013-11-26 주식회사 네패스 반도체 패키지 및 그 제조 방법
JP2015119077A (ja) * 2013-12-19 2015-06-25 ソニー株式会社 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI766280B (zh) * 2020-05-14 2022-06-01 南茂科技股份有限公司 晶圓級晶片尺寸封裝結構及其製造方法

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