WO2023040144A1 - 芯片封装结构及制备方法、半导体结构的封装方法 - Google Patents

芯片封装结构及制备方法、半导体结构的封装方法 Download PDF

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Publication number
WO2023040144A1
WO2023040144A1 PCT/CN2022/071277 CN2022071277W WO2023040144A1 WO 2023040144 A1 WO2023040144 A1 WO 2023040144A1 CN 2022071277 W CN2022071277 W CN 2022071277W WO 2023040144 A1 WO2023040144 A1 WO 2023040144A1
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Prior art keywords
chip
conductive
insulating layer
intermediate insulating
packaging structure
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PCT/CN2022/071277
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English (en)
French (fr)
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范增焰
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长鑫存储技术有限公司
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Priority to US18/169,303 priority Critical patent/US20230197666A1/en
Publication of WO2023040144A1 publication Critical patent/WO2023040144A1/zh

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    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract

本申请提供一种芯片封装结构及制备方法、半导体结构的封装方法，涉及半导体技术领域，解决芯片的良率低的技术问题，该芯片封装结构包括芯片、设置在芯片上的中间绝缘层和设置在中间绝缘层上的非导电胶层；所述芯片上设有多个导电凸柱，各所述导电凸柱贯穿中间绝缘层；中间绝缘层设有至少一组容纳孔，非导电胶层填充容纳孔，以使非导电胶层背离中间绝缘层的表面上形成有与容纳孔相匹配的凹槽；非导电胶层中的部分非导电胶在第一预设温度和预设压力下溢出非导电胶层并流动填充至凹槽内，以避免非导电胶溢出芯片边缘，从而提高了芯片的良率。

Description

芯片封装结构及制备方法、半导体结构的封装方法
本申请要求于2021年09月17日提交中国专利局、申请号为202111091950.6、申请名称为“芯片封装结构及制备方法、半导体结构的封装方法”的中国专利申请的优先权，其全部内部通过引用结合在本申请中。
技术领域
本申请涉及封装技术领域，尤其涉及一种芯片封装结构及制备方法、半导体结构的封装方法。
背景技术
芯片封装结构中随着输入/输出(input/output，I/O)引脚数量的增加，在芯片尺寸缩小或者缩小芯片尺寸的情况下，芯片的功能凸点的间距(bump pitch)也越来越小，导致采用普通的毛细管底部填充工艺无法填充到芯片内部以保护电极焊盘。
针对上述问题，一般采用热压键合工艺，先在基板上预涂覆非导电胶，然后在基板上倒装半导体芯片并热压键合焊接，以解决普通的毛细管底部填充工艺中填充困难以及虚焊等问题。
然而，非导电胶在热压键合时，非导电胶易溢出芯片的边缘，导致芯片的良率低。
发明内容
鉴于上述问题，本申请实施例提供一种芯片封装结构及制备方法、半导体结构的封装方法，能够提高芯片的良率。
为了实现上述目的，本申请实施例提供如下技术方案：
第一方面，本申请实施例提供一种芯片封装结构，其包括：芯片、设置在所述芯片上的中间绝缘层和设置在所述中间绝缘层上的非导电胶层；所述芯片上设有多个导电凸柱，各所述导电凸柱贯穿所述中间绝缘层；所述中间绝缘层设有至少一组容纳孔，所述非导电胶层填充所述容纳孔，以使所述非导电胶层背离所述中间绝缘层的表面上形成有与所述容纳孔相匹配的凹槽。
与相关技术相比，本申请实施例提供的芯片封装结构，至少具有如下优点：
本申请实施例提供的芯片封装结构中，通过在芯片上设置中间绝缘层，中间绝缘层上设有至少一组容纳孔，在中间绝缘层上形成非导电胶层时，非导电胶层中与各容纳孔相对应的部分非导电胶会先填充容纳孔，这样，非导电胶层背离中间绝缘层的表面上会形成与容纳孔相匹配的凹槽，芯片封装结构在封装过程中，非导电胶层中的部分非导电胶在第一预设温度和预设压力下溢出非导电胶层的表面并流动填充至凹槽内，这样，可以避免溢出非导电胶层的部分非导电胶从芯片的边缘溢出，从而能够提高芯片的良率。
第二方面，本申请实施例提供一种芯片封装结构的制备方法，其包括：提供芯片；在所述芯片上形成中间绝缘层；在所述中间绝缘层上形成至少一组容纳孔和暴露所述芯片中电路层的多个凹陷；在各所述凹陷中形成多个导电凸柱，其中，所述导电凸柱远离所述 芯片的一端具有焊接部，所述焊接部为向远离所述导电凸柱一侧弯曲的弧形面；在所述中间绝缘层上形成非导电胶层，所述非导电胶层填充所述容纳孔，以在所述非导电胶背离所述中间绝缘层的表面上形成与所述容纳孔相匹配的凹槽。
第三方面，本申请实施例提供一种半导体结构的封装方法，其包括：
提供一基板，基板上设有多个焊盘；提供第一方面的芯片封装结构，所述芯片封装结构具有多个与各焊盘相对应的导电凸柱；将所述芯片封装结构倒装在所述基板上，以使所述芯片封装结构上的各导电凸柱与所述基板上的各焊盘一一对应；提供压力设备，所述压力设备位于所述芯片封装结构的上方；所述压力设备向所述芯片封装结构提供第一预设温度和预设压力；以使所述芯片封装结构上的各导电凸柱与其对应的所述基板上的所述焊盘键合并电导通。
本申请实施例提供的芯片封装结构的制备方法、半导体结构的封装方法具有与芯片封装结构相同的有益效果，在此，不再一一进行赘述。
除了上面所描述的本申请实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本申请实施例提供的芯片封装结构及制备方法、半导体结构的封装方法所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中芯片封装结构和基板热压键合后的结构示意图；
图2为本申请实施例中芯片封装结构的结构示意图；
图3为本申请实施例中芯片和中间绝缘层的俯视示意图；
图4为本申请实施例中芯片封装结构的制备方法的流程示意图；
图5为本申请实施例中在芯片上形成中间绝缘层的结构示意图；
图6为本申请实施例中在中间绝缘层上形成容纳孔的结构示意图；
图7为本申请实施例中在中间绝缘层上形成掩膜层的结构示意图；
图8为本申请实施例中图案化掩膜层的结构示意图；
图9为本申请实施例中形成导电凸柱的结构示意图；
图10为本申请实施例中去除掩膜层的结构示意图；
图11为本申请实施例中对导电凸柱回流后的结构示意图；
图12为本申请另一实施例中半导体结构的封装方法的流程示意图；
图13为本申请另一实施例中芯片封装结构和基板热压键合过程中的结构示意图；
图14为本申请另一实施例中芯片封装结构和基板热压键合后的结构示意图；
图15为本申请另一实施例中芯片和基板封装后形成封装后的芯片的结构示意图。
附图标记：
100-芯片封装结构；                       101-芯片；
1011-金属布线层；                        102-中间绝缘层；
103-非导电胶层；                         1031-凹槽；
104-导电柱；                             1041-焊接部；
104a-导电凸柱；                          104b-支撑柱；
105-容纳孔；                             1051-第一容纳孔；
1052-第二容纳孔；                        106-排气通道；
107-掩膜层；                             1071-凹陷；
200-基板；                               201-焊盘；
300-压力设备；                           400-焊球；
500-塑封层。
具体实施方式
在相关技术中，如图1所示，芯片封装结构100上设有导电凸柱104a，基板200上设有焊盘，当芯片封装结构100和基板200热压键合时，通常先在基板200上涂覆一层一定厚度的非导电胶，这样，当芯片封装结构100倒装在基板200上并与基板200热压键合时，非导电胶填充基板200上的毛细管，以解决毛细管底部无法填充到芯片101内部以及虚焊的问题，然而，当芯片封装结构和基板通过热压键合时，非导电胶会因受挤压而溢出芯片的侧面，导致芯片的良率低的问题。
为了解决上述问题，本申请实施例提供一种芯片封装结构及制备方法、半导体结构的封装方法，在芯片封装结构中，通过在芯片上设置中间绝缘层，中间绝缘层上设有至少一组容纳孔，在中间绝缘层上形成非导电胶层时，非导电胶层中与各容纳孔相对应的部分非导电胶会先填充容纳孔，这样，非导电胶层背离中间绝缘层的表面上会形成与容纳孔相匹配的凹槽，芯片封装结构在封装过程中，非导电胶层中的部分非导电胶在第一预设温度和预设压力下溢出非导电胶层的表面并流动填充至凹槽内，这样，可以避免溢出非导电胶层的部分非导电胶从芯片的边缘溢出，从而能够提高芯片的良率。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
图2为本申请实施例中芯片封装结构的结构示意图；图3为本申请实施例中芯片和中间绝缘层的俯视示意图。
如图2和图3所示，本申请实施例提供的芯片封装结构100，其包括：芯片101、设置在芯片101上的中间绝缘层102和设置在中间绝缘层102上的非导电胶层103；芯片101上设有多个导电凸柱104a，各导电凸柱104a贯穿中间绝缘层102；中间绝缘层102设有至少一组容纳孔105，非导电胶层103填充容纳孔105，以使非导电胶层103背离中间绝缘层102的表面上形成有与容纳孔105相匹配的凹槽1031。
可以理解的是，当非导电胶层103在第一预设温度和预设压力下，部分非导电胶具有流动性，会溢出非导电胶层103的表面，由于非导电胶层103的表面具有凹槽1031，因此，当部分非导电胶溢出非导电胶层103的表面时，溢出的非导电胶会在非导电胶层103的表面流动以填充至凹槽1031内，这样，可以避免非导电胶溢出芯片的边缘，从而提高芯片的良率。
其中，第一预设温度指的是能够使非导电胶由固态转换为液态的温度，以使非导电胶具有流动性和粘结性；而预设压力指的是芯片封装结构100在与基板等结构进行封装时所需的压力。
示例性的，非导电胶层103可以是热固性树脂、树胶、合成树脂等，而中间绝缘层102可以光刻胶层等，对此，本实施例不做具体限制。
在具体实现时，当将芯片封装结构100与基板等结构进行封装时，非导电胶在第一预设温度和预设压力下，部分非导电胶会溢出非导电胶层103的表面，溢出的非导 电胶会流动至非导电胶层103表面上的凹槽1031内，这样，可以避免溢出非导电胶层103的非导电胶从芯片101的边缘溢出，从而能够提高芯片101的良率。
可以理解的是，非导电胶层103上形成的凹槽1031是用于收容溢出非导电胶层103表面的部分非导电胶，避免溢出的非导电胶从芯片101的边缘溢出。
因此，在本申请实施例中，通过在芯片101上设置中间绝缘层102，中间绝缘层102上设有至少一组容纳孔105，在中间绝缘层102上形成非导电胶层103时，非导电胶层103中与各容纳孔105相对应的部分非导电胶会先填充容纳孔105，这样，非导电胶层103背离中间绝缘层102的表面上会形成与容纳孔105相匹配的凹槽1031，芯片封装结构100在封装过程中，非导电胶层103中的部分非导电胶在第一预设温度和预设压力下溢出非导电胶层103的表面并流动填充至凹槽1031内，这样，可以避免溢出非导电胶层103的部分非导电胶从芯片的边缘溢出，从而能够提高芯片的良率。
继续参见图2和图3所示，多个导电凸柱104a形成至少一组导电凸柱组，且各导电凸柱104a设置在芯片101上并与芯片101中的金属布线层1011电连接，而各导电凸柱104a远离芯片101的一端贯穿中间绝缘层102，以便后续导电凸柱104a与基板上的焊盘焊接以实现电导通；另外，芯片封装结构还包括多个支撑柱104b，多个支撑柱104b形成至少一组支撑柱组，且各支撑柱104b分别间隔设置在中间绝缘层102上，可以理解的是，当芯片封装结构100倒装在基板上时，支撑柱104b主要用于支撑芯片101。
可以理解的是，导电凸柱104a的材质包括锡、铜、铝、镍、金、银、钛中的一种或者几种的组合。
在靠近导电凸柱104a和支撑柱104b的边缘设置有多组容纳孔105，在非导电胶层103上形成多个与容纳孔105相匹配的凹槽1031，当芯片封装结构100受到预设挤压力时，各导电凸柱104a以及支撑柱104b与基板等结构上的焊盘201之间的非导电胶会受挤压溢出，而该溢出的导电胶会先填充在导电凸柱104a和支撑柱104b边缘的凹槽1031内，从而避免导电胶溢出芯片101的边缘，进而提高芯片101的良率。
其中，导电凸柱组中各导电凸柱104a排布形成的图案，与支凸柱组中各支撑柱104b排布形成的图案不同；例如，导电凸柱组形成长度方向沿第一方向延伸的矩形，而支撑柱组形成长度方向沿第二方向延伸的矩形，其中，第一方向和第二方向可以在水平面内垂直。
而每组容纳孔105包括相连通的第一容纳孔1051和第二容纳孔1052，第一容纳孔1051设置于导电凸柱组的一侧，第二容纳孔1052设置于支撑柱组的一侧，这样，在非导电胶层103上分别与第一容纳孔1051和第二容纳孔1052相对应的位置处，会形成分别与第一容纳孔1051和第二容纳孔1052相匹配的凹槽1031，当芯片封装结构100与基板进行封装时，导电凸柱组附近的凹槽1031可以收容导电凸柱组附近因挤压溢出的非导电胶，支撑柱组附近的凹槽1031可以收容支撑柱组附近因挤压溢出的非导电胶，从而避免非导电胶溢出芯片101边缘，进而提高芯片101的良率。
优选的，继续参照图10所示，第一容纳孔1051的图案可以与导电凸柱组中各导电凸柱104a排布的图案相匹配，这样，在非导电胶层103上的形成的凹槽1031也与导电凸柱组的排布图案相匹配；第二容纳孔1052的图案与支撑柱组中各支撑柱104b排布的图案相匹配，这样，在非导电胶层103上形成的凹槽1031也与支撑柱组的排布图案相匹配。
示例性的，导电凸柱组中的各导电凸柱104a排布形成矩形，因此，第一容纳孔1051的图案也为与该矩形的形状和大小相匹配的矩形，在非导电胶层103上形成的与第一容纳孔1051相匹配的凹槽1031也为矩形，以便于能够更好的将导电凸柱组附近溢出的非导电胶进行收容，避免非导电胶溢出芯片101的边缘；当然，当支撑柱组中 的各支撑柱104b排布形成矩形，因此，第二容纳孔1052的图案也为与该矩形的形状和大小相匹配的矩形，在非导电胶层103上形成的与第二容纳孔1052相匹配的凹槽1031也为矩形，以便于能够更好的将支撑柱组附近溢出的非导电胶进行收容，避免非导电胶溢出芯片101的边缘。
在本申请实施例中，第一容纳孔1051至与第一容纳孔1051相对应的各导电凸柱104a的边缘的距离可以为9～11μm，优选的，第一容纳孔1051至与第一容纳孔1051相对应的各导电凸柱104a的边缘的距离为10μm；这样，在非导电胶层103上形成的与第一容纳孔1051相匹配的凹槽1031距离导电凸柱104a的边缘也为9～11μm，以便于与导电凸柱104a相对应的非导电胶在受挤压溢出时，溢出的非导电胶能够填充在凹槽1031内，从而避免非导电胶溢出芯片101边缘，进而提高芯片101的良率。
第二容纳孔1052至第二容纳孔1052相对应的各支撑柱104b的边缘的距离可以为9～11μm，优选的，第二容纳孔1052至第二容纳孔1052相对应的各支撑柱104b的边缘的距离为10μm，这样，在非导电胶层103上形成的与第二容纳孔1052相匹配的凹槽1031距离支撑柱104b的边缘也为9～11μm，以便于与支撑柱104b相对应的非导电胶在受挤压溢出时，溢出的非导电胶能够填充在凹槽1031内，从而避免非导电胶溢出芯片101边缘，进而提高芯片101的良率。
导电凸柱组为至少两组，至少两组导电凸柱组在芯片101上间隔排布，一组导电凸柱组对应一个第一容纳孔1051；支撑柱组为至少两组，至少两组支撑柱组在芯片101上间隔排布，一组支撑柱组对应一个第二容纳孔1052，这样，非导电胶层103上会形成分别与第一容纳孔1051和第二容纳孔1052相匹配的凹槽1031，导电凸柱组附近溢出的非导电胶则填充在与导电凸柱组对应的凹槽1031内，而支撑柱组附近溢出的非导电胶则填充在与支撑柱组对应的凹槽1031内，以避免非导电胶溢出芯片101边缘，从而提高芯片101良率。
继续参见图3所示，中间绝缘层102设有与容纳孔105连通的排气通道106，其中，一组容纳孔105对应一个排气通道106，各排气通道106延伸至中间绝缘层102的边缘并与外界连通。
通过在中间绝缘层102中设置与容纳孔105连通的排气通道106，这样，非导电胶层103在形成时或者芯片封装结构100与基板封装时，容纳孔105中的空气以及非导电胶中的气泡可以从排气通道106中排出。
容纳孔105在中间绝缘层102上投影的面积之和，为芯片封装结构100上所有的导电凸柱104a和所有的支撑柱104b在中间绝缘层102上投影的面积之和的3.5～4倍。
可以理解的是，在非导电胶层103中形成的与容纳孔105相对应的凹槽1031的面积在中间绝缘层102上投影的面积，为芯片101上所有导电凸柱104a和所有的支撑柱104b在中间绝缘层102上投影面积的3.5～4倍，这样，增大了凹槽1031对导电凸柱104a附近溢出的非导电胶的收容性，避免非导电胶溢出芯片101的边缘，从而提高芯片101的良率。
中间绝缘层102的厚度为4.5～5μm，这样，可以使在非导电胶层103上形成的凹槽1031的深度适中，避免凹槽1031的深度太深而使非导电胶层103的表面凸凹不平，也可以避免凹槽1031的深度太浅而导致部分非导电胶溢出芯片101边缘。
可以理解的是，导电凸柱104a和支撑柱104b分别包括导电柱104和设置在导电柱104上的焊接部1041，其中，位于金属布线层1011上的导电柱104和焊接部1041形成导电凸柱104a，导电凸柱104a与金属布线层1011电连接，而位于中间绝缘层上的导电柱104和位于导电柱104上的焊接部1041形成支撑柱104b，主要用于支撑芯片等器件。
可以理解的是，导电凸柱104a和支撑柱104b可以通过一体工艺形成，以减少加工工序，降低加工成本。
其中，焊接部1041为向远离导电柱104一侧弯曲的弧形面，通过将焊接部1041设置为弧形面，以便于导电凸柱104a与基板等结构上的焊盘抵接并电导通。
可以理解的是，焊接部1041为圆弧形面，也可以为椭圆形弧形面，对此，本实施例不做具体限制。
图4为本申请实施例中芯片封装结构的制备方法的流程示意图。
如图4所示，本申请实施例还提供一种芯片封装结构的制备方法，其包括：
步骤S101：提供芯片。
如图5所示，芯片101包括硅基底和设置在硅基底上的介质层，介质层上具有暴露硅基底的开口，开口中形成有导电层，介质层包括聚酰亚胺或高分子材料，介质层能够起到绝缘、缓冲的作用，避免芯片101受损。
步骤S102：在芯片上形成中间绝缘层。
继续参见图5所示，在介质层和开口上形成有中间绝缘层102，其中，中间绝缘层102可以是通过在介质层和开口上通过涂布的方式形成的光刻胶层。
步骤S103：在中间绝缘层上形成至少一组容纳孔和暴露芯片中金属布线层的多个凹陷。
其具体包括：图案化中间绝缘层，在中间绝缘层上形成第一图案组。另外，还可以同时在中间绝缘层上形成第二图案组。
如图6所示，按照第一图案组去除中间绝缘层102，形成至少一组容纳孔105；按照第二图案组去除中间绝缘层102和部分芯片101，暴露芯片101中的金属布线层，形成多个凹陷1071。
其中，凹陷1071的截面形状可以与其对应的导电凸柱104a的截面形状相匹配。
步骤S104：在各凹陷中形成多个导电凸柱，其中，导电凸柱远离芯片的一端具有焊接部，焊接部为向远离导电凸柱的一侧弯曲的弧形面。
在中间绝缘层上形成多个凹陷后，在各凹陷中形成导电凸柱和支撑柱，其具体包括：
如图7所示，在中间绝缘层102上形成掩膜层107；并图案化掩膜层107。
如图8所示，根据图案化的掩膜层107，可采用湿法刻蚀或者干法刻蚀的方式去除部分掩膜层107，去除与凹陷1071对应的掩膜层107，以暴露凹陷1071中的金属布线层1011，且去除中间绝缘层102上的部分掩膜层，以暴露部分中间绝缘层，以在各凹陷1071中和在暴露的中间绝缘层102上形成导电柱104，在各导电柱104远离芯片的一端形成焊接部1041，其中，各凹陷1071中的导电柱104和导电柱104上的焊接部1041形成导电凸柱104a，而中间绝缘层102上的导电柱104和导电柱104上的焊接部1041形成支撑柱104b。
可以理解的是，金属布线层1011上的导电柱104和焊接部1041，与中间绝缘层102上的导电柱104和焊接部1041是通过一体成型的方式形成的，即导电凸柱104a和支撑柱104b是通过一体成型的工艺形成的。
如图9所示，可以理解的是，可通过电镀的方式在导电柱104远离芯片101的一端形成有焊接部1041。
如图10所示，当在各凹陷1071中形成导电凸柱104a和支撑柱104b之后，去除掩膜层107。
如图11所示，在第二预设温度下，使焊接部1041朝向导电柱104的一侧回流，以使焊接部1041形成向远离导电柱104的一侧弯曲的弧形面。其中，该弧形面可以是圆弧形面，或者椭圆形弧形面等。
步骤S105：在中间绝缘层上形成非导电胶层，非导电胶层填充容纳孔，以在非导电胶背离中间绝缘层的表面上形成与容纳孔相匹配的凹槽，非导电胶在第一预设温度和预设压力下流动填充凹槽。
如图2所示，在中间绝缘层102上形成非导电胶层103，非导电胶会先填充容纳 孔105，因此，在各容纳孔105对应的非导电胶层103上会形成与容纳孔105相匹配的凹槽1031，这样，当芯片封装结构100与基板进行封装时，导电凸柱104a与基板200之间以及附近的非导电胶会受挤压而向导电凸柱104a的四周溢出，溢出的非导电胶会填充至靠近导电凸柱104a边缘的凹槽1031内，从而避免非导电胶溢出芯片101的边缘，进而提高封装后芯片101的良率。
如图14所示，本申请实施例提供的半导体结构包括：基板200和上述实施例中提供的芯片封装结构100，其中，芯片封装结构100包括多个间隔设置的导电凸柱104a，基板200上设有多个与各导电凸柱104a相对应的焊盘201，当芯片封装结构100位于基板200上与基板200封装时，各导电凸柱104a与其对应的焊盘201焊接并电导通。
图12为本申请另一实施例中半导体结构的封装方法的流程示意图。
如图12所示，本申请实施例还提供的半导体结构的封装方法，其步骤包括：
步骤S201：提供一基板，基板上设有多个焊盘。
其中，焊盘的材质包括铜、铝、镍、金、银、钛中的一种或者几种组合。基板的材质包括树脂、硅、玻璃、氧化硅、陶瓷、金属中的一种或者几种组合。
步骤S202：提供如上述实施例中提供的芯片封装结构的制备方法制备的芯片封装结构，芯片封装结构具有多个与各焊盘相对应的导电凸柱；
步骤S203：将芯片封装结构倒装在基板上，以使芯片封装结构上的各导电凸柱与基板上的各焊盘一一对应；
步骤S204：提供压力设备，压力设备位于芯片封装结构的上方；
步骤S205：压力设备向芯片封装结构提供第一预设温度和预设压力；以使芯片封装结构上的各导电凸柱与其对应的基板上的焊盘键合并电导通。
如图13和图14所示，压力设备300在向芯片封装结构100和基板200提供压力的同时还加热芯片封装结构100和基板200，以使芯片封装结构100和基板200之间达到热压键合的压力和温度，从而时芯片封装结构100上的导电凸柱104a分别与各焊盘201焊接并电导通。
可以理解的是，芯片101上的加热设备自身的加热温度为60℃～70℃；以使芯片封装结构100与基板200之间的第一预设温度达到240℃～250℃，预设压力为5～12N，键合时间为3～5s。
如图15所示，压力设备300向芯片封装结构100提供第一预设温度和预设压力，以使芯片封装结构100上的各导电凸柱104a与其对应的基板200上的焊盘201键合并电导通之后，对芯片封装结构100和基板200进行烘烤；对烘烤后的基板200和芯片封装结构100上形成包裹基板200和芯片封装结构100的塑封层500；在塑封后的基板200背离芯片封装结构100的表面上形成焊球400；切割基板200，切割后的基板200、切割后的基板200上对应的焊球400以及切割后的基板200上对应的芯片封装结构100形成封装后的芯片。
上述实施例提供的芯片封装结构的制备方法、半导体结构、半导体结构的封装方法的有益效果与芯片封装结构具有相同的有益效果，在此，不再一一进行赘述。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种芯片封装结构，包括：芯片、设置在所述芯片上的中间绝缘层和设置在所述中间绝缘层上的非导电胶层；
    所述芯片上设有多个导电凸柱，各所述导电凸柱贯穿所述中间绝缘层；
    所述中间绝缘层设有至少一组容纳孔，所述非导电胶层填充所述容纳孔，以使所述非导电胶层背离所述中间绝缘层的表面上形成有与所述容纳孔相匹配的凹槽。
  2. 根据权利要求1所述的芯片封装结构，其中，所述芯片封装结构还包括多个支撑柱；多个所述支撑柱形成至少一组支撑柱组，且各所述支撑柱分别间隔设置在所述中间绝缘层上；
    多个导电凸柱形成至少一组导电凸柱组，所述导电凸柱组中的各所述导电凸柱排布形成的图案，与所述支撑柱组中各所述支撑柱排布形成的图案不同。
  3. 根据权利要求2所述的芯片封装结构，其中，所述容纳孔包括相连通的第一容纳孔和第二容纳孔，所述第一容纳孔设置于所述导电凸柱组一侧，所述第二容纳孔设置于所述支撑柱组一侧。
  4. 根据权利要求3所述的芯片封装结构，其中，所述第一容纳孔的图案与所述导电凸柱组中各所述导电凸柱的排布图案相匹配；所述第二容纳孔的图案与所述支撑柱组中各所述支撑柱的排布图案相匹配。
  5. 根据权利要求4所述的芯片封装结构，其中，所述导电凸柱组为至少两组，至少两组所述导电凸柱组在所述芯片上间隔排布，一组所述导电凸柱组对应一个所述第一容纳孔。
  6. 根据权利要求4所述的芯片封装结构，其中，所述支撑柱组为至少两组，至少两组所述支撑柱组在所述中间绝缘层上间隔排布，一组所述支撑柱组对应一个所述第二容纳孔。
  7. 根据权利要求2-6中任一项所述的芯片封装结构，其中，所述中间绝缘层设有与每组所述容纳孔连通的排气通道，其中，一组所述容纳孔对应一个所述排气通道，各所述排气通道延伸至所述中间绝缘层的边缘并与外界连通。
  8. 根据权利要求7所述的芯片封装结构，其中，所述容纳孔在所述中间绝缘层上投影的面积之和，为多个所述导电凸柱和多个所述支撑柱在所述中间绝缘层上投影的面积之和的3.5～4倍。
  9. 根据权利要求1所述的芯片封装结构，其中，所述导电凸柱远离所述芯片的一端设有焊接部，所述焊接部为弧形面。
  10. 一种芯片封装结构的制备方法，包括：
    提供芯片；
    在所述芯片上形成中间绝缘层；
    在所述中间绝缘层上形成至少一组容纳孔和暴露所述芯片中金属布线层的多个凹陷；
    在各所述凹陷中形成多个导电凸柱，其中，所述导电凸柱远离所述芯片的一端具有焊接部，所述焊接部为向远离所述导电凸柱一侧弯曲的弧形面；
    在所述中间绝缘层上形成非导电胶层，所述非导电胶层填充所述容纳孔，以在所述非导电胶层背离所述中间绝缘层的表面上形成与所述容纳孔相匹配的凹槽。
  11. 根据权利要求10所述的芯片封装结构的制备方法，其中，在所述中间绝缘层上形成至少一组容纳孔和暴露所述芯片中电路层的多个凹陷，具体包括：
    图案化所述中间绝缘层，在所述中间绝缘层上形成第一图案组和第二图案组；
    按照所述第一图案组去除所述中间绝缘层，形成至少一组所述容纳孔；按照所述第二图案组去除所述中间绝缘层和部分所述芯片，暴露所述芯片中的金属布线层，形成多个所 述凹陷。
  12. 根据权利要求11所述的芯片封装结构的制备方法，其中，按照所述第一图案组去除所述中间绝缘层，形成至少一组所述容纳孔；按照所述第二图案组去除所述中间绝缘层和部分所述芯片，暴露所述芯片中的所述金属布线层，形成多个所述凹陷之后，包括：
    在各所述凹陷中和所述中间绝缘层上分别形成导电柱；
    在各所述导电柱上形成焊接部，各所述凹陷中的所述导电柱和所述焊接部形成所述导电凸柱；所述中间绝缘层上的所述导电柱和所述焊接部形成支撑柱。
  13. 根据权利要求12所述的芯片封装结构的制备方法，其中，在各所述导电柱上形成焊接部，各所述凹陷中的所述导电柱和所述焊接部形成所述导电凸柱；所述中间绝缘层上的所述导电柱和所述焊接部形成所述支撑柱之后，还包括：
    在第二预设温度下，回流所述焊接部，以使所述焊接部形成向远离所述导电柱的一侧弯曲的弧形面。
  14. 一种半导体结构的封装方法，包括：
    提供一基板，基板上设有多个焊盘；
    提供如权利要求1至9中任一项所述的芯片封装结构，所述芯片封装结构具有多个与各焊盘相对应的导电凸柱；
    将所述芯片封装结构倒装在所述基板上，以使所述芯片封装结构上的各所述导电凸柱与所述基板上的各焊盘一一对应；
    提供压力设备，所述压力设备位于所述芯片封装结构的上方；
    所述压力设备向所述芯片封装结构提供第一预设温度和预设压力；以使所述芯片封装结构上的各导电凸柱与其对应的所述基板上的所述焊盘键合并电导通。
  15. 根据权利要求14所述的半导体结构的封装方法，其中，所述压力设备向所述芯片封装结构提供第一预设温度和预设压力，以使所述芯片封装结构上的各导电凸柱与其对应的所述基板上的所述焊盘键合并电导通之后，还包括：
    对所述芯片封装结构和所述基板进行烘烤；
    对烘烤后的所述基板和所述芯片封装结构上形成包裹所述基板和所述芯片封装结构的塑封层；
    在塑封后的所述基板背离所述芯片封装结构的表面上形成焊球；
    切割所述基板，切割后的所述基板、切割后的所述基板上对应的所述焊球以及切割后的所述基板上对应的所述芯片封装结构形成封装后的芯片。
PCT/CN2022/071277 2021-09-17 2022-01-11 芯片封装结构及制备方法、半导体结构的封装方法 WO2023040144A1 (zh)

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JP2012074449A (ja) * 2010-09-28 2012-04-12 Toppan Printing Co Ltd 実装基板
JP2015056480A (ja) * 2013-09-11 2015-03-23 デクセリアルズ株式会社 アンダーフィル材、及びこれを用いた半導体装置の製造方法
US20160005707A1 (en) * 2014-07-02 2016-01-07 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
CN106206510A (zh) * 2015-04-27 2016-12-07 南茂科技股份有限公司 多芯片封装结构、晶圆级芯片封装结构及其方法
CN110416170A (zh) * 2019-06-24 2019-11-05 苏州通富超威半导体有限公司 基板、芯片封装结构及其制备方法

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JP2012074449A (ja) * 2010-09-28 2012-04-12 Toppan Printing Co Ltd 実装基板
JP2015056480A (ja) * 2013-09-11 2015-03-23 デクセリアルズ株式会社 アンダーフィル材、及びこれを用いた半導体装置の製造方法
US20160005707A1 (en) * 2014-07-02 2016-01-07 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
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