CN104681456A - 一种扇出型晶圆级封装方法 - Google Patents
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Abstract
本发明实施例提供了一种扇出型晶圆级封装方法,可适用于小薄芯片并简化了工艺流程。该扇出型晶圆级封装方法包括:在至少一个芯片的正面上分别制备导电凸柱,将所述至少一个芯片的正面朝上贴装于一个载板上,并对所述至少一个芯片进行塑封,使得塑封后所述导电凸柱的顶端外露在塑封体之外;在外露导电凸柱的所述塑封体上通过重布线工艺完成扇出型晶圆级封装。
Description
技术领域
本发明涉及半导体封装技术领域,具体涉及一种扇出型晶圆级封装方法。
技术背景
扇出型晶圆级封装(Fan Out Wafer Level Package,可简写为FOWLP)是一种晶圆级加工的嵌入式芯片封装方法,是目前一种输入/输出端口(I/O)较多、集成灵活性较好的先进封装方法之一。现有常见的FOWLP技术有由英飞凌科技公司(Infineon Technologies AG)发明的eWLP封装以及由台积电公司发明的TSMC FOWLP封装。
图1所示为现有技术中Infineon eWLP封装的结构示意图。如图1所示,这种封装方式是将芯片11的正面朝下贴装到载板上,然后将芯片11塑封在塑封体12中。由于塑封后芯片11的正面朝向载板,为了使芯片11的正面上的导电电极露出以进行重布线工艺,必须在塑封完成后就将载板进行180度翻转,并将胶膜及载板拆除以露出位于芯片11正面的导电电极。为此,芯片必须做得足够厚,不能做太薄,否则载板拆除后的塑封体会形成较大的翘曲,导致后续的重布线工艺难以进行。
图2所示为现有技术中TSMC FOWLP封装的结构示意图。如图2所示,这种封装方式是首先在芯片21正面上种植导电凸柱22,将芯片21正面朝上贴装到了一个载板23上,并将芯片21塑封在一个塑封体24内。塑封完成后通过打磨塑封体24漏出导电凸柱22,后续在此基础上进行重布线工艺完成焊盘布局并植球。从图2封装结构上看,在这种方法中,由于芯片导电凸柱没有露出塑封体外,因此在工艺上需要额外的打磨才可以把I/O引出,导致封装成本增加。
发明内容
有鉴于此,本发明实施例提供了一种扇出型晶圆级封装方法,可适用于小薄芯片并简化了工艺流程。
本发明一实施例提供了一种扇出型晶圆级封装方法,包括:
在至少一个芯片的正面上分别制备导电凸柱,并对所述至少一个芯片进行塑封,使得塑封后所述导电凸柱的顶端外露在塑封体之外;所述至少一个芯片的正面朝上贴装于一个载板上;
在外露导电凸柱的所述塑封体上通过重布线工艺完成扇出型晶圆级封装。
本发明实施例公开的一种扇出型晶圆级封装方法,在对芯片进行塑封时,首先在芯片正面形成导电凸柱,并将塑封体直接塑封至露出导电凸柱的位置,这样省去了现有技术中对塑封体进行额外的打磨以露出导电凸柱的工艺步骤,可快速简易的实现导电凸柱与重布线金属层的互联,简化了工艺流程;同时由于导电凸柱高度大于导电凸点,所以在进行塑封高度控制时,易于控制塑封露出导电凸点的工艺步骤,降低了工艺难度。
附图说明
图1所示为现有技术的一种芯片导电电极面朝下封装的结构示意图。
图2所示为现有技术的一种芯片导电电极面朝上封装的结构示意图。
图3所示为本发明一实施例提供的一种扇出型晶圆级封装方法的流程图。
图4所示为本发明一实施例提供的一种扇出型晶圆级封装方法所形成的封装结构示意图。
图5所示为本发明一实施例提供的一种扇出型晶圆级封装方法所形成的另一封装结构示意图。
图6a~6n所示为本发明一实施例提供的一种扇出型晶圆级封装方法的分解流程结构示意图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
图3所示为本发明一实施例提供的一种扇出型晶圆级封装方法的流程图。如图3所示,该方法包括:
步骤301:在至少一个芯片的正面上分别制备导电凸柱,将所述至少一个芯片的正面朝上贴装于一个载板上,并对所述至少一个芯片进行塑封,使得塑封后所述导电凸柱的顶端外露在塑封体之外。
芯片是通过对一个半导体晶圆进行减薄、切割而成,芯片的正面是由芯片内部电路引出至芯片表面的导电电极构成,导电凸柱制备在这些导电电极上。在本发明一实施例中,导电凸柱可采用电镀、或凸点、或植球法制备而成。导电凸柱的制备材料可为金、银、铜或其他金属材料。
本领域技术人员可以理解,芯片的正面上的导电凸柱可以是在半导体晶圆上就制备完成,然后再将半导体晶圆切割成带有导电凸柱的单个芯片;也可以是先将半导体晶圆切割成单个芯片,等到对芯片进行塑封之前再在芯片正面上制备导电凸柱。本发明对导电凸柱的制备时机不做限定。
在本发明一实施例中,载板的形状可包括:圆形、矩形或其他形状,本发明对载板的形状不做限定。如前所述,导电凸柱可在对芯片进行塑封之前再制备,因此导电凸柱可以在芯片贴装到载板上后再制备。
在本发明一实施例中,载板可在重布线完成后再拆除;也可以在塑封完成后就拆除载板。在本发明另一实施例中,为了提高芯片的散热性能和机械性能,载板也可以不拆除。本发明对载板拆除的时机和是否拆除不做限定。
在本发明一实施例中,对所述至少一个芯片的导电电极面的塑封采用模塑法或印刷法完成。具体过程可为:使用模塑法或印刷法在载板上填充塑封材料,使塑封材料将芯片和导电凸柱的底部覆盖,将导电凸柱的顶部露出。露出的导电凸柱顶部与重布线层相连起到导通电流的作用。
步骤302:在所述外露导电凸柱的塑封体上通过重布线(RedistributionLine)工艺完成扇出型晶圆级封装。
具体而言,该过程可为:
首先在塑封体和外露的导电凸柱上制备导电种子层;
然后采用光刻法在导电种子层上用光刻胶掩膜构成重布线金属层图案;
接着在光刻胶掩膜上进行电镀,填补光刻胶掩膜的空白部分;
再后,去除光刻胶掩膜形成包含焊垫的重布线金属层;
然后,在重布线金属层上制备阻焊层,露出所述重布线金属层上的焊垫部分;
最后再在焊垫上制备焊球,形成最终的整体封装结构。
按照以上实施例的封装方法形成的封装结构可以如图4所示。该封装结构中包括两个芯片,每个芯片的正面上制备有两个导电凸柱。虽然这两个芯片均以正面朝上封装在塑封材料构成的塑封体内,但每个芯片正面上的导电凸柱的顶端都外露出塑封体表面。外露的四个导电凸柱顶端通过导电种子层分别与四个焊垫连接,每个焊垫上焊接有一个焊球。四个焊垫之间的间隙由阻焊材料填充。
在本发明一实施例中,为了提高封装芯片的密度,也可以事先在塑封体和外露的导电凸柱上制备电介质层;在该电介质层上采用光刻法使导电凸柱的顶端露出;然后在电介质层和所述导电凸柱上制备导电种子层。在这种情况下形成的封装结果可以如图5所示。与图4所示的封装结构不同,导电种子层与塑封体表面之间还包括一个电介质层,该电介质层在每个导电凸柱的位置上设有一个由光刻法形成的开口,每个导电凸柱通过该开口与导电种子层连接。
本领域技术人员可以理解,在一个载板上可以同时贴装多个芯片。在形成一个包含多个芯片的整体封装结构后,再将该整体封装结构分离为包含单一芯片的封装结构即可。本发明对一个载板上贴装的芯片数量同样不做限定。
下面通过一个实施例将本发明从芯片制作到形成包含单一芯片封装结构的技术方案进行详细说明。
图6a~6n所示为本发明一实施例提供的一种扇出型晶圆级封装方法的分解流程结构示意图。如图6a~6n所示,该扇出型晶圆级封装方法包括如下步骤。
如图6a所示,在裸晶圆1上划定芯片分割线(图中虚线),并在晶圆上制作导电凸柱2。
如图6b所示,对裸晶圆1进行减薄,形成带有导电凸柱2的芯片。
如图6c所示,将带有导电凸柱2的芯片3正面贴装于一个载板4上。
如图6d所示,对芯片3进行塑封形成塑封体5,塑封后导电凸柱2的顶端露在塑封体5之外。
如图6e所示,在塑封体5和导电凸柱2的顶端上制备电介质层6。
如图6f所示,采用光刻法使得电介质层6上暴露出导电凸柱2。
如图6g所示,在电介质层6和暴露的导电凸柱2上制备导电种子层7。
如图6h所示,采用光刻法在导电种子层7上用光刻胶掩膜8构成重布线金属层图案。其中,暴露的光刻胶掩膜空白部分9为后续形成焊垫的位置。
如图6i所示,用导电材料填充光刻胶掩膜空白部分9。
如图6j所示,去除光刻胶掩膜8,保留导电种子层。
如图6k所示,拆除芯片3背面的载板4。
如图6l所示,制备阻焊层10,仅在用导电材料填充后的原光刻胶掩膜空白部分9上留出焊垫11的位置,即焊垫11的位置不用阻焊层覆盖。
如图6m所示,在焊垫11上制备焊球12。
如图6n所示,将整体封装结构分离为包含单一芯片的封装结构。
本发明实施例公开的一种扇出型晶圆级封装方法,在对芯片进行塑封时,首先在芯片正面形成导电凸柱,并在塑封体直接塑封至露出导电凸柱的位置,这样省去了现有技术中对塑封体进行额外的打磨以露出导电凸点的工艺步骤,可快速简易的实现导电凸柱与重布线金属层的互联,简化了工艺流程;同时由于导电凸柱高度大于导电凸点,所以在进行塑封高度控制时,易于控制塑封露出导电凸点的工艺步骤,降低了工艺难度。
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内,所作的任何修改、等同替换等,均应包含在本发明的保护范围之内。
Claims (8)
1.一种扇出型晶圆级封装方法,其特征在于,包括:
在至少一个芯片的正面上分别制备导电凸柱,将所述至少一个芯片的正面朝上贴装于一个载板上,并对所述至少一个芯片进行塑封,使得塑封后所述导电凸柱的顶端外露在塑封体之外;
在外露导电凸柱的所述塑封体上通过重布线工艺完成扇出型晶圆级封装。
2.根据权利要求1所述的方法,其特征在于,在外露导电凸柱的所述塑封体上通过重布线工艺完成扇出型晶圆级封装包括:
在所述塑封体和外露的导电凸柱上制备导电种子层;
采用光刻法在所述导电种子层上用光刻胶掩膜构成重布线金属层图案;
在所述光刻胶掩膜上进行电镀填补所述光刻胶掩膜的空白部分;
去除所述光刻胶掩膜形成包含焊垫的重布线金属层;
在所述重布线金属层上制备阻焊层,露出所述重布线金属层上的焊垫部分;
在所述焊垫上制备焊球。
3.根据权利要求2所述的方法,其特征在于,在所述塑封体和外露的导电凸柱上制备导电种子层之前,进一步包括:
在所述塑封体和外露的导电凸柱上制备电介质层;
在所述电介质层上采用光刻法使所述导电凸柱的顶端露出。
4.根据权利要求1至3中任一所述的方法,其特征在于,所述导电凸柱的制备方法包括:电镀、凸点和植球。
5.根据权利要求1至3中任一所述的方法,其特征在于,所述导电凸柱的制备材料包括:金、银或铜。
6.根据权利要求1至3中任一所述的方法,其特征在于,对所述至少一个芯片进行塑封之后,进一步包括:
将所述载板从所述芯片背面拆除。
7.根据权利要求6所述的方法,其特征在于,所述载板的形状包括:圆形和矩形。
8.根据权利要求1至3中任一所述的方法,其特征在于,对所述至少一个芯片进行的塑封采用模塑法或印刷法完成。
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