CN109037082A - 封装结构及其形成方法 - Google Patents

封装结构及其形成方法 Download PDF

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Publication number
CN109037082A
CN109037082A CN201810796603.5A CN201810796603A CN109037082A CN 109037082 A CN109037082 A CN 109037082A CN 201810796603 A CN201810796603 A CN 201810796603A CN 109037082 A CN109037082 A CN 109037082A
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Prior art keywords
layer
chip
encapsulating structure
improvement
opening
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CN201810796603.5A
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CN109037082B (zh
Inventor
石磊
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Tongfu Microelectronics Co Ltd
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Tongfu Microelectronics Co Ltd
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Priority to CN201810796603.5A priority Critical patent/CN109037082B/zh
Publication of CN109037082A publication Critical patent/CN109037082A/zh
Priority to US16/393,632 priority patent/US10998289B2/en
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Publication of CN109037082B publication Critical patent/CN109037082B/zh
Priority to US17/232,786 priority patent/US20210233890A1/en
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Abstract

一种封装结构及其形成方法，其中封装结构的形成方法包括：提供基板，所述基板表面具有粘合层；在所述粘合层表面形成改善层，所述改善层内具有开口，所述开口底部暴露出粘合层表面；提供芯片，所述芯片包括功能面；贴装芯片，使所述功能面与开口底部的粘合层贴合，且所述芯片表面低于或者齐平于改善层的表面。所述方法形成的封装结构较好。

Description

封装结构及其形成方法
技术领域
本发明涉及封装领域，尤其涉及一种芯片的封装结构及其形成方法。
背景技术
随着集成电路制造业的快速发展，人们对集成电路的封装技术的要求也不断提高，现有的封装技术包括球栅阵列封装(BGA)、芯片尺寸封装(CSP)、圆片级封装(WLP)、三维封装(3D)和系统封装(SiP)。其中，圆片级封装(WLP)由于其出色的优点逐渐被大部分的半导体制造者所采用，它的全部或者大部分工艺步骤是在已完成前工序的硅圆片上完成的，最后将圆片直接切割成分离的独立器件。圆片级封装具有如下独特优势：封装加工效率高，可以多个圆片同时加工；具有倒装芯片封装的优点，即：轻、薄、短、小；与前工序相比，只是增加了引脚重新布线(RDL)和凸点制作两个工序，其余全部是传统工艺；减少了传统封装中的多次测试。因此，世界上各大型IC封装公司纷纷投入圆片级封装的研究、开发和生产。
然而，现有圆片级封装技术仍存在较多的问题，所形成的封装结构的性能较差。
发明内容
本发明解决的技术问题是提供一种封装结构及其形成方法，以提高封装结构的性能。
为解决上述技术问题，本发明提供一种封装结构的形成方法，包括：提供基板，所述基板表面具有粘合层；在所述粘合层表面形成改善层，所述改善层内具有开口，所述开口底部暴露出粘合层表面；提供芯片，所述芯片包括功能面；贴装芯片，使所述功能面与开口底部的粘合层贴合，且所述芯片表面低于或者齐平于改善层的表面。
可选的，所述粘合层包括：紫外粘合胶、丙烯酸压敏胶或者环氧树脂压敏胶。
可选的，所述改善层和开口的形成方法包括：在所述粘合层表面形成改善膜；对所述改善膜进行曝光显影，形成所述改善层，所述改善层内具有开口。
可选的，所述改善膜的材料包括光刻胶。
可选的，贴装所述芯片之后，还包括：在所述改善层表面、以及芯片的侧壁和表面形成塑封层；形成所述塑封层之后，去除所述基板和粘合层，暴露出芯片的功能面；去除所述基板和粘合层之后，在所述功能面上形成布线层和位于布线层表面的钝化层，所述钝化层内具有暴露出布线层表面的焊料开口；在所述焊料开口内形成焊球；形成所述焊球之后，进行切割处理，形成芯片结构。
可选的，所述芯片结构不包括改善层；或者，所述芯片结构包括部分改善层。
可选的，形成所述芯片结构之后，还包括：对塑封层进行减薄处理，直至暴露出芯片的顶部表面。
可选的，形成所述焊球之后，进行切割处理之前，还包括：对所述塑封层进行减薄处理，直至暴露出芯片表面；暴露出芯片表面之后，去除所述改善层。
相应的，本发明还提供一种封装结构，包括：基板，所述基板表面具有粘合层；位于所述粘合层表面的改善层，所述改善层内具有开口，所述开口底部暴露出粘合层顶部表面；位于所述开口内的芯片，所述芯片包括功能面，所述功能面与粘合层贴合，且所述芯片表面低于或者齐平于改善层的表面。
可选的，所述粘合层包括：紫外粘合胶、丙烯酸压敏胶或者环氧树脂压敏胶。
可选的，所述改善层的材料包括光刻胶。
与现有技术相比，本发明的技术方案具有以下有益效果：
本发明技术方案提供的封装结构的形成方法中，所述改善层内具有开口，所述开口用于容纳后续芯片。并且，所述芯片的表面低于或者齐平于改善层的表面，使得所述芯片完全嵌入开口内，则所述开口侧壁的改善层限制芯片发生偏移的能力较强，则所述芯片不易发生偏移，因此，有利于提高封装结构的性能。
附图说明
图1是一种封装结构的结构示意图；
图2至图13是本发明一实施例的封装结构的形成方法的各步骤的结构示意图；
图14是本发明另一实施例的结构示意图；
图15至图17是本发明再一实施例的封装结构的形成方法的各步骤的结构示意图。
具体实施方式
正如背景技术所述，封装结构的性能较差。
图1是一种封装结构的结构示意图。
请参考图1，提供基底100，所述基底100表面具有粘合层101；提供芯片102，所述芯片102包括功能面1，所述功能面1的芯片102内具有焊盘102a；贴装所述芯片102，使所述功能面1与粘合层101贴合。
上述方法中，所述芯片102的材料包括硅，硅的热膨胀系数较小，而所述粘合层101材料的热膨胀系数较芯片102大的多，则在后续高温工艺过程中，所述粘合层101和芯片102的热膨胀程度不同，使得芯片102和粘合层101之间易发生相对位移，不利于提高封装结构的性能。
为解决所述技术问题，本发明提供了一种封装结构的形成方法，通过在所述粘合层顶部形成改善层，所述改善层内具有开口，所述开口用于限定芯片的位置的能力较强，使得芯片不易发生相对位移，有利于提高封装结构的性能。
为使本发明的上述目的、特征和有益效果能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图2至图13是本发明一实施例的封装结构的形成方法的各步骤的结构示意图。
请参考图2，提基板200，所述基板200表面具有粘合层201。
所述基板200的材料包括：玻璃、陶瓷、金属或者聚合物。
所述基板200的形状包括圆形、矩形或者三角形。
所述粘合层201用于后续将芯片粘附于基板200上。
在本实施例中，所述粘合层201的材料为紫外粘合胶，所述紫外粘合胶在未经过紫外照射时粘性很高，而经过紫外光照射后材料内的交联化学键被打断导致粘性大幅下降或消失，有利于后续剥离粘合层201和基板200。
在其他实施例中，所述粘合层包括：丙烯酸压敏胶或者环氧树脂压敏胶。
所述粘合层201的形成工艺包括：旋涂工艺、喷涂工艺、滚压工艺、印刷工艺、非旋转涂覆工艺、热压工艺、真空压合工艺或者压力压合工艺。
所述粘合层201的材料具有第一热膨胀系数，所述第一热膨胀系数较高。
请参考图3，在所述粘合层201表面形成改善膜202。
所述改善膜202的材料包括：光刻胶，所述改善膜202的形成工艺包括：旋涂工艺或者印刷工艺。
所述改善膜202用于后续形成改善层。所述改善膜202具有第二热膨胀系数，所述第二热膨胀系数也较大，且所述第二热膨胀系数与第一热膨胀系数之间的差值落在预设范围内，具体的，预设范围为：-50～50，使得在后续高温工艺过程中，所述改善层和粘合层201之间不易发生相对位移，而后续改善层内的开口用于限制芯片发生位移，因此，有利于减少封装结构发生偏移或者翘曲。
所述改善膜202的厚度为20微米～100微米，选择所述改善膜202的厚度的意义在于：所述改善膜202用于后续形成改善层，若所述改善膜202的厚度小于20微米，则所述改善层的厚度小于20微米，使得后续部分芯片嵌入改善层之间的开口内，则所述开口侧壁的改善层对芯片的限制能力较弱，则在后续高温工艺过程中，所述芯片仍易发生相对位移，不利于提高封装结构的性能；若所述改善膜202的厚度大于100微米，易造成改善膜202材料的耗费过多，不利于节约成本。
请参考图4，对所述改善膜202(见图3)进行曝光显影，形成改善层220，所述改善层220内具有若干开口203，所述开口203底部暴露出粘合层201的顶部表面。
所述改善层220是由改善膜202形成，而第二热膨胀系数与第一热膨胀系数之间的差值落在预设范围内，则在后续高温工艺过程中，所述改善层220和粘合层201之间不易发生相对位移。
并且，由于所述改善膜202的厚度较厚，所形成的开口203的深度较深，则所述开口203侧壁的改善层220限定后续芯片的能力较强，则芯片不易发生相对位移。综上，所述芯片、改善层220和粘合层201之间均不易发生相对位移，有利于减少封装结构发生偏移或者翘曲。
所述改善层220的厚度是由改善膜202的厚度所决定，因此，所述改善层220的厚度为：20微米～100微米，所述改善层220的厚度决定开口203的深度，因此，所述开口203的深度为：20微米～100微米。
选择所述开口203的深度的意义为：若所述开口203的深度小于20微米，使得后续芯片部分嵌入开口203内，则所述开口203侧壁的改善层220对后续芯片的限制能力较弱，使得在后续高温工艺过程中，所述芯片仍易发生相对位移，不利于提高封装结构的性能；若所述开口203的深度大于100微米，使得所需改善膜202的厚度较厚，易造成改善膜202材料的耗费过多，不利于节约成本。
请参考图5，提供芯片204，所述芯片204包括功能面11，所述功能面11内具有焊盘204a；贴装芯片204，使所述功能面11与开口203(见图4)粘合层201贴合，且所述芯片204表面低于或者齐平于改善层220的表面。
所述芯片204的材料包括硅，所述芯片204的热膨胀系数为2.2～2.4。所述焊盘204a用于将芯片204内的电信号输出。
所述芯片204的厚度为：20微米～100微米。
所述芯片204通过粘合层201贴装与基板200上。由于所述芯片204表面低于或者齐平于改善层220的表面，使得所述芯片204完全嵌入开口203内，所述开口203侧壁的改善层220限制芯片204位置的能力较强，则芯片204不易发生偏移，有利于减少封装结构发生偏移或者翘曲。
请参考图6，在所述改善层220表面、以及芯片204的侧壁和表面形成塑封层205。
在本实施例中，所述塑封层205的材料为环氧树脂，所述环氧树脂的密封性能好，塑型容易，是形成塑封层205较佳的材料。
在其他实施例中，所述塑封层的材料为塑封材料，所述塑封材料包括聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、乙烯-醋酸乙烯共聚物、聚乙烯醇。
在本实施例中，所述塑封层205的形成工艺为注塑工艺(injection molding)。在其他实施例中，所述塑封层的形成工艺包括：转塑工艺(transfer molding)或丝网印刷工艺。
采用注塑工艺形成塑封层205的方法包括：提供模具；在所述模具中填充塑封材料，使所述塑封材料包覆所述芯片204；对所述塑封材料进行升温固化，形成塑封层205。
所述塑封层205既能够保护芯片204又可作为后续工艺的承载体。
在形成所述塑封层205的过程中，尽管所述芯片204材料的热膨胀系数与改善层220和粘合层201的热膨胀系数之间的差值较大，但是，由于全部所述芯片204位于开口203内，因此，所述开口203侧壁的改善层220在升温固化的过程中对芯片204位置的限制能力较强，则所述芯片204不易发生偏移。
并且，改善层220与粘合层201的热膨胀系数之间的差值落在预设范围之内，则在所述升温固化过程中，所述改善层220和粘合层201之间不易发生相对位移。综上、芯片204、改善层220和粘合层201之间不易发生相对位移，有利于减少封装结构发生偏移或者翘曲。
在本实施例中，形成所述塑封层205之后，不对塑封层205进行减薄处理。
在其他实施例中，形成所述塑封层之后，对塑封层进行减薄处理，直至暴露出芯片的顶部表面。
请参考图7，形成所述塑封层205之后，去除所述基板200(见图6)和粘合层201(见图6)，暴露出芯片204的功能面11。
在本实施例中，所述粘合层201的材料为紫外粘合胶，去除所述基板200(见图6)和粘合层201(见图6)的方法包括：利用紫外光照射照射，使粘合层201的粘性降低，从而使得粘合层201和基板200剥离。
去除所述基板200(见图6)和粘合层201(见图6)，直接暴露出芯片204的功能面11，无需对塑封层205进行减薄处理暴露出功能面11，有利于减少工艺复杂度。
请参考图8，去除所述基板200和粘合层201之后，在所述焊盘204a表面形成布线层206。
所述布线层206的材料为金属，如：铝、铜、锡、镍、金或者银。
所述布线层206的形成工艺包括蒸镀工艺、溅射工艺、电镀工艺或者化学镀工艺。
所述布线层206底部与焊盘204a顶部电连接，所述布线层206顶部与后续焊球之间的电连接。
请参考图9，在所述改善层220表面和布线层206的侧壁形成钝化层207，所述钝化层207内具有暴露出布线层206顶部的焊料开口208。
所述钝化层207的材料包括：聚酰亚胺、聚对苯撑苯并双恶唑或光敏苯并环丁烯，所述钝化层207的形成工艺包括：印刷工艺或者旋涂工艺。
所述钝化层207暴露出部分布线层206，有利于后续的焊球与布线层206电连接。
所述焊料开口208用于后续容纳焊球。
请参考图10，在所述焊料开口208(见图9)内形成焊球209。
所述焊球209包括金锡焊球、银锡焊球或者铜锡焊球。
在本实施例中，所述焊球209为金锡焊球，所述金锡焊球的形成方法包括：在所述焊料开口208内形成金锡层；形成所述金锡层之后，进行高温回流工艺，使金锡层回流成球状，降温后形成金锡焊球。
请参考图11，形成所述焊球209之后，对所述塑封层205进行减薄处理，直至暴露出芯片204表面。
由于所述芯片204完全嵌入开口203内，对所述塑封层205进行减薄处理暴露出芯片204表面时，所述改善层220顶部的塑封层205被完全去除，有利于暴露出改善层220，进而有利于后续去除所述改善层220。
请参考图12，暴露出芯片204表面之后，去除所述改善层220。
去除所述改善层220的工艺包括干法刻蚀工艺和湿法刻蚀工艺中的一种或者两种组合。
请参考图13，去除所述改善层220之后，在相邻芯片204之间进行切割处理，形成芯片结构250。
由于去除所述改善层220之后，相邻芯片204之间仅具有钝化层207，则所述切割处理切断的仅仅为钝化层207。
图14为本发明封装结构另一实施例的结构示意图。
请参考图14，形成所述焊球209之后，进行切割处理，形成芯片结构300。
需要说明的是，图14是在上述实施例图10基础上后续步骤的结构示意图。
在本实施例中，所述芯片结构300不包含改善层220，则后续无需去除所述改善层220的工艺，使得工艺步骤较少，有利于降低工艺的复杂度。
在本实施例中，形成所述芯片结构300之后，不对塑封层205进行减薄处理。
在其他实施例中，形成所述芯片结构之后，对塑封层进行减薄处理，直至暴露出芯片的表面。
图15至图17是本发明再一实施例的封装结构的形成方法的各步骤的结构示意图。
请参考图15，形成所述焊球209之后，进行切割处理，形成芯片结构400。
需要说明的是，图15是在图10基础上后续步骤的结构示意图。
在本实施例中，所述芯片结构400包含部分改善层220。
请参考图16，进行切割之后，去除所述改善层220。
去除所述改善层220的工艺包括干法刻蚀工艺和湿法刻蚀工艺中的一种或者两种组合。
请参考图17，去除所述改善层220之后，对塑封层205进行减薄处理，直至暴露出芯片204顶部。
相应的，本发明还提供一种封装结构，请参考图5，包括：
基板200，所述基板200表面具有粘合层201；
位于所述粘合层201表面的改善层220，所述改善层220内具有开口203(见图4)，所述开口203底部暴露出粘合层201表面；
位于所述开口203内的芯片204，所述芯片204包括功能面11，所述功能面11与粘合层201贴合，且所述芯片204表面低于或者齐平于改善层220的表面。
所述粘合层201包括：紫外粘合胶、丙烯酸压敏胶或者环氧树脂压敏胶。
所述改善层220的材料包括光刻胶。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (11)

1.一种封装结构的形成方法，其特征在于，包括：
提供基板，所述基板表面具有粘合层；
在所述粘合层表面形成改善层，所述改善层内具有开口，所述开口底部暴露出粘合层表面；
提供芯片，所述芯片包括功能面；
贴装芯片，使所述功能面与开口底部的粘合层贴合，且所述芯片表面低于或者齐平于改善层的表面。
2.如权利要求1所述的封装结构的形成方法，其特征在于，所述粘合层包括：紫外粘合胶、丙烯酸压敏胶或者环氧树脂压敏胶。
3.如权利要求1所述的封装结构的形成方法，其特征在于，所述改善层和开口的形成方法包括：在所述粘合层表面形成改善膜；对所述改善膜进行曝光显影，形成所述改善层，且所述改善层内具有开口。
4.如权利要求3所述的封装结构的形成方法，其特征在于，所述改善膜的材料包括光刻胶。
5.如权利要求1所述的封装结构的形成方法，其特征在于，贴装所述芯片之后，还包括：在所述改善层表面、以及芯片的侧壁和顶部表面形成塑封层；形成所述塑封层之后，去除所述基板和粘合层，暴露出芯片的功能面；去除所述基板和粘合层之后，在所述功能面上形成布线层和位于布线层表面的钝化层，所述钝化层内具有暴露出布线层表面的焊料开口；在所述焊料开口内形成焊球；形成所述焊球之后，进行切割处理，形成芯片结构。
6.如权利要求5所述的封装结构的形成方法，其特征在于，所述芯片结构不包括改善层；或者，所述芯片结构包括部分改善层。
7.如权利要求6所述的封装结构的形成方法，其特征在于，形成所述芯片结构之后，还包括：对塑封层进行减薄处理，直至暴露出芯片的顶部表面。
8.如权利要求5所述的封装结构的形成方法，其特征在于，形成所述焊球之后，进行切割处理之前，还包括：对所述塑封层进行减薄处理，直至暴露出芯片表面；暴露出芯片表面之后，去除所述改善层。
9.一种封装结构，其特征在于，包括：
基板，所述基板表面具有粘合层；
位于所述粘合层表面的改善层，所述改善层内具有开口，所述开口底部暴露出粘合层顶部表面；
位于所述开口内的芯片，所述芯片包括功能面，所述功能面与粘合层贴合，且所述芯片表面低于或者等于改善层的表面。
10.如权利要求9所述的封装结构，其特征在于，所述粘合层包括：紫外粘合胶、丙烯酸压敏胶或者环氧树脂压敏胶。
11.如权利要求9所述的封装结构，其特征在于，所述改善层的材料包括光刻胶。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115849298A (zh) * 2023-01-18 2023-03-28 胜科纳米(苏州)股份有限公司 一种具有梳齿结构芯片的梳齿层去除方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109037082B (zh) * 2018-07-19 2021-01-22 通富微电子股份有限公司 封装结构及其形成方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102177580A (zh) * 2006-08-31 2011-09-07 Ati科技无限责任公司 具有封装剂保持结构的反转芯片半导体封装及条带
CN103383923A (zh) * 2012-03-08 2013-11-06 新科金朋有限公司 用于应用处理器和存储器集成的薄3d扇出嵌入式晶片级封装(ewlb)
CN103715104A (zh) * 2012-09-28 2014-04-09 新科金朋有限公司 在半导体管芯上形成支撑层的半导体器件和方法
CN104241217A (zh) * 2014-06-25 2014-12-24 中国科学院微电子研究所 一种芯片背面裸露的扇出型封装结构及制造方法
CN104681456A (zh) * 2015-01-27 2015-06-03 华进半导体封装先导技术研发中心有限公司 一种扇出型晶圆级封装方法
CN105206539A (zh) * 2015-09-01 2015-12-30 华进半导体封装先导技术研发中心有限公司 扇出型封装制备方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7276919B1 (en) * 1995-04-20 2007-10-02 International Business Machines Corporation High density integral test probe
SG77652A1 (en) * 1998-03-18 2001-01-16 Hitachi Cable Semiconductor device lead-patterning substrate and electronics device and method for fabricating same
US6332270B2 (en) * 1998-11-23 2001-12-25 International Business Machines Corporation Method of making high density integral test probe
JP2006506657A (ja) * 2002-03-14 2006-02-23 エスエーイー・マグネティクス（エイチ・ケイ）リミテッド 光ファイバーとの半導体装置の能動的光学整合のための一体化プラットホーム
JP2006253014A (ja) * 2005-03-11 2006-09-21 Tyco Electronics Amp Kk ピッチ変換コネクタおよびその製造方法
US8159059B2 (en) * 2006-08-25 2012-04-17 Kyocera Corporation Microelectromechanical device and method for manufacturing the same
TWI352406B (en) * 2006-11-16 2011-11-11 Nan Ya Printed Circuit Board Corp Embedded chip package with improved heat dissipati
US8110912B2 (en) * 2008-07-31 2012-02-07 Infineon Technologies Ag Semiconductor device
US9620934B2 (en) * 2010-08-31 2017-04-11 Avago Technologies General Ip (Singapore) Pte. Ltd. Flip-chip assembly comprising an array of vertical cavity surface emitting lasers (VCSELs)
US9188751B2 (en) * 2010-08-31 2015-11-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Flip-chip assembly comprising an array of vertical cavity surface emitting lasers (VCSELSs), and an optical transmitter assembly that incorporates the flip-chip assembly
WO2016011172A1 (en) * 2014-07-16 2016-01-21 Chirp Microsystems Piezoelectric micromachined ultrasonic transducers using two bonded substrates
US9842789B2 (en) * 2015-05-11 2017-12-12 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
TWI570854B (zh) * 2015-08-10 2017-02-11 頎邦科技股份有限公司 具中空腔室之半導體封裝結構及其下基板及製程
CN105514071B (zh) * 2016-01-22 2019-01-25 中芯长电半导体（江阴）有限公司 一种扇出型芯片的封装方法及封装结构
KR102019351B1 (ko) * 2016-03-14 2019-09-09 삼성전자주식회사 전자 부품 패키지 및 그 제조방법
CN109037082B (zh) * 2018-07-19 2021-01-22 通富微电子股份有限公司 封装结构及其形成方法
CN108962772B (zh) * 2018-07-19 2021-01-22 通富微电子股份有限公司 封装结构及其形成方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102177580A (zh) * 2006-08-31 2011-09-07 Ati科技无限责任公司 具有封装剂保持结构的反转芯片半导体封装及条带
CN103383923A (zh) * 2012-03-08 2013-11-06 新科金朋有限公司 用于应用处理器和存储器集成的薄3d扇出嵌入式晶片级封装(ewlb)
CN103715104A (zh) * 2012-09-28 2014-04-09 新科金朋有限公司 在半导体管芯上形成支撑层的半导体器件和方法
CN104241217A (zh) * 2014-06-25 2014-12-24 中国科学院微电子研究所 一种芯片背面裸露的扇出型封装结构及制造方法
CN104681456A (zh) * 2015-01-27 2015-06-03 华进半导体封装先导技术研发中心有限公司 一种扇出型晶圆级封装方法
CN105206539A (zh) * 2015-09-01 2015-12-30 华进半导体封装先导技术研发中心有限公司 扇出型封装制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115849298A (zh) * 2023-01-18 2023-03-28 胜科纳米(苏州)股份有限公司 一种具有梳齿结构芯片的梳齿层去除方法

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