WO2017128567A1 - 双面扇出型晶圆级封装方法及封装结构 - Google Patents

双面扇出型晶圆级封装方法及封装结构 Download PDF

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WO2017128567A1
WO2017128567A1 PCT/CN2016/082830 CN2016082830W WO2017128567A1 WO 2017128567 A1 WO2017128567 A1 WO 2017128567A1 CN 2016082830 W CN2016082830 W CN 2016082830W WO 2017128567 A1 WO2017128567 A1 WO 2017128567A1
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layer
double
wafer level
wiring layer
electrode
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PCT/CN2016/082830
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English (en)
French (fr)
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蔡奇风
林正忠
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中芯长电半导体（江阴）有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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Definitions

  • the invention belongs to the field of semiconductor packaging, and in particular relates to a double-sided fan-out wafer level packaging method and a package structure.
  • Fan-out Wafer Level Package is an embedded chip packaging method for wafer level processing. It is a kind of input/output port (I/O) and integration flexibility. One of the better advanced packaging methods. Fan-out wafer-level packaging has its unique advantages over conventional wafer-level packaging: 1I/O pitch is flexible, independent of chip size; 2 uses only effective die, product yield increases; 3 has flexible 3D The package path, that is, the pattern of any array can be formed on the top; 4 has better electrical and thermal properties; 5 high frequency application; 6 easy to achieve high density wiring in the rewiring layer (RDL).
  • I/O input/output port
  • Fan-out wafer-level packaging has its unique advantages over conventional wafer-level packaging: 1I/O pitch is flexible, independent of chip size; 2 uses only effective die, product yield increases; 3 has flexible 3D The package path, that is, the pattern of any array can be formed on the top; 4 has better electrical and thermal properties; 5 high frequency application; 6 easy to achieve high density wiring in the rewiring layer (RDL
  • the existing fan-out wafer level packaging method generally comprises: providing a carrier, forming an adhesive layer on the surface of the carrier; mounting the semiconductor chip face up on the surface of the adhesive layer; coating the dielectric layer; lithography, electroplating Rewiring layer (RDL); plastic film is encapsulated in a layer of plastic sealing material by injection molding process; plastic sealing, opening; lithography, electroplating out the metal layer under the ball; ball reflow, forming an array of solder balls; removing the carrier.
  • RDL electroplating Rewiring layer
  • the double-sided fan-out chip packaging technology can simultaneously package the chips on the two surfaces of the same substrate, which can greatly improve the integration of the device and reduce the cost. At the same time, through the application of the carrier, reducing the warpage and improving the yield.
  • the invention provides a double-sided fan-out wafer level packaging method and package structure which is simple in steps, low in cost, and effectively improves the integration degree. necessary.
  • the present invention aims to provide a novel double-sided fan-out wafer level packaging method and package structure for improving the integration degree of the packaged products in the prior art and reducing the cost.
  • the present invention provides a double-sided fan-out wafer level packaging method, comprising the steps of: step 1), providing a substrate, and forming a first rewiring layer on the first surface of the substrate; Step 2) attaching a first device to the first rewiring layer and electrically connecting the first device to the first rewiring layer; and step 3), making a first on the first rewiring layer Electrode bump; step 4), performing a molding process on the first device, exposing the first electrode bump after molding; and step 5) bonding the side exposing the first electrode bump to a carrier based on the adhesive layer Step 6), forming a via electrode penetrating between the first rewiring layer and the second surface of the substrate in the substrate; and step 7), making a second re-surface on the second surface of the substrate Wiring layer and implementing each via electrode and second weight Electrical connection of the new wiring layer; step 8), attaching the second device to the second rewiring layer, and implementing electrical connection between the second device
  • the first re-wiring layer and the second re-wiring layer include a patterned dielectric layer and a patterned metal wiring layer.
  • the material of the dielectric layer comprises one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorine-containing glass.
  • the material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
  • the first device and the second device include one or a combination of a bare chip and a packaged chip.
  • step 3) includes: step 3-1), forming a copper pillar on the first rewiring layer; step 3-2), Forming a nickel layer on the copper pillar; step 3-3), forming a solder metal on the nickel layer, and performing high temperature reflow to form a solder ball to complete the preparation of the first electrode bump.
  • the curing materials used in the molding process of step 4) and step 10) include one of polyimide, silica gel and epoxy resin. .
  • the material of the carrier includes one or more composite materials of silicon, glass, silicon oxide, ceramic, polymer, and metal. .
  • the adhesive layer comprises a separation layer, which can be removed by UV irradiation or laser in step 10) to separate the device from the carrier.
  • the remaining adhesive layer is removed by a chemical agent such that the adhesive layer is separated from the first bump.
  • step 9) includes: step 9-1), forming a copper pillar on the second rewiring layer; step 9-2), Forming a nickel layer on the copper pillar; step 9-3), forming a solder metal on the nickel layer, and performing high temperature reflow to form a solder ball to complete the preparation of the second electrode bump.
  • the present invention also provides a double-sided fan-out type wafer level package structure, comprising: a substrate, a first surface of the substrate is formed with a first rewiring layer, a second surface is formed with a second rewiring layer, and a via electrode connecting the first re-wiring layer and the second re-wiring layer is formed in the substrate; the first device is fixed to the first re-wiring layer and electrically connected to the first re-wiring layer; An electrode bump formed on the first rewiring layer; a first curing material covering the surface of the first device and exposing the first electrode bump; and a second device fixed to the first Second rewiring a layer and electrically connected to the second rewiring layer; a second electrode bump formed on the second rewiring layer; a second curing material covering the surface of the second device and exposing the Second electrode bump.
  • the first re-wiring layer and the second re-wiring layer include a patterned dielectric layer and a patterned metal wiring layer.
  • the material of the dielectric layer comprises epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass.
  • epoxy resin silica gel
  • PI polyimide
  • PBO polyimide
  • BCB silicon oxide
  • phosphosilicate glass and fluorine-containing glass.
  • fluorine-containing glass One or a combination of two or more.
  • the material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
  • the first device and the second device comprise one or a combination of a bare chip and a packaged chip.
  • the cured material includes one of polyimide, silica gel, and epoxy resin.
  • the first electrode bump and the second electrode bump include a copper pillar, a nickel layer formed on the copper pillar, and a nickel layer formed on the copper pillar The solder ball.
  • the double-sided fan-out wafer level packaging method and package structure of the present invention have the following beneficial effects:
  • the rewiring layer is fabricated before the chip is attached, so that the chip shift during the molding process can be avoided, and the connection abnormality is avoided;
  • FIG. 15 are schematic diagrams showing the steps of the steps of the double-sided fan-out wafer level packaging method of the present invention, wherein FIG. 15 is a schematic structural view of the double-sided fan-out wafer level package structure of the present invention. .
  • the embodiment provides a double-sided fan-out wafer level packaging method, including the following steps:
  • step 1) is performed to provide a substrate 101, and a first re-wiring layer 102 is formed on the first surface of the substrate 101.
  • the substrate 101 may be made of a material such as silicon, silicon dioxide, BCB board, ceramic, glass, polymer, or the like.
  • the first re-wiring layer 102 includes a patterned dielectric layer and a patterned metal wiring layer.
  • the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass.
  • the material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
  • step 2) is then performed to attach the first device to the first re-wiring layer 102 and to electrically connect the first device to the first re-wiring layer 102.
  • the first device includes one or more combinations of a bare chip and a packaged chip.
  • the first device includes two devices, wherein one device is a bare chip 103, and the other device is a packaged chip 104, and the first device may be a device structure that implements any function. It is not limited to the examples listed here.
  • step 3 is followed to form a first electrode bump 105 on the first rewiring layer 102.
  • step 3) includes:
  • Step 3-1) forming a copper pillar on the first rewiring layer 102;
  • Step 3-2 forming a nickel layer on the copper pillar
  • solder metal is formed on the nickel layer, and high temperature reflow is performed to form a solder ball to complete the preparation of the first electrode bump 105.
  • the solder metal is a silver tin alloy.
  • step 4 the first device is subjected to a molding process, after exposing the first electrode bump 105.
  • the exposure of the first electrode bump 105 is realized to save the subsequent grinding to expose the first electrode bump, which greatly saves the process cost.
  • the first cured material 106 employed in the molding process of this step includes one of polyimide, silica gel, and epoxy resin.
  • the molding process may include a spin coating process, an injection molding process, a compression molding process, a printing process, a transfer molding process, a liquid sealant curing molding process, a vacuum lamination process, and the like.
  • a compression molding process is used herein.
  • step 5 is followed by bonding the side on which the first electrode bump 105 is exposed to a carrier 108 based on the adhesive layer 107.
  • the material of the carrier 108 includes one or more composite materials of silicon, glass, silicon oxide, ceramic, polymer, and metal.
  • the adhesive layer 107 may be a tape, an epoxy resin, a UV adhesive, or the like, and the subsequent removal process may be exposure, laser ablation, solution etching, or the like.
  • the adhesive layer 107 includes a separation layer.
  • the separation layer is removed by laser ablation, and the remaining adhesive layer is removed by a chemical reagent to realize the first electrode. The separation of the bumps 105.
  • step 6 is then performed to thin the substrate 101 and form a through-hole in the substrate 101.
  • the step includes:
  • first step 6-1 the substrate 101 is thinned by a grinding method
  • step 6-2 is performed to form a via hole in the base by photolithography-etching or laser processing;
  • step 6-3) is followed to deposit a metal material such as copper, aluminum, or the like in the through hole;
  • the final step 6-4) is performed to remove excess metal material on the surface of the substrate 101, and it may be a polishing method or an etching method.
  • step 7) is followed to form a second re-wiring layer 110 on the second surface of the substrate 101, and electrical connection between each via electrode 109 and the second re-wiring layer 110 is achieved.
  • the second re-wiring layer 110 includes a patterned dielectric layer and a patterned metal wiring layer.
  • the material of the dielectric layer includes one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass.
  • the material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
  • step 8 is then performed to attach the second device to the second re-wiring layer 110 and to electrically connect the second device to the second re-wiring layer 110.
  • the second device includes one or more combinations of bare chips and packaged chips.
  • the second device includes two different devices, one being a bare chip 112 and the other being a packaged chip 111, wherein the second device and the first device may be the same
  • the chip can also be a different chip, and can be integrated according to the needs of different functional devices to meet different application requirements.
  • step 9) is then performed to form a second electrode bump 113 on the second rewiring layer 110.
  • step 9) includes:
  • Step 9-1 forming a copper pillar on the second rewiring layer 110;
  • Step 9-2 forming a nickel layer on the copper pillar
  • solder metal is formed on the nickel layer, and high temperature reflow is performed to form a solder ball to complete the preparation of the second electrode bump 113.
  • the solder metal is a silver tin alloy.
  • step 10 is followed to perform a molding process on the second device, and the second electrode bump 113 is exposed after molding.
  • the exposure of the second electrode bump 113 is realized to save the subsequent grinding to expose the second electrode bump, which greatly saves the process cost.
  • the second cured material 114 used in the molding process includes polyimide, silica gel, and epoxy resin.
  • polyimide polyimide
  • silica gel silica gel
  • epoxy resin epoxy resin
  • step 11) is performed to remove the adhesive layer 107 and the carrier 108.
  • the adhesive layer 107 comprises a separate layer, the separation layer is removed by laser ablation, and the remaining adhesive layer is removed with a chemical agent to separate the carrier from the first electrode bumps 105.
  • the embodiment further provides a double-sided fan-out wafer level package structure, including: a substrate 101, a first surface of the substrate 101 is formed with a first re-wiring layer 102, and a second surface is formed.
  • a second re-wiring layer 110 There is a second re-wiring layer 110, and a via electrode 109 connecting the first re-wiring layer 102 and the second re-wiring layer 110 is formed in the substrate 101; a first device is fixed to the first rewiring The layer 102 is electrically connected to the first rewiring layer 102; the first electrode bump 105 is formed on the first rewiring layer 102; and the first curing material 106 covers the surface of the first device.
  • the second device is fixed to the second re-wiring layer 110 and electrically connected to the second re-wiring layer 110; the second electrode bump 113 is formed in the On the second rewiring layer 110; a second curing material 114 covering the surface of the second device and exposing the second electrode bump 113.
  • the first re-wiring layer 102 and the second re-wiring layer 110 include a patterned dielectric layer and a patterned metal wiring layer.
  • the material of the dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorine-containing glass.
  • the material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
  • the first device and the second device comprise one or a combination of a bare chip and a packaged chip.
  • the cured material includes one of polyimide, silica gel, and epoxy resin.
  • the first electrode bump 105 and the second electrode bump 113 include a copper pillar, a nickel layer formed on the copper pillar, and a solder ball.
  • the double-sided fan-out wafer level packaging method and package structure of the present invention have the following beneficial effects:
  • the rewiring layer is fabricated before the chip is attached, so that the chip shift during the molding process can be avoided, and the connection abnormality is avoided;
  • the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种双面扇出型晶圆级封装方法及封装结构，包括基底、第一重新布线层、第二重新布线层、通孔电极、第一器件、第一电极凸块、第一固化材料、第二器件、第二电极凸块以及第二固化材料，所述第一、第二重新布线层通过通孔电极连接，各电极露出于固化材料表面。通过制作电极通孔实现双面器件的互连，并可实现多层封装结构的垂直互连，实现不同电子设备功能；重新布线层制作于芯片附着之前，避免芯片移位；将结构粘合于载体上，避免结构翘曲；用电极凸块作为互连引出，为多种不同器件的集成提供了保证；通过控制固化材料的厚度来控制电极凸块的引出，节省了固化材料的研磨工艺；通过双面扇出型封装，大大提高器件的集成度。

Description

双面扇出型晶圆级封装方法及封装结构 技术领域
本发明属于半导体封装领域，特别是涉及一种双面扇出型晶圆级封装方法及封装结构。
背景技术
扇出型晶圆级封装(Fan-out Wafer Level package，FOWLP)是一种晶圆级加工的嵌入式芯片封装方法，是目前一种输入/输出端口(I/O)较多、集成灵活性较好的先进封装方法之一。扇出型晶圆级封装相较于常规的晶圆级封装具有其独特的优点：①I/O间距灵活，不依赖于芯片尺寸；②只使用有效die，产品良率提高；③具有灵活的3D封装路径，即可以在顶部形成任意阵列的图形；④具有较好的电性能及热性能；⑤高频应用；⑥容易在重新布线层(RDL)中实现高密度布线。
现有的扇出型晶圆级封装方法一般为：提供载体，在载体表面形成粘合层；将半导体芯片正面朝上贴装于粘合层表面；涂布介电层；光刻、电镀出重新布线层(RDL)；采用注塑工艺将半导体芯片塑封于塑封材料层中；塑封研磨、开口；光刻、电镀出球下金属层；进行植球回流，形成焊球阵列；移除载体。而且，现有技术在成型工艺以及后续的焊料回流等工艺的过程中，容易出现翘曲、破裂等缺陷，从而降低封装产品的成品率。双面扇出型芯片封装技术能够将芯片同时封装于同一个基底的两个表面上，可以大大提高器件的集成度，降低成本。同时通过载体的应用，减少翘曲，提高成品率鉴于以上原因，提供一种步骤简单、低成本、且有效提高集成度，成品率的双面扇出型晶圆级封装方法及封装结构实属必要。
发明内容
鉴于以上所述现有技术的特点，本发明的目的在于提供一种新型双面扇出型晶圆级封装方法及封装结构，用于提高现有技术中封装成品的集成度，降低成本。
为实现上述目的及其他相关目的，本发明提供一种双面扇出型晶圆级封装方法，包括步骤：步骤1)，提供一基底，于所述基底第一表面制作第一重新布线层；步骤2)，将第一器件附着于所述第一重新布线层，并实现第一器件与第一重新布线层的电性连接；步骤3)，于所述第一重新布线层上制作第一电极凸块；步骤4)，对第一器件进行成型工艺，成型后露出所述第一电极凸块；步骤5)，基于粘合层将露出有第一电极凸块的一面粘合于一载体上；步骤6)，于所述基底中形成贯穿于所述第一重新布线层及基底的第二表面之间的通孔电极；步骤7)，于所述基底的第二表面制作第二重新布线层，并实现各通孔电极与第二重 新布线层的电性连接；步骤8)，将第二器件附着于所述第二重新布线层，并实现第二器件与第二重新布线层的电性连接；步骤9)，于所述第二重新布线层上制作第二电极凸块；步骤10)，对第二器件进行成型工艺，成型后露出所述第二电极凸块；步骤11)，去除所述粘合层以及载体。
作为本发明的双面扇出型晶圆级封装方法的一种优选方案，所述第一重新布线层以及第二重新布线层包括图形化的介质层以及图形化的金属布线层。
优选地，所述介质层的材料包括环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃，含氟玻璃中的一种或两种以上组合。
优选地，所述金属布线层的材料包括铜、铝、镍、金、银、钛中的一种或两种以上组合。
作为本发明的双面扇出型晶圆级封装方法的一种优选方案，所述第一器件以及第二器件包括裸芯片以及封装好的芯片中的一种或两种组合。
作为本发明的双面扇出型晶圆级封装方法的一种优选方案，步骤3)包括：步骤3-1)，于所述第一重新布线层上制作铜柱；步骤3-2)，于所述铜柱上制作镍层；步骤3-3)，于所述镍层上制作焊料金属，并进行高温回流形成焊料球，以完成第一电极凸块的制备。
作为本发明的双面扇出型晶圆级封装方法的一种优选方案，步骤4)及步骤10)的成型工艺所采用的固化材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。
作为本发明的双面扇出型晶圆级封装方法的一种优选方案，所述载体的材料包括硅、玻璃、氧化硅、陶瓷、聚合物以及金属中的一种或两种以上的复合材料。
作为本发明的双面扇出型晶圆级封装方法的一种优选方案，所述粘合层包含一层分离层，步骤10)中可以通过UV照射或激光将其去除，使得器件与载体分离；剩余的粘合层通过化学试剂去除，使得粘合层与第一凸块分离。
作为本发明的双面扇出型晶圆级封装方法的一种优选方案，步骤9)包括：步骤9-1)，于所述第二重新布线层上制作铜柱；步骤9-2)，于所述铜柱上制作镍层；步骤9-3)，于所述镍层上制作焊料金属，并进行高温回流形成焊料球，以完成第二电极凸块的制备。
本发明还提供一种双面扇出型晶圆级封装结构，包括：基底，所述基底的第一表面形成有第一重新布线层，第二表面形成有第二重新布线层，且所述基底中形成有连接所述第一重新布线层及第二重新布线层的通孔电极；第一器件，固定于所述第一重新布线层，且与第一重新布线层的电性连接；第一电极凸块，形成于所述第一重新布线层上；第一固化材料，覆盖于所述第一器件表面，且露出有所述第一电极凸块；第二器件，固定于所述第二重新布线 层，且与第二重新布线层的电性连接；第二电极凸块，形成于所述第二重新布线层上；第二固化材料，覆盖于所述第二器件表面，且露出有所述第二电极凸块。
作为本发明的双面扇出型晶圆级封装结构的一种优选方案，所述第一重新布线层以及第二重新布线层包括图形化的介质层以及图形化的金属布线层。
作为本发明的双面扇出型晶圆级封装结构的一种优选方案，所述介质层的材料包括环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃，含氟玻璃中的一种或两种以上组合。
作为本发明的双面扇出型晶圆级封装结构的一种优选方案，所述金属布线层的材料包括铜、铝、镍、金、银、钛中的一种或两种以上组合
作为本发明的双面扇出型晶圆级封装结构的一种优选方案，所述第一器件以及第二器件包括裸芯片以及封装好的芯片中的一种或两种组合。
作为本发明的双面扇出型晶圆级封装结构的一种优选方案，所述固化材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。
作为本发明的双面扇出型晶圆级封装结构的一种优选方案，所述第一电极凸块以及第二电极凸块包括铜柱、形成于所述铜柱上的镍层以及形成于所述焊料球。
如上所述，本发明的双面扇出型晶圆级封装方法及封装结构，具有以下有益效果：
1)通过在基底上制作电极通孔实现双面器件之间的互连，这种结构可以实现多层封装结构的垂直互连，实现不同的电子设备功能；
2)重新布线层制作于芯片附着之前，可以避免在成型过程中的芯片移位，避免连线异常；
3)将结构粘合于载体上，避免了制作重新布线层及焊料球的过程中造成的结构翘曲、破裂等缺陷；
4)采用电极凸块作为互连引出，为多种不同器件的集成提供了有效的保证；
5)通过控制固化材料的厚度来控制电极凸块的引出，节省了固化材料的研磨等工艺。
附图说明
图1～图15显示为本发明的双面扇出型晶圆级封装方法各步骤所呈现的结构示意图，其中，图15显示为本发明的双面扇出型晶圆级封装结构的结构示意图。
元件标号说明
101    基底
102    第一重新布线层
103    裸芯片
104    封装好的芯片
105    第一电极凸块
106    第一固化材料
107    粘合层
108    载体
109    通孔电极
110    第二重新布线层
111    封装好的芯片
112    裸芯片
113    第二电极凸块
114    第二固化材料
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1～图15。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
如图1～图15所示，本实施例提供一种双面扇出型晶圆级封装方法，包括步骤：
如图1～图2所示，首先进行步骤1)，提供一基底101，于所述基底101第一表面制作第一重新布线层102。
作为示例，所述基底101可以为硅、二氧化硅、BCB板、陶瓷、玻璃、聚合物等材料制成。
作为示例，所述第一重新布线层102包括图形化的介质层以及图形化的金属布线层。所述介质层的材料包括环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃，含氟玻璃中的 一种。所述金属布线层的材料包括铜、铝、镍、金、银、钛中的一种或两种以上组合。
如图3所示，然后进行步骤2)，将第一器件附着于所述第一重新布线层102，并实现第一器件与第一重新布线层102的电性连接。
作为示例，所述第一器件包括裸芯片以及封装好的芯片中的一种或多种组合。在本实施例中，所述第一器件包括两种器件，其中，一种器件为裸芯片103，另一种器件为封装好的芯片104，所述第一器件可以是实现任意功能的器件结构，并不限于此处所列举的示例。
如图4所示，接着进行步骤3)，于所述第一重新布线层102上制作第一电极凸块105。
作为示例，步骤3)包括：
步骤3-1)，于所述第一重新布线层102上制作铜柱；
步骤3-2)，于所述铜柱上制作镍层；
步骤3-3)，于所述镍层上制作焊料金属，并进行高温回流形成焊料球，以完成第一电极凸块105的制备。作为示例，所述焊料金属为银锡合金。
如图5所示，然后进行步骤4)，对第一器件进行成型工艺，成型后露出所述第一电极凸块105.
作为示例，通过控制所述成型工艺的第一固化材料的厚度，实现所述第一电极凸块105的露出，以节省后续研磨以将第一电极凸块露出的工艺，大大节约了工艺成本。
作为示例，本步骤的成型工艺所采用的第一固化材料106包括聚酰亚胺、硅胶以及环氧树脂中的一种。
作为示例，成型工艺可以包括旋涂工艺、注塑工艺、压缩成型工艺、印刷工艺、传递模塑工艺、液体密封剂固化成型工艺、以及真空层压工艺等。作为示例，此处使用压缩成型工艺。
如图6所示，接着进行步骤5)，基于粘合层107将露出有第一电极凸块105的一面粘合于一载体108上。
作为示例，所述载体108的材料包括硅、玻璃、氧化硅、陶瓷、聚合物以及金属中的一种或两种以上的复合材料。
作为示例，所述粘合层107可以为胶带、环氧树脂、UV粘合胶等，后续的去除工艺可以为曝光法、激光烧蚀、溶液腐蚀等。在本实施例中，所述粘合层107包括一分离层，在后续的步骤10)中，采用激光烧蚀去除分离层，再用化学试剂去除剩余的粘合层以实现其与第一电极凸块105的分离。
如图7～图10所示，然后进行步骤6)，减薄所述基底101，于所述基底101中形成贯穿 于所述第一重新布线层102及基底101的第二表面之间的通孔电极109。
具体地，该步骤包括：
如图7所示，首先进行步骤6-1)，通过研磨方法减薄所述基底101；
如图8所示，然后进行步骤6-2)，通过光刻-刻蚀或者是激光等方法于所述基地中形成通孔；
如图9所示，接着进行步骤6-3)，于所述通孔内沉积金属材料，如铜、铝等；
如图10所示，最后进行步骤6-4)，去除基底101表面多余的金属材料，可以采用为抛光法或者腐蚀法等。
如图11所示，接着进行步骤7)，于所述基底101的第二表面制作与第二重新布线层110，并实现各通孔电极109与第二重新布线层110的电性连接。
作为示例，所述第二重新布线层110包括图形化的介质层以及图形化的金属布线层。所述介质层的材料包括环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃，含氟玻璃中的一种。所述金属布线层的材料包括铜、铝、镍、金、银、钛中的一种或两种以上组合。
如图12所示，然后进行步骤8)，将第二器件附着于所述第二重新布线层110，并实现第二器件与第二重新布线层110的电性连接。
作为示例，所述第二器件包括裸芯片以及封装好的芯片中的一种或多种组合。在本实施例中，所述第二器件包括两种不同的器件，一种为裸芯片112，另一种为封装好的芯片111，其中，所述第二器件与第一器件可以为相同的芯片，也可以为不同的芯片，可以依据需要选择不同功能的器件进行集成，以满足不同的应用需求。
如图13所示，然后进行步骤9)，于所述第二重新布线层110上制作第二电极凸块113。
作为示例，步骤9)包括：
步骤9-1)，于所述第二重新布线层110上制作铜柱；
步骤9-2)，于所述铜柱上制作镍层；
步骤9-3)，于所述镍层上制作焊料金属，并进行高温回流形成焊料球，以完成第二电极凸块113的制备。在本实施例中，所述焊料金属为银锡合金。
如图14所示，接着进行步骤10)，对第二器件进行成型工艺，成型后露出所述第二电极凸块113。
作为示例，通过控制所述成型工艺的第二固化材料的厚度，实现所述第二电极凸块113的露出，以节省后续研磨以将第二电极凸块露出的工艺，大大节约了工艺成本。
作为示例，成型工艺所采用的第二固化材料114包括聚酰亚胺、硅胶以及环氧树脂中的 一种。
如图15所示，最后进行步骤11)，去除所述粘合层107以及载体108。
作为示例，所述粘合层107包含一层分离层，采用激光烧蚀去除分离层，再用化学试剂去除剩余的粘合层，使得载体与第一电极凸块105分离。如图15所示，本实施例还提供一种双面扇出型晶圆级封装结构，包括：基底101，所述基底101的第一表面形成有第一重新布线层102，第二表面形成有第二重新布线层110，且所述基底101中形成有连接所述第一重新布线层102及第二重新布线层110的通孔电极109；第一器件，固定于所述第一重新布线层102，且与第一重新布线层102的电性连接；第一电极凸块105，形成于所述第一重新布线层102上；第一固化材料106，覆盖于所述第一器件表面，且露出有所述第一电极凸块105；第二器件，固定于所述第二重新布线层110，且与第二重新布线层110的电性连接；第二电极凸块113，形成于所述第二重新布线层110上；第二固化材料114，覆盖于所述第二器件表面，且露出有所述第二电极凸块113。
作为示例，所述第一重新布线层102以及第二重新布线层110包括图形化的介质层以及图形化的金属布线层。
作为示例，所述介质层的材料包括环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃，含氟玻璃中的一种或两种以上组合。
作为示例，所述金属布线层的材料包括铜、铝、镍、金、银、钛中的一种或两种以上组合。
作为示例，所述第一器件以及第二器件包括裸芯片以及封装好的芯片中的一种或两种组合。
作为示例，所述固化材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。
作为示例，所述第一电极凸块105以及第二电极凸块113包括铜柱、形成于所述铜柱上的镍层以及形成于所述焊料球。
如上所述，本发明的双面扇出型晶圆级封装方法及封装结构，具有以下有益效果：
1)通过在基底101上制作电极通孔实现双面器件之间的互连，这种结构可以实现多层封装结构的垂直互连，实现不同的电子设备功能；
2)重新布线层制作于芯片附着之前，可以避免在成型过程中的芯片移位，避免连线异常；
3)将结构粘合于载体108上，避免了制作重新布线层及焊料球的过程中造成的结构翘曲、破裂等缺陷；
4)采用电极凸块作为互连引出，为多种不同器件的集成提供了有效的保证；
5)通过控制固化材料的厚度来控制电极凸块的引出，节省了固化材料的研磨等工艺。
所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (17)

  1. 一种双面扇出型晶圆级封装方法，其特征在于，包括步骤：
    步骤1)，提供一基底，于所述基底第一表面制作第一重新布线层；
    步骤2)，将第一器件附着于所述第一重新布线层，并实现第一器件与第一重新布线层的电性连接；
    步骤3)，于所述第一重新布线层上制作第一电极凸块；
    步骤4)，对第一器件进行成型工艺，成型后露出所述第一电极凸块；
    步骤5)，基于粘合层将露出有第一电极凸块的一面粘合于一载体上；
    步骤6)，于所述基底中形成贯穿于所述第一重新布线层及基底的第二表面之间的通孔电极；
    步骤7)，于所述基底的第二表面制作第二重新布线层，并实现各通孔电极与第二重新布线层的电性连接；
    步骤8)，将第二器件附着于所述第二重新布线层，并实现第二器件与第二重新布线层的电性连接；
    步骤9)，于所述第二重新布线层上制作第二电极凸块；
    步骤10)，对第二器件进行成型工艺，成型后露出所述第二电极凸块；
    步骤11)，去除所述粘合层以及载体。
  2. 根据权利要求1所述的双面扇出型晶圆级封装方法，其特征在于：所述第一重新布线层以及第二重新布线层包括图形化的介质层以及图形化的金属布线层。
  3. 根据权利要求2所述的双面扇出型晶圆级封装方法，其特征在于：所述介质层的材料包括环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃，含氟玻璃中的一种或两种以上组合。
  4. 根据权利要求2所述的双面扇出型晶圆级封装方法，其特征在于：所述金属布线层的材料包括铜、铝、镍、金、银、钛中的一种或两种以上组合。
  5. 根据权利要求1所述的双面扇出型晶圆级封装方法，其特征在于：所述第一器件以及第二器件包括裸芯片以及封装好的芯片中的一种或两种组合。
  6. 根据权利要求1所述的双面扇出型晶圆级封装方法，其特征在于：步骤3)包括：
    步骤3-1)，于所述第一重新布线层上制作铜柱；
    步骤3-2)，于所述铜柱上制作镍层；
    步骤3-3)，于所述镍层上制作焊料金属，并进行高温回流形成焊料球，以完成第一电极凸块的制备。
  7. 根据权利要求1所述的双面扇出型晶圆级封装方法，其特征在于：步骤4)及步骤10)的成型工艺所采用的固化材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。
  8. 根据权利要求1所述的双面扇出型晶圆级封装方法，其特征在于：所述载体的材料包括硅、玻璃、氧化硅、陶瓷、聚合物以及金属中的一种或两种以上的复合材料。
  9. 根据权利要求1所述的双面扇出型晶圆级封装方法，其特征在于：所述粘合层包含一层分离层，步骤10)中可以通过UV照射或激光将其去除，使得器件与载体分离；剩余的粘合层通过化学试剂去除，使得粘合层与第一凸块分离。
  10. 根据权利要求1所述的双面扇出型晶圆级封装方法，其特征在于：步骤9)包括：
    步骤9-1)，于所述第二重新布线层上制作铜柱；
    步骤9-2)，于所述铜柱上制作镍层；
    步骤9-3)，于所述镍层上制作焊料金属，并进行高温回流形成焊料球，以完成第二电极凸块的制备。
  11. 一种双面扇出型晶圆级封装结构，其特征在于，包括：
    基底，所述基底的第一表面形成有第一重新布线层，第二表面形成有第二重新布线层，且所述基底中形成有连接所述第一重新布线层及第二重新布线层的通孔电极；
    第一器件，固定于所述第一重新布线层，且与第一重新布线层的电性连接；
    第一电极凸块，形成于所述第一重新布线层上；
    第一固化材料，覆盖于所述第一器件表面，且露出有所述第一电极凸块；
    第二器件，固定于所述第二重新布线层，且与第二重新布线层的电性连接；
    第二电极凸块，形成于所述第二重新布线层上；
    第二固化材料，覆盖于所述第二器件表面，且露出有所述第二电极凸块。
  12. 根据权利要求11所述的双面扇出型晶圆级封装结构，其特征在于：所述第一重新布线层以及第二重新布线层包括图形化的介质层以及图形化的金属布线层。
  13. 根据权利要求12所述的双面扇出型晶圆级封装结构，其特征在于：所述介质层的材料包括环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃，含氟玻璃中的一种或两种以上组合。
  14. 根据权利要求12所述的双面扇出型晶圆级封装结构，其特征在于：所述金属布线层的材料包括铜、铝、镍、金、银、钛中的一种或两种以上组合。
  15. 根据权利要求11所述的双面扇出型晶圆级封装结构，其特征在于：所述第一器件以及第二器件包括裸芯片以及封装好的芯片中的一种或两种组合。
  16. 根据权利要求11所述的双面扇出型晶圆级封装结构，其特征在于：所述固化材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。
  17. 根据权利要求11所述的双面扇出型晶圆级封装结构，其特征在于：所述第一电极凸块以及第二电极凸块包括铜柱、形成于所述铜柱上的镍层以及形成于所述焊料球。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107452689A (zh) * 2017-09-14 2017-12-08 厦门大学 三维系统级封装应用的内嵌扇出型硅转接板及制作方法
CN108389822A (zh) * 2018-01-31 2018-08-10 浙江卓晶科技有限公司 一种三维扇出型集成封装结构及其封装工艺
CN109473765A (zh) * 2018-12-21 2019-03-15 中芯长电半导体（江阴）有限公司 三维封装天线及其封装方法
CN113130420A (zh) * 2021-03-19 2021-07-16 南通越亚半导体有限公司 一种嵌埋封装结构及其制造方法
CN113363166A (zh) * 2020-03-04 2021-09-07 力成科技股份有限公司 扇出型堆迭式半导体封装结构的多层模封方法
CN113725153A (zh) * 2021-08-31 2021-11-30 中国电子科技集团公司第五十八研究所 多层多芯片扇出型三维集成封装方法及结构

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105514087A (zh) * 2016-01-26 2016-04-20 中芯长电半导体（江阴）有限公司 双面扇出型晶圆级封装方法及封装结构
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CN108231722A (zh) * 2016-12-21 2018-06-29 贵州振华风光半导体有限公司 高密度表贴式半导体集成电路的集成方法
WO2018129908A1 (zh) * 2017-01-13 2018-07-19 中芯长电半导体（江阴）有限公司 一种双面扇出型晶圆级封装方法及封装结构
CN106960825A (zh) * 2017-03-08 2017-07-18 华进半导体封装先导技术研发中心有限公司 一种基于硅转接板的双面扇出封装结构及封装方法
CN107123645A (zh) * 2017-05-11 2017-09-01 王家恒 扇出型集成封装结构及其制作方法、终端设备
US10283474B2 (en) 2017-06-30 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
CN107611152B (zh) * 2017-09-05 2020-02-04 中芯长电半导体（江阴）有限公司 背照式cmos传感器的封装方法
CN107507821A (zh) * 2017-09-05 2017-12-22 中芯长电半导体（江阴）有限公司 集成图像传感器芯片及逻辑芯片的封装结构及封装方法
CN107644867A (zh) * 2017-09-07 2018-01-30 维沃移动通信有限公司 一种PoP封装件及其制作方法
CN107622957B (zh) * 2017-09-25 2019-11-01 江苏长电科技股份有限公司 双面SiP的三维封装结构的制造方法
CN107749411B (zh) * 2017-09-25 2019-11-01 江苏长电科技股份有限公司 双面SiP的三维封装结构
KR101963293B1 (ko) 2017-11-01 2019-03-28 삼성전기주식회사 팬-아웃 반도체 패키지
CN109987572A (zh) * 2017-12-29 2019-07-09 中芯长电半导体（江阴）有限公司 一种mems晶圆级封装结构及方法
CN109559996A (zh) * 2018-11-13 2019-04-02 无锡中微高科电子有限公司 一种3D高密度互联的PoP塑封器件制备方法
CN111348613B (zh) * 2018-12-21 2023-12-26 中芯集成电路（宁波）有限公司 封装方法及封装结构
CN109742056A (zh) * 2019-02-18 2019-05-10 中芯长电半导体（江阴）有限公司 天线的封装结构及封装方法
CN109860156A (zh) * 2019-04-02 2019-06-07 中芯长电半导体（江阴）有限公司 天线封装结构及封装方法
CN114566482A (zh) * 2022-04-28 2022-05-31 武汉大学 一种三维扇出封装结构及其制备方法
CN115148612A (zh) * 2022-09-05 2022-10-04 盛合晶微半导体(江阴)有限公司 一种扇出型系统级封装结构及制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202871783U (zh) * 2012-08-31 2013-04-10 江阴长电先进封装有限公司 一种芯片嵌入式堆叠圆片级封装结构
CN204332941U (zh) * 2015-01-27 2015-05-13 江阴长电先进封装有限公司 一种三维叠层封装结构
CN105514087A (zh) * 2016-01-26 2016-04-20 中芯长电半导体（江阴）有限公司 双面扇出型晶圆级封装方法及封装结构

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5496445B2 (ja) * 2007-06-08 2014-05-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7858441B2 (en) * 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
US20110186960A1 (en) * 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202871783U (zh) * 2012-08-31 2013-04-10 江阴长电先进封装有限公司 一种芯片嵌入式堆叠圆片级封装结构
CN204332941U (zh) * 2015-01-27 2015-05-13 江阴长电先进封装有限公司 一种三维叠层封装结构
CN105514087A (zh) * 2016-01-26 2016-04-20 中芯长电半导体（江阴）有限公司 双面扇出型晶圆级封装方法及封装结构

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107452689A (zh) * 2017-09-14 2017-12-08 厦门大学 三维系统级封装应用的内嵌扇出型硅转接板及制作方法
CN108389822A (zh) * 2018-01-31 2018-08-10 浙江卓晶科技有限公司 一种三维扇出型集成封装结构及其封装工艺
CN109473765A (zh) * 2018-12-21 2019-03-15 中芯长电半导体（江阴）有限公司 三维封装天线及其封装方法
CN113363166A (zh) * 2020-03-04 2021-09-07 力成科技股份有限公司 扇出型堆迭式半导体封装结构的多层模封方法
CN113130420A (zh) * 2021-03-19 2021-07-16 南通越亚半导体有限公司 一种嵌埋封装结构及其制造方法
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CN113725153B (zh) * 2021-08-31 2023-10-27 中国电子科技集团公司第五十八研究所 多层多芯片扇出型三维集成封装方法及结构

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