CN108231722A - 高密度表贴式半导体集成电路的集成方法 - Google Patents

高密度表贴式半导体集成电路的集成方法 Download PDF

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CN108231722A
CN108231722A CN201611188497.XA CN201611188497A CN108231722A CN 108231722 A CN108231722 A CN 108231722A CN 201611188497 A CN201611188497 A CN 201611188497A CN 108231722 A CN108231722 A CN 108231722A
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semiconductor integrated
chip
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胡锐
杨成刚
黄华
苏贵东
唐拓
刘学林
路兰艳
杨晓琴
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Guizhou Zhenhua Fengguang Semiconductor Co Ltd
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    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Abstract

高密度表贴式半导体集成电路的集成方法，该方法是在预先烧结成型的陶瓷管帽外表面用涂覆金属浆料烧结、化学电镀或真空镀膜的方式形成金属层；用低温共烧陶瓷工艺及厚膜印刷与烧结工艺制作管基底座及管基管帽，在其上分别形成半导体集成电路芯片键合区、表面金属层，在下陶瓷基片的背面制作对外电气引脚等结构；再进行半导体集成电路芯片的倒装键合，接着将两基片，用表贴式集成法芯片面对芯片面地装接在一起，对外电气引脚从下层陶瓷基片的背面引出。本发明解决了原有的半导体集成电路在装备系统的小型化、集成化和轻便化等应用领域受限的难题，广泛应用于多种工业领域，特别适用于装备系统小型化、高频、高可靠的领域，具有广阔的市场前景和应用空间。

Description

高密度表贴式半导体集成电路的集成方法
技术领域
本发明涉及半导体集成电路，更进一步来说，涉及高密度表贴式半导体集成电路的集成方法。
背景技术
原有半导体集成电路的集成技术中，将半导体集成电路芯片封装在金属管基和金属管帽内，或封装在陶瓷管基和陶瓷管帽内，先将半导体集成电路芯片装贴在管基上，再采用键合丝（金丝或硅铝丝）进行芯片与管脚的引线键合，完成整个电器连接，最后将管基和管帽进行密封而成。现有技术存在的主要问题是：集成电路封装内部仅能进行单层封装，不能充分利用封装空间进行更多集成电路芯片的封装；不利于装备系统的小型化、集成化和轻便化。
中国专利数据库中涉及半导体集成电路的申请件有上千件，从2015年以来的就有57件，说明该领域技术进步非常快。例如： 2015209928947号《一种抗干扰半导体集成电路》、2015209932124号《一种抗干扰抗腐蚀半导体集成电路》、 201510399162.1 号《一种高密度集成电路封装结构》、2015201161706号《集成电路的虚拟图案以及半导体集成电路》等。然而迄今为止，尚无高密度表贴式半导体集成电路集成方法的申请件。
发明内容
本发明旨在提供高密度表贴式半导体集成电路的集成方法，通过半导体集成电路的高密度集成，促进装备系统的小型化、集成化和轻便化。
发明人提供的高密度表贴式半导体集成电路的集成方法是：在预先烧结成型的陶瓷管帽的外表面，采用涂覆金属浆料烧结、化学电镀或真空镀膜的方式形成所需金属层；采用低温共烧陶瓷工艺（LTCC工艺）及厚膜印刷与烧结工艺制作管基底座及管基管帽，在管基底座及管基管帽上分别形成半导体集成电路芯片键合区、表面金属层，在下层陶瓷基片的背面制作对外电气引脚等结构；再进行半导体集成电路芯片的倒装键合，接着将两片组装有半导体集成电路芯片的基片，用表贴式集成法芯片面对芯片面地装接在一起，对外电气引脚从下层陶瓷基片的背面引出，从而实现半导体集成电路的高密度集成。
上述对外电气连接端与陶瓷基片之间有金属焊盘。
本发明方法具有以下优点：①可以实现多个半导体集成电路芯片双层集成，实现高密度集成；②可集成更多的电路功能，实现系统集成；③实现表贴式安装，缩小装备体积，提升装备的高频性能；④提高装备系统的可靠性；⑤可扩展到其他电路模块的高密度集成。
本发明方法解决了原有的半导体集成电路在装备系统的小型化、集成化和轻便化等应用领域受限的难题，使用本发明的器件广泛应用于航天、航空、船舶、电子、通讯、医疗设备、工业控制等领域，特别适用于装备系统小型化、高频、高可靠的领域，具有广阔的市场前景和应用空间。
附图说明
图1为原有表贴式半导体集成电路结构示意图，图2为高密度表贴式半导体集成电路组装结构示意图，图3为高密度表贴式半导体集成电路结构示意图。
图中， 1为金属管基，2为金属底座，3为金属管脚，4为金属管帽，5为半导体集成电路芯片，6为键合丝，7为上陶瓷基片，8为上陶瓷基片金属焊盘，9为半导体集成电路芯片1，10为金属化通孔12的电气连接金属带，11为陶瓷加厚层，12为金属化通孔，13为下陶瓷基片，14为金属引脚，15为半导体集成电路芯片2，16为半导体集成电路芯片2的对外电气连接端，17为半导体集成电路芯片1的对外电气连接端，18为陶瓷基片的电气连接端。
具体实施方式
实施例 结构如图1的高密度表贴式半导体集成电路的集成工艺流程如下：
（1）陶瓷生瓷片、镀层材料的准备；
（2）采用现有技术中的低温共烧陶瓷工艺（LTCC工艺）及厚膜印刷与烧结工艺制作上陶瓷基片及下陶瓷基片，分别形成半导体集成电路芯片键合区、表面金属层，在下层陶瓷基片的背面制作对外电气引脚等结构，金属层材料为金浆料烧结而成；
（3）在上陶瓷基片、下陶瓷基片上分别组装相应的半导体集成电路芯片；
（4）将两片组装有半导体集成电路芯片的基片，采用表贴式集成的方法芯片面对芯片面地装接在一起，粘结材料为低熔点金属浆料再流化而成；
（5）性能测试；
（6）老化筛选测试、密封性检查；
（7）产品编号打印、包装入库。

Claims (2)

1.高密度表贴式半导体集成电路的集成方法，其特征在于在预先烧结成型的陶瓷管帽的外表面，采用涂覆金属浆料烧结、化学电镀或真空镀膜的方式形成所需金属层；采用低温共烧陶瓷工艺及厚膜印刷与烧结工艺制作管基底座及管基管帽，在管基底座及管基管帽上分别形成半导体集成电路芯片键合区、表面金属层，在下层陶瓷基片的背面制作对外电气引脚等结构；再进行半导体集成电路芯片的倒装键合，接着将两片组装有半导体集成电路芯片的基片，用表贴式集成法芯片面对芯片面地装接在一起，对外电气引脚从下层陶瓷基片的背面引出，从而实现半导体集成电路的高密度集成。
2.如权利要求1所述的集成方法，其特征在于所述电气连接端与上陶瓷基片和下陶瓷基片之间有金属焊盘。
CN201611188497.XA 2016-12-21 2016-12-21 高密度表贴式半导体集成电路的集成方法 Pending CN108231722A (zh)

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CN110690208A (zh) * 2019-10-08 2020-01-14 中国电子科技集团公司第二十四研究所 一种功率混合集成电路封装结构
CN111498791A (zh) * 2020-04-30 2020-08-07 青岛歌尔微电子研究院有限公司 微机电系统封装结构及其制作方法

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CN105514087A (zh) * 2016-01-26 2016-04-20 中芯长电半导体（江阴）有限公司 双面扇出型晶圆级封装方法及封装结构

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CN104157619A (zh) * 2014-08-22 2014-11-19 山东华芯半导体有限公司 一种新型PoP堆叠封装结构及其制造方法
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110690208A (zh) * 2019-10-08 2020-01-14 中国电子科技集团公司第二十四研究所 一种功率混合集成电路封装结构
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